[lld][ARM][2/3]Big Endian support - Word invariant support

[simpal01]

Summary

Changes:

• Adding BE32 big endian Support for Arm.
• Replace the writele and readle with their endian-aware versions.
• Adding test cases for the big-endian be32 arm configuration.
  
  Patch by: Milosz Plichta. This patch merges all the changes from this patch https://reviews.llvm.org/D140203 as well.

[peter.smith]

It will be worth adding to the description of the difference between BE32 and BE8. BE32 is the legacy way of handling big-endian on Arm systems prior to ArmV6. In this model all relocatable object files are BigEndian, and all the instructions and data are BigEndian. In ArmV6 the byte-invariant BE8 mode was added, in the output ELF file (executable/shared library) this is the same model as AArch64 where the ELF file and Data are big-endian but instructions are little-endian. In contrast to AArch64 relocatable object files are identical in BE8 and BE32, the linker is expected to endian reverse big-endian instructions from big-endian to little-endian. In modern Arm systems BE32 support has been removed, leaving only BE8. However BE32 is a necessary pre-requisite to support BE8.

For BE8 support we'll have to endian reverse the instructions. For non-SyntheticSections we'll have to use the mapping symbols to do that during or more likely after writeTo(). For SyntheticSections we have a choice, we can write them big-endian with mapping symbols, and then do the same endian reversal as for non-SyntheticSections; or we can have the SyntheticSections force little-endian writes for instructions.

I notice that ARMErrataFix.cpp hard-codes reading of little-endian instructions. This won't work on a big-endian relocatable object. In practice all the systems that use ARMErrataFix.cpp are likely to be little-endian so it may not be necessary to support it for big-endian at this point. It would be good to error out with an unsupported error message.

I suspect that some reviewers will prefer to have the tests in the same review as the patch as this is making functional changes.

Not had a chance to go over all the small changes, but on a quick scan I couldn't spot anything obviously wrong. The more difficult bit will be spotting anything missing.

I'll be on vacation for three weeks. Happy for others to review in my absence. Otherwise I can pick it back up next year.

[MaskRay]

lld/ELF/Options.td

39

What do the options do? arm-linux-gnueabihf-ld doesn't support --be8 or --be32.

[MaskRay]

lld/ELF/Options.td

39

If they are really needed, FF< to only support the double-dash form.

lld/docs/ld.lld.1

92

This description isn't very clear.

[M-Plichta]

Thanks for the description Peter, and for all the comments. Hope this adds enough clarity.

[MaskRay]

Please answer why --be8 and --be32 are added and what the references are.

lld/ELF/ARMErrataFix.cpp

181

don't capitalize. see other diagnostics. this incompatibility check should be added to Driver.cpp see " may not be used together"

lld/ELF/Arch/ARM.cpp

918

Add newline at end of file

lld/ELF/Driver.cpp

1075

If not yet supported, just delete this option. Are use cases using this option still useful?

[M-Plichta]

In D140202#4016163, @MaskRay wrote:

Please answer why --be8 and --be32 are added and what the references are.

Some documentation for --be8: https://sourceware.org/binutils/docs/ld/ARM.html and https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
As far as I'm aware, --be32 is deprecated but needed to be added for backwards compatibility.

The --be8 and --be32 were added at the same time because this patch is a precursor for the patch that adds --be8 support. You're right though, it does not belong in this patch.

Thanks.

[MaskRay]

In D140202#4023008, @M-Plichta wrote:

In D140202#4016163, @MaskRay wrote:

Please answer why --be8 and --be32 are added and what the references are.

Some documentation for --be8: https://sourceware.org/binutils/docs/ld/ARM.html and https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
As far as I'm aware, --be32 is deprecated but needed to be added for backwards compatibility.

The --be8 and --be32 were added at the same time because this patch is a precursor for the patch that adds --be8 support. You're right though, it does not belong in this patch.

Thanks.

Removing the options and this patch is fine.

[simpal01]

I am taking over this change from the original author @Milosz-Plichta with his permission to move the change forward.

[MaskRay]

In D140202#4023960, @MaskRay wrote:

In D140202#4023008, @M-Plichta wrote:

In D140202#4016163, @MaskRay wrote:

Please answer why --be8 and --be32 are added and what the references are.

Some documentation for --be8: https://sourceware.org/binutils/docs/ld/ARM.html and https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
As far as I'm aware, --be32 is deprecated but needed to be added for backwards compatibility.

The --be8 and --be32 were added at the same time because this patch is a precursor for the patch that adds --be8 support. You're right though, it does not belong in this patch.

Thanks.

Removing the options and this patch is fine.

Request for removal :)

[simpal01]

Addressed all the comments. I have added all the tests in this same
patch where we are making all the functional changes. I have literally
taken all the changes from https://reviews.llvm.org/D140203 to here.
Also added few more testcases.

[peter.smith]

A few small comments to move an error message to Driver.cpp and to remove the --be32 option. This will mean updating the tests.

I've not had the chance to check through the tests yet, but will do so tomorrow.

Please can you Commandeer https://reviews.llvm.org/D140203 and take the Abandon Revision action. That revision is now redundant as this one includes all of its changes and tests.

lld/ELF/ARMErrataFix.cpp

181

This comment still needs to be done. I've left a comment to highlight the place in Driver.cpp

lld/ELF/Driver.cpp

349

This would be the place to move the check from ARMErrataFix.cpp.

Message text could be something like --fix-cortex-a8 is not supported on big-endian targets

I also suggest adding an error message for --be32 on emachine != EM_ARM

lld/ELF/Options.td

43

These comments not done yet.

GNU ld only has the --be8 option, it defaults to --be32. We should remove this command line from upstream and default to --be32 (tests will need altering).

When the --be8 support is added we can add the --be8 switch.

The --be8 is in theory the better default, but if we do go down that route we will need both --be8 and --be32 as GCC and clang drivers will always pass --be8.

lld/docs/ld.lld.1

91

I think we should take this out given that I'm suggesting taking out --be32 to match the GNU ld interface.

When we add --be8 we'll need to add that here.

[simpal01]

This patch now

• Removes the --be32 command line option and make it default.
• Added an error check for the --fix-cortex-a8 option on big endian targets
• Updated the tests accordingly.

[simpal01]

This comment was removed by simpal01.

lld/ELF/Driver.cpp

349

Now i have set be32 in Config.h with

**bool be32 = false;**

And again setting this value in setConfigs with

**config->be32 = (k==ELF32BEKIND && m==EM_ARM);**

And when we implement --be8 switch, my plan is to change this to

config->be32 = (k==ELF32BEKIND && m==EM_ARM && !config->be8);

where config->be8 will be

config->be8 = args.hasArg(OPT_be8);

Since i am setting the be32 value only when emachine = EM_ARM, i am not sure if we still need to add an error message for --be32 on emachine!=EM_ARM.

[simpal01]

lld/ELF/Driver.cpp

349

Now i have set be32 in Config.h with

bool be32 = false;

And again setting this value in setConfigs with

config->be32 = (k==ELF32BEKIND && m==EM_ARM);

And when we implement --be8 switch, my plan is to change this to

config->be32 = (k==ELF32BEKIND && m==EM_ARM && !config->be8);

where config->be8 will be

config->be8 = args.hasArg(OPT_be8);

Since i am setting the be32 value only when emachine = EM_ARM, i am not sure if we still need to add an error message for --be32 on emachine!=EM_ARM.

[peter.smith]

I think I've spotted a problem in .ARM.exidx table compression. I also think we can get rid of config->be32 for this patch as nothing else reads it.

lld/ELF/Config.h

195

I don't think anything in this patch uses this be32 variable. Given that there will be a --be8 switch and be32 will be the default I think we can do everything we need in a follow up patch with just be8 which is set with config->be8 = args.hasArg(OPT_be8);

lld/ELF/Driver.cpp

1544

As mentioned above I think we can take this out for this patch as config->be32 is never read.

lld/ELF/SyntheticSections.cpp

3414 ↗

(On Diff #505400)

I think this needs changing, it is probably the reason the .ARM.exidx table is not identical between little and big-endian.

lld/test/ELF/arm-exidx-emit-relocs.s

77 ↗

(On Diff #505400)

There is an extra table entry in the .ARM.exidx section, which I can't immediately see why that would be the case. The only difference I can see in the RUN: line is -mcpu=cortex-a8 but I wouldn't expect that to make any difference.

At a glance I can see two identical entries at addresses 100d4 and 100dc with unwinding instructions 80978408. Table compression should be able to merge these two adjacent, identical entries.

lld/test/ELF/arm-exidx-sentinel-norelocatable.s

23 ↗

(On Diff #505400)

Remove extra trailing whitespace

[simpal01]

This patch:

• get rid of config->be32 for this patch
• Fixed the problem found in .ARM.exidx table compression. Now isDuplicateArmExidxSec works for both little and big endians. .ARM.exidx table is now identical between little and big-endian.

[peter.smith]

This looks correct, although I think there are a few places where we can simplify the code to remove the explicit endianness.

lld/ELF/SyntheticSections.cpp

3545 ↗

(On Diff #506567)

I think we can simplify the function by replacing cantUnwindData with a comment

// A linker generated CANTUNWIND entry is made up of two words
// 0x0 with R_ARM_PREL31 relocation to target.
// 0x1

We can then replace read32le(cantUnwindData+0) with 0x0 and read32le(cantUnwindData+4) with 0x1 in the two places it is used.

3568 ↗

(On Diff #506567)

Suggest making this // Write Sentinel CANTUNWIND entry.

[peter.smith]

lld/ELF/SyntheticSections.cpp

3445 ↗

(On Diff #506567)

Phab lost my previous comment that I had spent ages on. Sigh...

I think that we can rewrite this so that we don't have to use explicit endianness. Instead of using getDataAs() we use content().getData() and read32().

For example (untested and will need comments)

uint32_t prevUnwind = 1;
if (prev)
  prevUnwind = read32(prev->getContent().getData() + prev->size - 4);
if (isExtabRef(prevUnwind))
  return false;
...
if (cur == nullptr)
  return prevUnwind == 1;

for(uint32_t offset = 4; offset < size; offset += 8) {
  uint32_t curUnwind = read32(getContent().getData() + offset);
  if (isExtabRef(curUnwind) || curUnwind != prevUnwind)
      return false;
}

[simpal01]

Addressed Peter's review comments.

[peter.smith]

One tiny change to add some punctuation to a comment. This can be done prior to commit, no need to post another review.

I think that this satisfies MaskRay's request in https://reviews.llvm.org/D140202#4132479 to remove --be8 from this patch. LLD now has the same interface as GNU ld for BE32. Will be worth waiting a day or so to see if there are any additional comments from the US timezone.

lld/ELF/SyntheticSections.cpp

3530 ↗

(On Diff #507658)

Just remembered the LLD convention for comments. Can you add a colon after two words and put a full stop after 0x1. essentially:

// A linker generated CANTUNWIND entry is made up of two words:
// 0x0 with R_ARM_PREL31 relocation to target.
// 0x1.

My apologies I should have made that clearer in the example.

[MaskRay]

PPC64 is not templated while supporting both endians. If we use templates for ARM, we can use write32<ELFT::TargetEndianness> to save a config->endianness dispatch.

lld/ELF/Arch/ARM.cpp

187

write32<ELFT::TargetEndianness> will be more efficient and compile to less code.

[simpal01]

Yeah, It does look like we do not need to add the template to the Arm target classes.
I can not see any places that we use the template parameter. Detemplating the classes
which makes it more readable.

[MaskRay]

LGTM.

lld/ELF/ARMErrataFix.cpp

 #include "OutputSections.h"
 #include "Relocations.h"
 #include "Symbols.h"
 #include "SyntheticSections.h"
 #include "Target.h"
 #include "lld/Common/CommonLinkerContext.h"
 #include "lld/Common/Strings.h"
 #include "llvm/Support/Endian.h"
+#include "llvm/Support/Error.h"
 #include <algorithm>
 
 using namespace llvm;
 using namespace llvm::ELF;
 using namespace llvm::object;
 using namespace llvm::support;
 using namespace llvm::support::endian;
 using namespace lld;
static uint64_t getThumbDestAddr(uint64_t sourceAddr, uint32_t instr) {
   // which corresponds to alignDown.
   if (isBLX(instr))
     sourceAddr = alignDown(sourceAddr, 4);
   return sourceAddr + offset + 4;
 }
 
 void Patch657417Section::writeTo(uint8_t *buf) {
   // The base instruction of the patch is always a 32-bit unconditional branch.
+  if (config->be32 || config->be8)
+    error("Unsupported for big-endian");
   if (isARM)
     write32le(buf, 0xea000000);
   else
     write32le(buf, 0x9000f000);
   // If we have a relocation then apply it.
   if (!relocs().empty()) {
     target->relocateAlloc(*this, buf);
     return;

lld/ELF/Arch/ARM.cpp

 using namespace llvm;
 using namespace llvm::support::endian;
 using namespace llvm::support;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
-class ARM final : public TargetInfo {
+template <class ELFT> class ARM final : public TargetInfo {
 public:
   ARM();
   uint32_t calcEFlags() const override;
   RelExpr getRelExpr(RelType type, const Symbol &s,
                      const uint8_t *loc) const override;
   RelType getDynRel(RelType type) const override;
   int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
   void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
   void writePltHeader(uint8_t *buf) const override;
   void writePlt(uint8_t *buf, const Symbol &sym,
                 uint64_t pltEntryAddr) const override;
   void addPltSymbols(InputSection &isec, uint64_t off) const override;
   void addPltHeaderSymbols(InputSection &isd) const override;
   bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
                   uint64_t branchAddr, const Symbol &s,
                   int64_t a) const override;
   uint32_t getThunkSectionSpacing() const override;
   bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
   void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
 };
 } // namespace
 
-ARM::ARM() {
+template <class ELFT> ARM<ELFT>::ARM() {
   copyRel = R_ARM_COPY;
   relativeRel = R_ARM_RELATIVE;
   iRelativeRel = R_ARM_IRELATIVE;
   gotRel = R_ARM_GLOB_DAT;
   pltRel = R_ARM_JUMP_SLOT;
   symbolicRel = R_ARM_ABS32;
   tlsGotRel = R_ARM_TLS_TPOFF32;
   tlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
   tlsOffsetRel = R_ARM_TLS_DTPOFF32;
   pltHeaderSize = 32;
   pltEntrySize = 16;
   ipltEntrySize = 16;
   trapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
   needsThunks = true;
   defaultMaxPageSize = 65536;
 }
 
-uint32_t ARM::calcEFlags() const {
+template <class ELFT> uint32_t ARM<ELFT>::calcEFlags() const {
   // The ABIFloatType is used by loaders to detect the floating point calling
   // convention.
   uint32_t abiFloatType = 0;
   if (config->armVFPArgs == ARMVFPArgKind::Base ||
       config->armVFPArgs == ARMVFPArgKind::Default)
     abiFloatType = EF_ARM_ABI_FLOAT_SOFT;
   else if (config->armVFPArgs == ARMVFPArgKind::VFP)
     abiFloatType = EF_ARM_ABI_FLOAT_HARD;
 
   // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
   // but we don't have any firm guarantees of conformance. Linux AArch64
   // kernels (as of 2016) require an EABI version to be set.
   return EF_ARM_EABI_VER5 | abiFloatType;
 }
 
-RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
+template <class ELFT> RelExpr ARM<ELFT>::getRelExpr(RelType type, const Symbol &s,
                         const uint8_t *loc) const {
   switch (type) {
   case R_ARM_ABS32:
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVT_ABS:
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVT_ABS:
     return R_ABS;
case R_ARM_V4BX:
     return R_NONE;
   default:
     error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
           ") against symbol " + toString(s));
     return R_NONE;
   }
 }
 
-RelType ARM::getDynRel(RelType type) const {
+template <class ELFT> RelType ARM<ELFT>::getDynRel(RelType type) const {
   if ((type == R_ARM_ABS32) || (type == R_ARM_TARGET1 && !config->target1Rel))
     return R_ARM_ABS32;
   return R_ARM_NONE;
 }
 
-void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
-  write32le(buf, in.plt->getVA());
+template <class ELFT> void ARM<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const {
+  write32(buf, in.plt->getVA());
 }
 
-void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
+template <class ELFT> void ARM<ELFT>::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
   // An ARM entry is the address of the ifunc resolver function.
-  write32le(buf, s.getVA());
+  write32(buf, s.getVA());
 }
 
 // Long form PLT Header that does not have any restrictions on the displacement
 // of the .plt from the .got.plt.
 static void writePltHeaderLong(uint8_t *buf) {
   write32(buf + 0, 0xe52de004);   //     str lr, [sp,#-4]!
   write32(buf + 4, 0xe59fe004);   //     ldr lr, L2
   write32(buf + 8, 0xe08fe00e);   // L1: add lr, pc, lr
   write32(buf + 12, 0xe5bef008);  //     ldr pc, [lr, #8]
   write32(buf + 16, 0x00000000);  // L2: .word   &(.got.plt) - L1 - 8
   write32(buf + 20, 0xd4d4d4d4);  //     Pad to 32-byte boundary
   write32(buf + 24, 0xd4d4d4d4);  //     Pad to 32-byte boundary
   write32(buf + 28, 0xd4d4d4d4);
   uint64_t gotPlt = in.gotPlt->getVA();
   uint64_t l1 = in.plt->getVA() + 8;
-  write32le(buf + 16, gotPlt - l1 - 8);
+  write32(buf + 16, gotPlt - l1 - 8);
 }
 
 // The default PLT header requires the .got.plt to be within 128 Mb of the
 // .plt in the positive direction.
-void ARM::writePltHeader(uint8_t *buf) const {
+template <class ELFT> void ARM<ELFT>::writePltHeader(uint8_t *buf) const {
   // Use a similar sequence to that in writePlt(), the difference is the calling
   // conventions mean we use lr instead of ip. The PLT entry is responsible for
   // saving lr on the stack, the dynamic loader is responsible for reloading
   // it.
   const uint32_t pltData[] = {
       0xe52de004, // L1: str lr, [sp,#-4]!
       0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
       0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
       0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
   };
 
   uint64_t offset = in.gotPlt->getVA() - in.plt->getVA() - 4;
   if (!llvm::isUInt<27>(offset)) {
     // We cannot encode the Offset, use the long form.
     writePltHeaderLong(buf);
     return;
   }
-  write32le(buf + 0, pltData[0]);
-  write32le(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
-  write32le(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
-  write32le(buf + 12, pltData[3] | (offset & 0xfff));
+  write32(buf + 0, pltData[0]);
+  write32(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
+  write32(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
+  write32(buf + 12, pltData[3] | (offset & 0xfff));
   memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary
   memcpy(buf + 20, trapInstr.data(), 4);
   memcpy(buf + 24, trapInstr.data(), 4);
   memcpy(buf + 28, trapInstr.data(), 4);
 }
 
-void ARM::addPltHeaderSymbols(InputSection &isec) const {
+template <class ELFT> void ARM<ELFT>::addPltHeaderSymbols(InputSection &isec) const {
   addSyntheticLocal("$a", STT_NOTYPE, 0, 0, isec);
   addSyntheticLocal("$d", STT_NOTYPE, 16, 0, isec);
 }
 
 // Long form PLT entries that do not have any restrictions on the displacement
 // of the .plt from the .got.plt.
 static void writePltLong(uint8_t *buf, uint64_t gotPltEntryAddr,
                          uint64_t pltEntryAddr) {
   write32(buf + 0, 0xe59fc004);   //     ldr ip, L2
   write32(buf + 4, 0xe08cc00f);   // L1: add ip, ip, pc
   write32(buf + 8, 0xe59cf000);   //     ldr pc, [ip]
   write32(buf + 12, 0x00000000);  // L2: .word   Offset(&(.got.plt) - L1 - 8
   uint64_t l1 = pltEntryAddr + 4;
-  write32le(buf + 12, gotPltEntryAddr - l1 - 8);
+  write32(buf + 12, gotPltEntryAddr - l1 - 8);
 }
 
 // The default PLT entries require the .got.plt to be within 128 Mb of the
 // .plt in the positive direction.
-void ARM::writePlt(uint8_t *buf, const Symbol &sym,
+template <class ELFT> void ARM<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
                    uint64_t pltEntryAddr) const {
   // The PLT entry is similar to the example given in Appendix A of ELF for
   // the Arm Architecture. Instead of using the Group Relocations to find the
   // optimal rotation for the 8-bit immediate used in the add instructions we
   // hard code the most compact rotations for simplicity. This saves a load
   // instruction over the long plt sequences.
   const uint32_t pltData[] = {
       0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.got.plt) - L1 - 8
       0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.got.plt) - L1 - 8
       0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.got.plt) - L1 - 8
   };
 
   uint64_t offset = sym.getGotPltVA() - pltEntryAddr - 8;
   if (!llvm::isUInt<27>(offset)) {
     // We cannot encode the Offset, use the long form.
     writePltLong(buf, sym.getGotPltVA(), pltEntryAddr);
     return;
   }
-  write32le(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
-  write32le(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
-  write32le(buf + 8, pltData[2] | (offset & 0xfff));
+  write32(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
+  write32(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
+  write32(buf + 8, pltData[2] | (offset & 0xfff));
   memcpy(buf + 12, trapInstr.data(), 4); // Pad to 16-byte boundary
 }
 
-void ARM::addPltSymbols(InputSection &isec, uint64_t off) const {
+template <class ELFT> void ARM<ELFT>::addPltSymbols(InputSection &isec, uint64_t off) const {
   addSyntheticLocal("$a", STT_NOTYPE, off, 0, isec);
   addSyntheticLocal("$d", STT_NOTYPE, off + 12, 0, isec);
 }
 
-bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
+template <class ELFT> bool ARM<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file,
                      uint64_t branchAddr, const Symbol &s,
                      int64_t a) const {
   // If s is an undefined weak symbol and does not have a PLT entry then it will
   // be resolved as a branch to the next instruction. If it is hidden, its
   // binding has been converted to local, so we just check isUndefined() here. A
   // undefined non-weak symbol will have been errored.
   if (s.isUndefined() && !s.isInPlt())
     return false;
template <class ELFT> bool ARM<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file,
   case R_ARM_THM_CALL: {
     uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA() : s.getVA();
     return !inBranchRange(type, branchAddr, dst + a);
   }
   }
   return false;
 }
 
-uint32_t ARM::getThunkSectionSpacing() const {
+template <class ELFT> uint32_t ARM<ELFT>::getThunkSectionSpacing() const {
   // The placing of pre-created ThunkSections is controlled by the value
   // thunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
   // place the ThunkSection such that all branches from the InputSections
   // prior to the ThunkSection can reach a Thunk placed at the end of the
   // ThunkSection. Graphically:
   // | up to thunkSectionSpacing .text input sections |
   // | ThunkSection                                   |
   // | up to thunkSectionSpacing .text input sections |
template <class ELFT> uint32_t ARM<ELFT>::getThunkSectionSpacing() const {
   // On Arm the thunkSectionSpacing depends on the range of the Thumb Branch
   // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
   // ARMv6T2) the range is +/- 4MiB.
 
   return (config->armJ1J2BranchEncoding) ? 0x1000000 - 0x30000
                                          : 0x400000 - 0x7500;
 }
 
-bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
+template <class ELFT> bool ARM<ELFT>::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
   if ((dst & 0x1) == 0)
     // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
     // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
     // destination will be 4 byte aligned.
     src &= ~0x3;
   else
     // Bit 0 == 1 denotes Thumb state, it is not part of the range.
     dst &= ~0x1;
static void encodeAluGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
   uint32_t rot = 0;
   if (lz < 24) {
     imm = rotr32(imm, 24 - lz);
     rot = (lz + 8) << 7;
   }
   if (check && imm > 0xff)
     error(getErrorLocation(loc) + "unencodeable immediate " + Twine(val).str() +
           " for relocation " + toString(rel.type));
-  write32le(loc, (read32le(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
+  write32(loc, (read32(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
 }
 
 static void encodeLdrGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
                            int group) {
   // R_ARM_LDR_PC_Gn is S + A - P, we have ((S + A) | T) - P, if S is a
   // function then addr is 0 (modulo 2) and Pa is 0 (modulo 4) so we can clear
   // bottom bit to recover S + A - P.
   if (rel.sym->isFunc())
     val &= ~0x1;
   // LDR (literal) u = bit23
   uint32_t opcode = 0x00800000;
   if (val >> 63) {
     opcode = 0x0;
     val = -val;
   }
   uint32_t imm = getRemAndLZForGroup(group, val).first;
   checkUInt(loc, imm, 12, rel);
-  write32le(loc, (read32le(loc) & 0xff7ff000) | opcode | imm);
+  write32(loc, (read32(loc) & 0xff7ff000) | opcode | imm);
 }
 
 static void encodeLdrsGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
                             int group) {
   // R_ARM_LDRS_PC_Gn is S + A - P, we have ((S + A) | T) - P, if S is a
   // function then addr is 0 (modulo 2) and Pa is 0 (modulo 4) so we can clear
   // bottom bit to recover S + A - P.
   if (rel.sym->isFunc())
     val &= ~0x1;
   // LDRD/LDRH/LDRSB/LDRSH (literal) u = bit23
   uint32_t opcode = 0x00800000;
   if (val >> 63) {
     opcode = 0x0;
     val = -val;
   }
   uint32_t imm = getRemAndLZForGroup(group, val).first;
   checkUInt(loc, imm, 8, rel);
-  write32le(loc, (read32le(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
+  write32(loc, (read32(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
                      (imm & 0xf));
 }
 
-void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
+template <class ELFT> void ARM<ELFT>::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   switch (rel.type) {
   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
   case R_ARM_GOTOFF32:
   case R_ARM_GOT_BREL:
   case R_ARM_GOT_PREL:
   case R_ARM_REL32:
   case R_ARM_RELATIVE:
   case R_ARM_SBREL32:
   case R_ARM_TARGET1:
   case R_ARM_TARGET2:
   case R_ARM_TLS_GD32:
   case R_ARM_TLS_IE32:
   case R_ARM_TLS_LDM32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_LE32:
   case R_ARM_TLS_TPOFF32:
   case R_ARM_TLS_DTPOFF32:
-    write32le(loc, val);
+    write32(loc, val);
     break;
   case R_ARM_PREL31:
     checkInt(loc, val, 31, rel);
-    write32le(loc, (read32le(loc) & 0x80000000) | (val & ~0x80000000));
+    write32(loc, (read32(loc) & 0x80000000) | (val & ~0x80000000));
     break;
   case R_ARM_CALL: {
     // R_ARM_CALL is used for BL and BLX instructions, for symbols of type
     // STT_FUNC we choose whether to write a BL or BLX depending on the
     // value of bit 0 of Val. With bit 0 == 1 denoting Thumb. If the symbol is
     // not of type STT_FUNC then we must preserve the original instruction.
     // PLT entries are always ARM state so we know we don't need to interwork.
     assert(rel.sym); // R_ARM_CALL is always reached via relocate().
     bool bit0Thumb = val & 1;
-    bool isBlx = (read32le(loc) & 0xfe000000) == 0xfa000000;
+    bool isBlx = (read32(loc) & 0xfe000000) == 0xfa000000;
     // lld 10.0 and before always used bit0Thumb when deciding to write a BLX
     // even when type not STT_FUNC.
     if (!rel.sym->isFunc() && isBlx != bit0Thumb)
       stateChangeWarning(loc, rel.type, *rel.sym);
     if (rel.sym->isFunc() ? bit0Thumb : isBlx) {
       // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
       checkInt(loc, val, 26, rel);
-      write32le(loc, 0xfa000000 |                    // opcode
+      write32(loc, 0xfa000000 |                    // opcode
                          ((val & 2) << 23) |         // H
                          ((val >> 2) & 0x00ffffff)); // imm24
       break;
     }
     // BLX (always unconditional) instruction to an ARM Target, select an
     // unconditional BL.
-    write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff));
+    write32(loc, 0xeb000000 | (read32(loc) & 0x00ffffff));
     // fall through as BL encoding is shared with B
   }
     [[fallthrough]];
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
     checkInt(loc, val, 26, rel);
-    write32le(loc, (read32le(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
+    write32(loc, (read32(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
     break;
   case R_ARM_THM_JUMP8:
     // We do a 9 bit check because val is right-shifted by 1 bit.
     checkInt(loc, val, 9, rel);
-    write16le(loc, (read32le(loc) & 0xff00) | ((val >> 1) & 0x00ff));
+    write16(loc, (read32(loc) & 0xff00) | ((val >> 1) & 0x00ff));
     break;
   case R_ARM_THM_JUMP11:
     // We do a 12 bit check because val is right-shifted by 1 bit.
     checkInt(loc, val, 12, rel);
-    write16le(loc, (read32le(loc) & 0xf800) | ((val >> 1) & 0x07ff));
+    write16(loc, (read32(loc) & 0xf800) | ((val >> 1) & 0x07ff));
     break;
   case R_ARM_THM_JUMP19:
     // Encoding T3: Val = S:J2:J1:imm6:imm11:0
     checkInt(loc, val, 21, rel);
-    write16le(loc,
-              (read16le(loc) & 0xfbc0) |   // opcode cond
+    write16(loc,
+              (read16(loc) & 0xfbc0) |   // opcode cond
                   ((val >> 10) & 0x0400) | // S
                   ((val >> 12) & 0x003f)); // imm6
-    write16le(loc + 2,
+    write16(loc + 2,
               0x8000 |                    // opcode
                   ((val >> 8) & 0x0800) | // J2
                   ((val >> 5) & 0x2000) | // J1
                   ((val >> 1) & 0x07ff)); // imm11
     break;
   case R_ARM_THM_CALL: {
     // R_ARM_THM_CALL is used for BL and BLX instructions, for symbols of type
     // STT_FUNC we choose whether to write a BL or BLX depending on the
     // value of bit 0 of Val. With bit 0 == 0 denoting ARM, if the symbol is
     // not of type STT_FUNC then we must preserve the original instruction.
     // PLT entries are always ARM state so we know we need to interwork.
     assert(rel.sym); // R_ARM_THM_CALL is always reached via relocate().
     bool bit0Thumb = val & 1;
-    bool isBlx = (read16le(loc + 2) & 0x1000) == 0;
+    bool isBlx = (read16(loc + 2) & 0x1000) == 0;
     // lld 10.0 and before always used bit0Thumb when deciding to write a BLX
     // even when type not STT_FUNC. PLT entries generated by LLD are always ARM.
     if (!rel.sym->isFunc() && !rel.sym->isInPlt() && isBlx == bit0Thumb)
       stateChangeWarning(loc, rel.type, *rel.sym);
     if (rel.sym->isFunc() || rel.sym->isInPlt() ? !bit0Thumb : isBlx) {
       // We are writing a BLX. Ensure BLX destination is 4-byte aligned. As
       // the BLX instruction may only be two byte aligned. This must be done
       // before overflow check.
       val = alignTo(val, 4);
-      write16le(loc + 2, read16le(loc + 2) & ~0x1000);
+      write16(loc + 2, read16(loc + 2) & ~0x1000);
     } else {
-      write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | 1 << 12);
+      write16(loc + 2, (read16(loc + 2) & ~0x1000) | 1 << 12);
     }
     if (!config->armJ1J2BranchEncoding) {
       // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
       // different encoding rules and range due to J1 and J2 always being 1.
       checkInt(loc, val, 23, rel);
-      write16le(loc,
+      write16(loc,
                 0xf000 |                     // opcode
                     ((val >> 12) & 0x07ff)); // imm11
-      write16le(loc + 2,
-                (read16le(loc + 2) & 0xd000) | // opcode
+      write16(loc + 2,
+                (read16(loc + 2) & 0xd000) | // opcode
                     0x2800 |                   // J1 == J2 == 1
                     ((val >> 1) & 0x07ff));    // imm11
       break;
     }
   }
     // Fall through as rest of encoding is the same as B.W
     [[fallthrough]];
   case R_ARM_THM_JUMP24:
     // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
     checkInt(loc, val, 25, rel);
-    write16le(loc,
+    write16(loc,
               0xf000 |                     // opcode
                   ((val >> 14) & 0x0400) | // S
                   ((val >> 12) & 0x03ff)); // imm10
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0xd000) |                  // opcode
+    write16(loc + 2,
+              (read16(loc + 2) & 0xd000) |                  // opcode
                   (((~(val >> 10)) ^ (val >> 11)) & 0x2000) | // J1
                   (((~(val >> 11)) ^ (val >> 13)) & 0x0800) | // J2
                   ((val >> 1) & 0x07ff));                     // imm11
     break;
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVW_PREL_NC:
   case R_ARM_MOVW_BREL_NC:
-    write32le(loc, (read32le(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
+    write32(loc, (read32(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
                        (val & 0x0fff));
     break;
   case R_ARM_MOVT_ABS:
   case R_ARM_MOVT_PREL:
   case R_ARM_MOVT_BREL:
-    write32le(loc, (read32le(loc) & ~0x000f0fff) |
+    write32(loc, (read32(loc) & ~0x000f0fff) |
                        (((val >> 16) & 0xf000) << 4) | ((val >> 16) & 0xfff));
     break;
   case R_ARM_THM_MOVT_ABS:
   case R_ARM_THM_MOVT_PREL:
   case R_ARM_THM_MOVT_BREL:
     // Encoding T1: A = imm4:i:imm3:imm8
-    write16le(loc,
-              0xf2c0 |                     // opcode
-                  ((val >> 17) & 0x0400) | // i
-                  ((val >> 28) & 0x000f)); // imm4
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | // opcode
+
+    write16(loc,
+
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | // opcode
                   ((val >> 12) & 0x7000) |   // imm3
                   ((val >> 16) & 0x00ff));   // imm8
     break;
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVW_PREL_NC:
   case R_ARM_THM_MOVW_BREL_NC:
     // Encoding T3: A = imm4:i:imm3:imm8
-    write16le(loc,
+    write16(loc,
               0xf240 |                     // opcode
                   ((val >> 1) & 0x0400) |  // i
                   ((val >> 12) & 0x000f)); // imm4
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | // opcode
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | // opcode
                   ((val << 4) & 0x7000) |    // imm3
                   (val & 0x00ff));           // imm8
     break;
   case R_ARM_ALU_PC_G0:
     encodeAluGroup(loc, rel, val, 0, true);
     break;
   case R_ARM_ALU_PC_G0_NC:
     encodeAluGroup(loc, rel, val, 0, false);
case R_ARM_THM_ALU_PREL_11_0: {
     // ADR encoding T2 (sub), T3 (add) i:imm3:imm8
     int64_t imm = val;
     uint16_t sub = 0;
     if (imm < 0) {
       imm = -imm;
       sub = 0x00a0;
     }
     checkUInt(loc, imm, 12, rel);
-    write16le(loc, (read16le(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
-    write16le(loc + 2,
-              (read16le(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff));
+    write16(loc, (read16(loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
+    write16(loc + 2,
+              (read16(loc + 2) & 0x8f00) | (imm & 0x700) << 4 | (imm & 0xff));
     break;
   }
   case R_ARM_THM_PC8:
     // ADR and LDR literal encoding T1 positive offset only imm8:00
     // R_ARM_THM_PC8 is S + A - Pa, we have ((S + A) | T) - Pa, if S is a
     // function then addr is 0 (modulo 2) and Pa is 0 (modulo 4) so we can clear
     // bottom bit to recover S + A - Pa.
     if (rel.sym->isFunc())
       val &= ~0x1;
     checkUInt(loc, val, 10, rel);
     checkAlignment(loc, val, 4, rel);
-    write16le(loc, (read16le(loc) & 0xff00) | (val & 0x3fc) >> 2);
+    write16(loc, (read16(loc) & 0xff00) | (val & 0x3fc) >> 2);
     break;
   case R_ARM_THM_PC12: {
     // LDR (literal) encoding T2, add = (U == '1') imm12
     // imm12 is unsigned
     // R_ARM_THM_PC12 is S + A - Pa, we have ((S + A) | T) - Pa, if S is a
     // function then addr is 0 (modulo 2) and Pa is 0 (modulo 4) so we can clear
     // bottom bit to recover S + A - Pa.
     if (rel.sym->isFunc())
       val &= ~0x1;
     int64_t imm12 = val;
     uint16_t u = 0x0080;
     if (imm12 < 0) {
       imm12 = -imm12;
       u = 0;
     }
     checkUInt(loc, imm12, 12, rel);
-    write16le(loc, read16le(loc) | u);
-    write16le(loc + 2, (read16le(loc + 2) & 0xf000) | imm12);
+    write16(loc, read16(loc) | u);
+    write16(loc + 2, (read16(loc + 2) & 0xf000) | imm12);
     break;
   }
   default:
     llvm_unreachable("unknown relocation");
   }
 }
 
-int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
+template <class ELFT> int64_t ARM<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
   switch (type) {
   default:
     internalLinkerError(getErrorLocation(buf),
                         "cannot read addend for relocation " + toString(type));
     return 0;
   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
   case R_ARM_GLOB_DAT:
template <class ELFT> int64_t ARM<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
   case R_ARM_TLS_DTPMOD32:
   case R_ARM_TLS_DTPOFF32:
   case R_ARM_TLS_GD32:
   case R_ARM_TLS_IE32:
   case R_ARM_TLS_LDM32:
   case R_ARM_TLS_LE32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_TPOFF32:
-    return SignExtend64<32>(read32le(buf));
+    return SignExtend64<32>(read32(buf));
   case R_ARM_PREL31:
-    return SignExtend64<31>(read32le(buf));
+    return SignExtend64<31>(read32(buf));
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
-    return SignExtend64<26>(read32le(buf) << 2);
+    return SignExtend64<26>(read32(buf) << 2);
   case R_ARM_THM_JUMP8:
-    return SignExtend64<9>(read16le(buf) << 1);
+    return SignExtend64<9>(read16(buf) << 1);
   case R_ARM_THM_JUMP11:
-    return SignExtend64<12>(read16le(buf) << 1);
+    return SignExtend64<12>(read16(buf) << 1);
   case R_ARM_THM_JUMP19: {
     // Encoding T3: A = S:J2:J1:imm10:imm6:0
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<20>(((hi & 0x0400) << 10) | // S
                             ((lo & 0x0800) << 8) |  // J2
                             ((lo & 0x2000) << 5) |  // J1
                             ((hi & 0x003f) << 12) | // imm6
                             ((lo & 0x07ff) << 1));  // imm11:0
   }
   case R_ARM_THM_CALL:
     if (!config->armJ1J2BranchEncoding) {
       // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
       // different encoding rules and range due to J1 and J2 always being 1.
-      uint16_t hi = read16le(buf);
-      uint16_t lo = read16le(buf + 2);
+      uint16_t hi = read16(buf);
+      uint16_t lo = read16(buf + 2);
       return SignExtend64<22>(((hi & 0x7ff) << 12) | // imm11
                               ((lo & 0x7ff) << 1));  // imm11:0
       break;
     }
     [[fallthrough]];
   case R_ARM_THM_JUMP24: {
     // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
     // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<24>(((hi & 0x0400) << 14) |                    // S
                             (~((lo ^ (hi << 3)) << 10) & 0x00800000) | // I1
                             (~((lo ^ (hi << 1)) << 11) & 0x00400000) | // I2
                             ((hi & 0x003ff) << 12) |                   // imm0
                             ((lo & 0x007ff) << 1)); // imm11:0
   }
   // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
   // MOVT is in the range -32768 <= A < 32768
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVT_ABS:
   case R_ARM_MOVW_PREL_NC:
   case R_ARM_MOVT_PREL:
   case R_ARM_MOVW_BREL_NC:
   case R_ARM_MOVT_BREL: {
-    uint64_t val = read32le(buf) & 0x000f0fff;
+    uint64_t val = read32(buf) & 0x000f0fff;
     return SignExtend64<16>(((val & 0x000f0000) >> 4) | (val & 0x00fff));
   }
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVT_ABS:
   case R_ARM_THM_MOVW_PREL_NC:
   case R_ARM_THM_MOVT_PREL:
   case R_ARM_THM_MOVW_BREL_NC:
   case R_ARM_THM_MOVT_BREL: {
     // Encoding T3: A = imm4:i:imm3:imm8
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     return SignExtend64<16>(((hi & 0x000f) << 12) | // imm4
                             ((hi & 0x0400) << 1) |  // i
                             ((lo & 0x7000) >> 4) |  // imm3
                             (lo & 0x00ff));         // imm8
   }
   case R_ARM_ALU_PC_G0:
   case R_ARM_ALU_PC_G0_NC:
   case R_ARM_ALU_PC_G1:
   case R_ARM_ALU_PC_G1_NC:
   case R_ARM_ALU_PC_G2: {
     // 12-bit immediate is a modified immediate made up of a 4-bit even
     // right rotation and 8-bit constant. After the rotation the value
     // is zero-extended. When bit 23 is set the instruction is an add, when
     // bit 22 is set it is a sub.
-    uint32_t instr = read32le(buf);
+    uint32_t instr = read32(buf);
     uint32_t val = rotr32(instr & 0xff, ((instr & 0xf00) >> 8) * 2);
     return (instr & 0x00400000) ? -val : val;
   }
   case R_ARM_LDR_PC_G0:
   case R_ARM_LDR_PC_G1:
   case R_ARM_LDR_PC_G2: {
     // ADR (literal) add = bit23, sub = bit22
     // LDR (literal) u = bit23 unsigned imm12
-    bool u = read32le(buf) & 0x00800000;
-    uint32_t imm12 = read32le(buf) & 0xfff;
+    bool u = read32(buf) & 0x00800000;
+    uint32_t imm12 = read32(buf) & 0xfff;
     return u ? imm12 : -imm12;
   }
   case R_ARM_LDRS_PC_G0:
   case R_ARM_LDRS_PC_G1:
   case R_ARM_LDRS_PC_G2: {
     // LDRD/LDRH/LDRSB/LDRSH (literal) u = bit23 unsigned imm8
-    uint32_t opcode = read32le(buf);
+    uint32_t opcode = read32(buf);
     bool u = opcode & 0x00800000;
     uint32_t imm4l = opcode & 0xf;
     uint32_t imm4h = (opcode & 0xf00) >> 4;
     return u ? (imm4h | imm4l) : -(imm4h | imm4l);
   }
   case R_ARM_THM_ALU_PREL_11_0: {
     // Thumb2 ADR, which is an alias for a sub or add instruction with an
     // unsigned immediate.
     // ADR encoding T2 (sub), T3 (add) i:imm3:imm8
-    uint16_t hi = read16le(buf);
-    uint16_t lo = read16le(buf + 2);
+    uint16_t hi = read16(buf);
+    uint16_t lo = read16(buf + 2);
     uint64_t imm = (hi & 0x0400) << 1 | // i
                    (lo & 0x7000) >> 4 | // imm3
                    (lo & 0x00ff);       // imm8
     // For sub, addend is negative, add is positive.
     return (hi & 0x00f0) ? -imm : imm;
   }
   case R_ARM_THM_PC8:
     // ADR and LDR (literal) encoding T1
     // From ELF for the ARM Architecture the initial signed addend is formed
     // from an unsigned field using expression (((imm8:00 + 4) & 0x3ff) – 4)
     // this trick permits the PC bias of -4 to be encoded using imm8 = 0xff
-    return ((((read16le(buf) & 0xff) << 2) + 4) & 0x3ff) - 4;
+    return ((((read16(buf) & 0xff) << 2) + 4) & 0x3ff) - 4;
   case R_ARM_THM_PC12: {
     // LDR (literal) encoding T2, add = (U == '1') imm12
-    bool u = read16le(buf) & 0x0080;
-    uint64_t imm12 = read16le(buf + 2) & 0x0fff;
+    bool u = read16(buf) & 0x0080;
+    uint64_t imm12 = read16(buf + 2) & 0x0fff;
     return u ? imm12 : -imm12;
   }
   case R_ARM_NONE:
   case R_ARM_V4BX:
   case R_ARM_JUMP_SLOT:
     // These relocations are defined as not having an implicit addend.
     return 0;
   }
 }
 
-TargetInfo *elf::getARMTargetInfo() {
-  static ARM target;
+template <class ELFT> TargetInfo *elf::getARMTargetInfo() {
+  static ARM<ELFT> target;
   return &target;
 }
+
+template TargetInfo *elf::getARMTargetInfo<llvm::object::ELF32LE>();
+template TargetInfo *elf::getARMTargetInfo<llvm::object::ELF32BE>();
 No newline at end of file

lld/ELF/Config.h

llvm::MapVector<std::pair<const InputSectionBase *, const InputSectionBase *>,
                   uint64_t>
       callGraphProfile;
   bool allowMultipleDefinition;
   bool androidPackDynRelocs = false;
   bool armHasBlx = false;
   bool armHasMovtMovw = false;
   bool armJ1J2BranchEncoding = false;
   bool asNeeded = false;
+  bool be32 = false;
+  bool be8 = false;
   BsymbolicKind bsymbolic = BsymbolicKind::None;
   bool callGraphProfileSort;
   bool checkSections;
   bool checkDynamicRelocs;
   llvm::DebugCompressionType compressDebugSections;
   bool cref;
   llvm::SmallVector<std::pair<llvm::GlobPattern, uint64_t>, 0>
       deadRelocInNonAlloc;

lld/ELF/Driver.cpp

if (s.endswith("_fbsd")) {
     osabi = ELFOSABI_FREEBSD;
   }
 
   std::pair<ELFKind, uint16_t> ret =
       StringSwitch<std::pair<ELFKind, uint16_t>>(s)
           .Cases("aarch64elf", "aarch64linux", {ELF64LEKind, EM_AARCH64})
           .Cases("aarch64elfb", "aarch64linuxb", {ELF64BEKind, EM_AARCH64})
           .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM})
+          .Cases("armelfb", "armelfb_linux_eabi", {ELF32BEKind, EM_ARM})
           .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
           .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
           .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
           .Case("elf32lriscv", {ELF32LEKind, EM_RISCV})
           .Cases("elf32ppc", "elf32ppclinux", {ELF32BEKind, EM_PPC})
           .Cases("elf32lppc", "elf32lppclinux", {ELF32LEKind, EM_PPC})
           .Case("elf64btsmip", {ELF64BEKind, EM_MIPS})
           .Case("elf64ltsmip", {ELF64LEKind, EM_MIPS})
static void checkOptions() {
   // The MIPS ABI as of 2016 does not support the GNU-style symbol lookup
   // table which is a relatively new feature.
   if (config->emachine == EM_MIPS && config->gnuHash)
     error("the .gnu.hash section is not compatible with the MIPS target");
 
   if (config->fixCortexA53Errata843419 && config->emachine != EM_AARCH64)
     error("--fix-cortex-a53-843419 is only supported on AArch64 targets");
 
+  if (config->be8 && config->emachine != EM_ARM)
+    error("--be8 is only supported on Arm targets");
+
   if (config->fixCortexA8 && config->emachine != EM_ARM)
     error("--fix-cortex-a8 is only supported on ARM targets");
 
   if (config->tocOptimize && config->emachine != EM_PPC64)
     error("--toc-optimize is only supported on PowerPC64 targets");
 
   if (config->pcRelOptimize && config->emachine != EM_PPC64)
     error("--pcrel-optimize is only supported on PowerPC64 targets");
 
config->allowMultipleDefinition =
                    OPT_no_allow_multiple_definition, false) ||
       hasZOption(args, "muldefs");
   config->androidMemtagHeap =
       args.hasFlag(OPT_android_memtag_heap, OPT_no_android_memtag_heap, false);
   config->androidMemtagStack = args.hasFlag(OPT_android_memtag_stack,
                                             OPT_no_android_memtag_stack, false);
   config->androidMemtagMode = getMemtagMode(args);
   config->auxiliaryList = args::getStrings(args, OPT_auxiliary);
+  config->be8 = args.hasArg(OPT_be8);
+  if (config->be8) error("byte invariant not yet supported");
+  config->be32 = args.hasArg(OPT_be32);
   if (opt::Arg *arg =
           args.getLastArg(OPT_Bno_symbolic, OPT_Bsymbolic_non_weak_functions,
                           OPT_Bsymbolic_functions, OPT_Bsymbolic)) {
     if (arg->getOption().matches(OPT_Bsymbolic_non_weak_functions))
       config->bsymbolic = BsymbolicKind::NonWeakFunctions;
     else if (arg->getOption().matches(OPT_Bsymbolic_functions))
       config->bsymbolic = BsymbolicKind::Functions;
     else if (arg->getOption().matches(OPT_Bsymbolic))

 static void setConfigs(opt::InputArgList &args) {
   ELFKind k = config->ekind;
   uint16_t m = config->emachine;
 
   config->copyRelocs = (config->relocatable || config->emitRelocs);
   config->is64 = (k == ELF64LEKind || k == ELF64BEKind);
   config->isLE = (k == ELF32LEKind || k == ELF64LEKind);
   config->endianness = config->isLE ? endianness::little : endianness::big;
   config->isMips64EL = (k == ELF64LEKind && m == EM_MIPS);
   config->isPic = config->pie || config->shared;
   config->picThunk = args.hasArg(OPT_pic_veneer, config->isPic);
   config->wordsize = config->is64 ? 8 : 4;
 
   // ELF defines two different ways to store relocation addends as shown below:
   //
   //  Rel: Addends are stored to the location where relocations are applied. It
   //  cannot pack the full range of addend values for all relocation types, but

lld/ELF/Options.td

 
 multiclass B<string name, string help1, string help2> {
   def NAME: Flag<["--", "-"], name>, HelpText<help1>;
   def no_ # NAME: Flag<["--", "-"], "no-" # name>, HelpText<help2>;
 }
 
 defm auxiliary: Eq<"auxiliary", "Set DT_AUXILIARY field to the specified name">;
 
+def be8: FF<"be8">, HelpText<"Big-endian via a byte invariant, reverses the endianness of the instructions "
+  "to give little-endian code and big-endian data for input objects that have been compiled or assembled as big-endian">;
+def be32: FF<"be32">, HelpText<"Big-endian via a word invariant, produces big-endian code and data">;
+
 def Bno_symbolic: F<"Bno-symbolic">, HelpText<"Don't bind default visibility defined symbols locally for -shared (default)">;
 
 def Bsymbolic: F<"Bsymbolic">, HelpText<"Bind default visibility defined symbols locally for -shared">;
 
 def Bsymbolic_functions: F<"Bsymbolic-functions">,
   HelpText<"Bind default visibility defined function symbols locally for -shared">;
 
 def Bsymbolic_non_weak_functions: F<"Bsymbolic-non-weak-functions">,
   HelpText<"Bind default visibility defined STB_GLOBAL function symbols locally for -shared">;

lld/ELF/ScriptParser.cpp

 }
 
 static std::pair<ELFKind, uint16_t> parseBfdName(StringRef s) {
   return StringSwitch<std::pair<ELFKind, uint16_t>>(s)
       .Case("elf32-i386", {ELF32LEKind, EM_386})
       .Case("elf32-avr", {ELF32LEKind, EM_AVR})
       .Case("elf32-iamcu", {ELF32LEKind, EM_IAMCU})
       .Case("elf32-littlearm", {ELF32LEKind, EM_ARM})
+      .Case("elf32-bigarm", {ELF32BEKind, EM_ARM})
       .Case("elf32-x86-64", {ELF32LEKind, EM_X86_64})
       .Case("elf64-aarch64", {ELF64LEKind, EM_AARCH64})
       .Case("elf64-littleaarch64", {ELF64LEKind, EM_AARCH64})
       .Case("elf64-bigaarch64", {ELF64BEKind, EM_AARCH64})
       .Case("elf32-powerpc", {ELF32BEKind, EM_PPC})
       .Case("elf32-powerpcle", {ELF32LEKind, EM_PPC})
       .Case("elf64-powerpc", {ELF64BEKind, EM_PPC64})
       .Case("elf64-powerpcle", {ELF64LEKind, EM_PPC64})

lld/ELF/Target.h

protected:
   // On Linux this is controlled by vm.mmap_min_addr. At least on some x86_64
   // installs this is set to 65536, so the first 15 pages cannot be used.
   // Given that, the smallest value that can be used in here is 0x10000.
   uint64_t defaultImageBase = 0x10000;
 };
 
 TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
-TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
 TargetInfo *getHexagonTargetInfo();
 TargetInfo *getMSP430TargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
 TargetInfo *getRISCVTargetInfo();
 TargetInfo *getSPARCV9TargetInfo();
 TargetInfo *getX86TargetInfo();
 TargetInfo *getX86_64TargetInfo();
+template <class ELFT> TargetInfo *getARMTargetInfo();
 template <class ELFT> TargetInfo *getMipsTargetInfo();
 
 struct ErrorPlace {
   InputSectionBase *isec;
   std::string loc;
   std::string srcLoc;
 };
 

lld/ELF/Target.cpp

TargetInfo *elf::getTarget() {
   case EM_386:
   case EM_IAMCU:
     return getX86TargetInfo();
   case EM_AARCH64:
     return getAArch64TargetInfo();
   case EM_AMDGPU:
     return getAMDGPUTargetInfo();
   case EM_ARM:
-    return getARMTargetInfo();
+    switch (config->ekind) {
+    case ELF32BEKind:
+      return getARMTargetInfo<ELF32BE>();
+    case ELF32LEKind:
+      return getARMTargetInfo<ELF32LE>();
+    default:
+      llvm_unreachable("unsupported ARM target");
+    }
   case EM_AVR:
     return getAVRTargetInfo();
   case EM_HEXAGON:
     return getHexagonTargetInfo();
   case EM_MIPS:
     switch (config->ekind) {
     case ELF32LEKind:
       return getMipsTargetInfo<ELF32LE>();

lld/ELF/Writer.cpp

template <class ELFT> void Writer<ELFT>::writeHeader() {
   writeEhdr<ELFT>(Out::bufferStart, *mainPart);
   writePhdrs<ELFT>(Out::bufferStart + sizeof(Elf_Ehdr), *mainPart);
 
   auto *eHdr = reinterpret_cast<Elf_Ehdr *>(Out::bufferStart);
   eHdr->e_type = getELFType();
   eHdr->e_entry = getEntryAddr();
   eHdr->e_shoff = sectionHeaderOff;
 
+  if (config->be8 && eHdr->e_type == ET_EXEC && !config->be32)
+    eHdr->e_flags |= 0x00800000;
+
   // Write the section header table.
   //
   // The ELF header can only store numbers up to SHN_LORESERVE in the e_shnum
   // and e_shstrndx fields. When the value of one of these fields exceeds
   // SHN_LORESERVE ELF requires us to put sentinel values in the ELF header and
   // use fields in the section header at index 0 to store
   // the value. The sentinel values and fields are:
   // e_shnum = 0, SHdrs[0].sh_size = number of sections.

lld/docs/ld.lld.1

 .Dv DF_SYMBOLIC
 flag.
 .It Fl Bsymbolic-functions
 Bind default visibility defined function symbols locally for
 .Fl shared.
 .It Fl Bsymbolic-non-weak-functions
 Bind default visibility defined STB_GLOBAL function symbols locally for
 .Fl shared.
+.It Fl --be8
+The default Byte Addressing mode for ARMv6 and later big-endian images. The linker reverses the endianness of the instructions to give little-endian code and big-endian data for input objects that have been compiled or assembled as big-endian.
+.It Fl --be32
+Specifies legacy Word Invariant Addressing big-endian mode, that is, identical to big-endian images prior to ARMv6. This produces big-endian code and data.
 .It Fl -build-id Ns = Ns Ar value
 Generate a build ID note.
 .Ar value
 may be one of
 .Cm fast ,
 .Cm md5 ,
 .Cm sha1 ,
 .Cm tree ,