[RISCV]Keep (select c, 0/-1, X) during PerformDAGCombine

[liaolucy]

Summary

D135833, lowerSelect: (select C, -1/0, X) -> or/and
Keep (select c, 0/-1, X), thus making better use of lowerSelect to eliminate branch instructions.

[craig.topper]

Nothing about the title or commit message gives much of a glue about which existing transformation is being modified. There are quite a few select related optimizations. Can you give more detail?

llvm/test/CodeGen/RISCV/select-binop-identity.ll

1

Can you add new RUN lines with short forward branch enabled?

[liaolucy]

add new RUN lines with -mcpu=sifive-u74

Try to add more optimization details

[liaolucy]

llvm/test/CodeGen/RISCV/select-binop-identity.ll

36

There is an extra instruction here, which seems to be caused by PseudoCCMOVGPR. I'll debug it more carefully, maybe a new patch is needed.

[craig.topper]

llvm/test/CodeGen/RISCV/select-binop-identity.ll

36

The short forward branch optimization does currently require a mv to be in shadow of the branch. Technically the hardware supports most ALU operations in the branch shadow, but that will likely require a pseudo instruction like PseudoCCMOVGPR for each ALU operation to express.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //   -> (select cond, x, (or x, c))  [AllOnes=0]
 // (xor (select cond, 0, c), x)
 //   -> (select cond, x, (xor x, c))  [AllOnes=0]
 // (add (select cond, 0, c), x)
 //   -> (select cond, x, (add x, c))  [AllOnes=0]
 // (sub x, (select cond, 0, c))
 //   -> (select cond, x, (sub x, c))  [AllOnes=0]
 static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
-                                   SelectionDAG &DAG, bool AllOnes) {
+                                   SelectionDAG &DAG, bool AllOnes,
+                                   const RISCVSubtarget &Subtarget) {
   EVT VT = N->getValueType(0);
 
   // Skip vectors.
   if (VT.isVector())
     return SDValue();
 
-  if ((Slct.getOpcode() != ISD::SELECT &&
+  if (!Subtarget.hasShortForwardBranchOpt() ||
+      (Slct.getOpcode() != ISD::SELECT &&
        Slct.getOpcode() != RISCVISD::SELECT_CC) ||
       !Slct.hasOneUse())
     return SDValue();
 
   auto isZeroOrAllOnes = [](SDValue N, bool AllOnes) {
     return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
   };
 
return DAG.getNode(RISCVISD::SELECT_CC, SDLoc(N), VT,
                         Slct.getOperand(2), TrueVal, FalseVal});
 
   return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
                      {Slct.getOperand(0), TrueVal, FalseVal});
 }
 
 // Attempt combineSelectAndUse on each operand of a commutative operator N.
 static SDValue combineSelectAndUseCommutative(SDNode *N, SelectionDAG &DAG,
-                                              bool AllOnes) {
+                                              bool AllOnes,
+                                              const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  if (SDValue Result = combineSelectAndUse(N, N0, N1, DAG, AllOnes))
+  if (SDValue Result = combineSelectAndUse(N, N0, N1, DAG, AllOnes, Subtarget))
     return Result;
-  if (SDValue Result = combineSelectAndUse(N, N1, N0, DAG, AllOnes))
+  if (SDValue Result = combineSelectAndUse(N, N1, N0, DAG, AllOnes, Subtarget))
     return Result;
   return SDValue();
 }
 
 // Transform (add (mul x, c0), c1) ->
 //           (add (mul (add x, c1/c0), c0), c1%c0).
 // if c1/c0 and c1%c0 are simm12, while c1 is not. A special corner case
 // that should be excluded is when c0*(c1/c0) is simm12, which will lead
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = transformAddImmMulImm(N, DAG, Subtarget))
     return V;
   if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
     return V;
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
   // fold (add (select lhs, rhs, cc, 0, y), x) ->
   //      (select lhs, rhs, cc, x, (add x, y))
-  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
+  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Try to turn a sub boolean RHS and constant LHS into an addi.
 static SDValue combineSubOfBoolean(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     NewLHS = N1.getOperand(0);
   } else
     return SDValue();
 
   SDValue NewRHS = DAG.getConstant(ImmValMinus1, DL, VT);
   return DAG.getNode(ISD::ADD, DL, VT, NewLHS, NewRHS);
 }
 
-static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
   if (SDValue V = combineSubOfBoolean(N, DAG))
     return V;
 
   // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
   //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
+  return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Apply DeMorgan's law to (and/or (xor X, 1), (xor Y, 1)) if X and Y are 0/1.
 // Legalizing setcc can introduce xors like this. Doing this transform reduces
 // the number of xors and may allow the xor to fold into a branch condition.
 static SDValue combineDeMorganOfBoolean(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
 
   if (DCI.isAfterLegalizeDAG())
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
 
   // fold (and (select lhs, rhs, cc, -1, y), x) ->
   //      (select lhs, rhs, cc, x, (and x, y))
-  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ true);
+  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ true, Subtarget);
 }
 
 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                                 const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
 
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
 
   if (DCI.isAfterLegalizeDAG())
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
 
   // fold (or (select cond, 0, y), x) ->
   //      (select cond, x, (or x, y))
-  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
+  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
-static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // fold (xor (sllw 1, x), -1) -> (rolw ~1, x)
   // NOTE: Assumes ROL being legal means ROLW is legal.
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   if (N0.getOpcode() == RISCVISD::SLLW &&
       isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0)) &&
       TLI.isOperationLegal(ISD::ROTL, MVT::i64)) {
     SDLoc DL(N);
     return DAG.getNode(RISCVISD::ROLW, DL, MVT::i64,
                        DAG.getConstant(~1, DL, MVT::i64), N0.getOperand(1));
   }
 
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
   // fold (xor (select cond, 0, y), x) ->
   //      (select cond, x, (xor x, y))
-  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
+  return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Replace (seteq (i64 (and X, 0xffffffff)), C1) with
 // (seteq (i64 (sext_inreg (X, i32)), C1')) where C1' is C1 sign extended from
 // bit 31. Same for setne. C1' may be cheaper to materialize and the sext_inreg
 // can become a sext.w instead of a shift pair.
 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
case RISCVISD::FMV_X_ANYEXTW_RV64: {
 
     assert(Op0.getOpcode() == ISD::FABS);
     return DAG.getNode(ISD::AND, DL, VT, NewFMV,
                        DAG.getConstant(~SignBit, DL, VT));
   }
   case ISD::ADD:
     return performADDCombine(N, DAG, Subtarget);
   case ISD::SUB:
-    return performSUBCombine(N, DAG);
+    return performSUBCombine(N, DAG, Subtarget);
   case ISD::AND:
     return performANDCombine(N, DCI, Subtarget);
   case ISD::OR:
     return performORCombine(N, DCI, Subtarget);
   case ISD::XOR:
-    return performXORCombine(N, DAG);
+    return performXORCombine(N, DAG, Subtarget);
   case ISD::FADD:
   case ISD::UMAX:
   case ISD::UMIN:
   case ISD::SMAX:
   case ISD::SMIN:
   case ISD::FMAXNUM:
   case ISD::FMINNUM:
     return combineBinOpToReduce(N, DAG);

llvm/test/CodeGen/RISCV/select-binop-identity.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=SFB64 %s
 
 ; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for
 ; other binary operations using their identity value as the constant.
 
 ; We can reverse this for and/or/xor. Allowing us to pull the binop into
 ; the basic block we create when we expand select.
 
 define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 %y) {
 ; RV32I-LABEL: and_select_all_ones_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a0, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    and a2, a2, a1
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and_select_all_ones_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB0_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    and a2, a2, a1
-; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    sext.w a0, a2
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: and_select_all_ones_i32:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    and a1, a1, a2
+; SFB64-NEXT:    bnez a0, .LBB0_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB0_2:
+; SFB64-NEXT:    sext.w a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
   %b = and i32 %a, %y
   ret i32 %b
 }
 
 define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: and_select_all_ones_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB1_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    and a3, a3, a1
-; RV32I-NEXT:    and a4, a4, a2
-; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a2, a0, a2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    and a0, a3, a0
+; RV32I-NEXT:    and a1, a4, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and_select_all_ones_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB1_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    and a2, a2, a1
-; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: and_select_all_ones_i64:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    and a1, a1, a2
+; SFB64-NEXT:    beqz a0, .LBB1_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB1_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i64 -1, i64 %x
   %b = and i64 %y, %a
   ret i64 %b
 }
 
 define signext i32 @or_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: or_select_all_zeros_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    neg a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: or_select_all_zeros_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: or_select_all_zeros_i32:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    or a1, a1, a2
+; SFB64-NEXT:    bnez a0, .LBB2_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB2_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 0
   %b = or i32 %y, %a
   ret i32 %b
 }
 
 define i64 @or_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: or_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB3_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    or a3, a3, a1
-; RV32I-NEXT:    or a4, a4, a2
-; RV32I-NEXT:  .LBB3_2:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    or a0, a0, a3
+; RV32I-NEXT:    or a1, a2, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: or_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB3_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    or a2, a2, a1
-; RV64I-NEXT:  .LBB3_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: or_select_all_zeros_i64:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    or a1, a1, a2
+; SFB64-NEXT:    beqz a0, .LBB3_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB3_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i64 0, i64 %x
   %b = or i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @xor_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: xor_select_all_zeros_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB4_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    xor a2, a2, a1
-; RV32I-NEXT:  .LBB4_2:
-; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    xor a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: xor_select_all_zeros_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB4_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    xor a2, a2, a1
-; RV64I-NEXT:  .LBB4_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    xor a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: xor_select_all_zeros_i32:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    xor a1, a1, a2
+; SFB64-NEXT:    beqz a0, .LBB4_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB4_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = xor i32 %y, %a
   ret i32 %b
 }
 
 define i64 @xor_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: xor_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    neg a5, a0
-; RV32I-NEXT:    and a0, a5, a1
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    xor a0, a0, a3
-; RV32I-NEXT:    and a1, a5, a2
-; RV32I-NEXT:    xor a1, a1, a4
+; RV32I-NEXT:    xor a1, a2, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: xor_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a2
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: xor_select_all_zeros_i64:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    xor a1, a1, a2
+; SFB64-NEXT:    bnez a0, .LBB5_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB5_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = xor i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @add_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: add_select_all_zeros_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB6_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    add a2, a2, a1
-; RV32I-NEXT:  .LBB6_2:
-; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_select_all_zeros_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB6_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addw a2, a2, a1
-; RV64I-NEXT:  .LBB6_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    addw a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: add_select_all_zeros_i32:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    addw a1, a1, a2
+; SFB64-NEXT:    beqz a0, .LBB6_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB6_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = add i32 %y, %a
   ret i32 %b
 }
 
 define i64 @add_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: add_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a0, .LBB7_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    add a2, a4, a2
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    sltu a4, a1, a3
-; RV32I-NEXT:    add a4, a2, a4
-; RV32I-NEXT:    mv a3, a1
-; RV32I-NEXT:  .LBB7_2:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    and a1, a0, a1
+; RV32I-NEXT:    add a0, a1, a3
+; RV32I-NEXT:    sltu a1, a0, a1
+; RV32I-NEXT:    add a2, a2, a4
+; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB7_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    add a2, a2, a1
-; RV64I-NEXT:  .LBB7_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    add a0, a0, a2
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: add_select_all_zeros_i64:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    add a1, a1, a2
+; SFB64-NEXT:    bnez a0, .LBB7_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB7_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = add i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @sub_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: sub_select_all_zeros_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB8_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sub a2, a2, a1
-; RV32I-NEXT:  .LBB8_2:
-; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sub_select_all_zeros_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB8_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    subw a2, a2, a1
-; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    subw a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: sub_select_all_zeros_i32:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    subw a1, a2, a1
+; SFB64-NEXT:    beqz a0, .LBB8_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB8_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = sub i32 %y, %a
   ret i32 %b
 }
 
 define i64 @sub_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: sub_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a0, .LBB9_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a0, a3, a1
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    sltu a1, a3, a0
 ; RV32I-NEXT:    sub a4, a4, a2
-; RV32I-NEXT:    sub a4, a4, a0
-; RV32I-NEXT:    sub a3, a3, a1
-; RV32I-NEXT:  .LBB9_2:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    sub a1, a4, a1
+; RV32I-NEXT:    sub a0, a3, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sub_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB9_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    sub a2, a2, a1
-; RV64I-NEXT:  .LBB9_2:
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    sub a0, a2, a0
 ; RV64I-NEXT:    ret
+;
+; SFB64-LABEL: sub_select_all_zeros_i64:
+; SFB64:       # %bb.0:
+; SFB64-NEXT:    sub a1, a2, a1
+; SFB64-NEXT:    bnez a0, .LBB9_2
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB9_2:
+; SFB64-NEXT:    mv a0, a1
+; SFB64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = sub i64 %y, %a
   ret i64 %b
 }