[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect

[craig.topper]

Summary

Same with (select C, X, -1), (select C, 0, X), and (select C, X, 0).

There's a DAGCombine after we turn the select into select_cc, but
that may introduce a setcc that didn't previously exist. We could
add more DAGCombines to remove the extra setcc, but this seemed lower
effort.

[reames]

LGTM.

I'm going to glance at the missing DAGCombine and see if the other approach works cleanly; if it does, I may propose removing these.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
 
   // Lower vector SELECTs to VSELECTs by splatting the condition.
   if (VT.isVector()) {
     MVT SplatCondVT = VT.changeVectorElementType(MVT::i1);
     SDValue CondSplat = DAG.getSplat(SplatCondVT, DL, CondV);
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
+  // (select c, -1, y) -> -c | y
+  if (isAllOnesConstant(TrueV)) {
+    SDValue Neg = DAG.getNegative(CondV, DL, VT);
+    return DAG.getNode(ISD::OR, DL, VT, Neg, FalseV);
+  }
+  // (select c, y, -1) -> (c-1) | y
+  if (isAllOnesConstant(FalseV)) {
+    SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,
+                              DAG.getAllOnesConstant(DL, VT));
+    return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV);
+  }
+
+  // (select c, 0, y) -> (c-1) & y
+  if (isNullConstant(TrueV)) {
+    SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,
+                              DAG.getAllOnesConstant(DL, VT));
+    return DAG.getNode(ISD::AND, DL, VT, Neg, FalseV);
+  }
+  // (select c, y, 0) -> -c & y
+  if (isNullConstant(FalseV)) {
+    SDValue Neg = DAG.getNegative(CondV, DL, VT);
+    return DAG.getNode(ISD::AND, DL, VT, Neg, TrueV);
+  }
+
   // If the CondV is the output of a SETCC node which operates on XLenVT inputs,
   // then merge the SETCC node into the lowered RISCVISD::SELECT_CC to take
   // advantage of the integer compare+branch instructions. i.e.:
   // (select (setcc lhs, rhs, cc), truev, falsev)
   // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
   if (CondV.getOpcode() == ISD::SETCC &&
       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
     SDValue LHS = CondV.getOperand(0);

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32I-LABEL: fcvt_wu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 270080
 ; RV32I-NEXT:    addi a3, a0, -1
 ; RV32I-NEXT:    lui a2, 1048064
-; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s2
-; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    bltz a0, .LBB6_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB6_2: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s3, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    call __fixunsdfsi@plt
+; RV32I-NEXT:    and a0, s3, a0
+; RV32I-NEXT:    or a0, s2, a0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

 ; RV32IFD-NEXT:    beqz a2, .LBB12_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB12_4: # %start
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_l_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1
 ; RV64IFD-NEXT:    addi a1, a1, -1
 ; RV64IFD-NEXT:    and a0, a1, a0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_d_sat:
 ; RV32I:       # %bb.0: # %start
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s2, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s3, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s4, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s5, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s6, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s7, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 278016
-; RV32I-NEXT:    addi s3, a0, -1
+; RV32I-NEXT:    addi s2, a0, -1
 ; RV32I-NEXT:    li a2, -1
 ; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a3, s3
+; RV32I-NEXT:    mv a3, s2
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s7, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s5, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfdi@plt
-; RV32I-NEXT:    mv s6, a0
-; RV32I-NEXT:    mv s4, a1
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    lui a0, 524288
+; RV32I-NEXT:    lui s6, 524288
+; RV32I-NEXT:    bltz s5, .LBB12_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv s6, a1
+; RV32I-NEXT:  .LBB12_2: # %start
+; RV32I-NEXT:    blez s4, .LBB12_4
+; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:    addi s6, a0, -1
+; RV32I-NEXT:  .LBB12_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    addi s2, a0, -1
-; RV32I-NEXT:    bgtz s7, .LBB12_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    slti a0, s5, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s6
-; RV32I-NEXT:    and s2, s2, a0
-; RV32I-NEXT:  .LBB12_2: # %start
-; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a3, s3
-; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    and s4, a0, s6
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    lui s5, 524288
-; RV32I-NEXT:    bltz a0, .LBB12_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s5, s4
-; RV32I-NEXT:  .LBB12_4: # %start
-; RV32I-NEXT:    blez s3, .LBB12_6
-; RV32I-NEXT:  # %bb.5:
-; RV32I-NEXT:    addi s5, a1, -1
-; RV32I-NEXT:  .LBB12_6: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and s3, a0, s3
+; RV32I-NEXT:    li a2, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    mv a3, s2
+; RV32I-NEXT:    call __gtdf2@plt
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or s2, a0, s3
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s5
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s2, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s3, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s4, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s5, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s6, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s7, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_l_d_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill

 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    lui a2, %hi(.LCPI14_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI14_0)(a2)
 ; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    neg a2, a2
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a1, s0, a1
 ; RV32IFD-NEXT:    or a1, a2, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret

 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 278272
-; RV32I-NEXT:    addi s3, a0, -1
+; RV32I-NEXT:    addi s2, a0, -1
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a3, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a3, s2
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s1, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    call __fixunsdfdi@plt
-; RV32I-NEXT:    mv s5, a0
-; RV32I-NEXT:    mv s4, a1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    neg s4, a0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    bltz a0, .LBB14_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s1, s1, s5
-; RV32I-NEXT:  .LBB14_2: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s5, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    call __fixunsdfdi@plt
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    and a0, s5, a0
+; RV32I-NEXT:    or s4, s4, a0
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a3, s3
+; RV32I-NEXT:    mv a3, s2
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s3, a0
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    bltz a0, .LBB14_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    or s3, s3, s4
-; RV32I-NEXT:  .LBB14_4: # %start
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, s3
+; RV32I-NEXT:    or a1, s2, a0
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_d_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    mv s0, a0
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    call __gedf2@plt
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    addi s1, a0, -1
+; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    call __fixunsdfdi@plt
+; RV64I-NEXT:    and s1, s1, a0
 ; RV64I-NEXT:    li a0, 1087
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
 ; RV64I-NEXT:    sgtz a0, a0
-; RV64I-NEXT:    neg s0, a0
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    call __fixunsdfdi@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    bltz a0, .LBB14_2
-; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    or s0, s0, s1
-; RV64I-NEXT:  .LBB14_2: # %start
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %0
 }
 declare i64 @llvm.fptoui.sat.i64.f64(double)
 

 ; RV32I-LABEL: fcvt_wu_d_sat_zext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 270080
 ; RV32I-NEXT:    addi a3, a0, -1
 ; RV32I-NEXT:    lui a2, 1048064
-; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s2
-; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    bltz a0, .LBB33_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB33_2: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s3, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    call __fixunsdfsi@plt
+; RV32I-NEXT:    and a0, s3, a0
+; RV32I-NEXT:    or a0, s2, a0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

 ; RV32IFD-NEXT:    beqz a2, .LBB1_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB1_4:
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 }
 
 define i64 @test_floor_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_floor_ui64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call floor@plt
-; RV32IFD-NEXT:    fmv.d fs0, fa0
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI3_0)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s1, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI3_0)(a2)
-; RV32IFD-NEXT:    and a0, s0, a0
-; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a0, a2, a0
-; RV32IFD-NEXT:    and a1, s0, a1
-; RV32IFD-NEXT:    or a1, a2, a1
+; RV32IFD-NEXT:    and a0, s1, a0
+; RV32IFD-NEXT:    or a0, s0, a0
+; RV32IFD-NEXT:    and a1, s1, a1
+; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_floor_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1

 ; RV32IFD-NEXT:    beqz a2, .LBB5_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB5_4:
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 }
 
 define i64 @test_ceil_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_ceil_ui64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call ceil@plt
-; RV32IFD-NEXT:    fmv.d fs0, fa0
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI7_0)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s1, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI7_0)(a2)
-; RV32IFD-NEXT:    and a0, s0, a0
-; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a0, a2, a0
-; RV32IFD-NEXT:    and a1, s0, a1
-; RV32IFD-NEXT:    or a1, a2, a1
+; RV32IFD-NEXT:    and a0, s1, a0
+; RV32IFD-NEXT:    or a0, s0, a0
+; RV32IFD-NEXT:    and a1, s1, a1
+; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_ceil_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1

 ; RV32IFD-NEXT:    beqz a2, .LBB9_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB9_4:
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 }
 
 define i64 @test_trunc_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_trunc_ui64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call trunc@plt
-; RV32IFD-NEXT:    fmv.d fs0, fa0
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s1, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a2)
-; RV32IFD-NEXT:    and a0, s0, a0
-; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a0, a2, a0
-; RV32IFD-NEXT:    and a1, s0, a1
-; RV32IFD-NEXT:    or a1, a2, a1
+; RV32IFD-NEXT:    and a0, s1, a0
+; RV32IFD-NEXT:    or a0, s0, a0
+; RV32IFD-NEXT:    and a1, s1, a1
+; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_trunc_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1

 ; RV32IFD-NEXT:    beqz a2, .LBB13_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB13_4:
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 }
 
 define i64 @test_round_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_round_ui64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call round@plt
-; RV32IFD-NEXT:    fmv.d fs0, fa0
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI15_0)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s1, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI15_0)(a2)
-; RV32IFD-NEXT:    and a0, s0, a0
-; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a0, a2, a0
-; RV32IFD-NEXT:    and a1, s0, a1
-; RV32IFD-NEXT:    or a1, a2, a1
+; RV32IFD-NEXT:    and a0, s1, a0
+; RV32IFD-NEXT:    or a0, s0, a0
+; RV32IFD-NEXT:    and a1, s1, a1
+; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_round_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1

 ; RV32IFD-NEXT:    beqz a2, .LBB17_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB17_4:
 ; RV32IFD-NEXT:    feq.d a3, fs0, fs0
 ; RV32IFD-NEXT:    seqz a3, a3
 ; RV32IFD-NEXT:    addi a3, a3, -1
 ; RV32IFD-NEXT:    and a1, a3, a1
-; RV32IFD-NEXT:    seqz a4, s0
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    neg a4, s0
 ; RV32IFD-NEXT:    and a0, a4, a0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a3, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 }
 
 define i64 @test_roundeven_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_roundeven_ui64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call roundeven@plt
-; RV32IFD-NEXT:    fmv.d fs0, fa0
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI19_0)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a0, ft0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi s0, a0, -1
+; RV32IFD-NEXT:    neg s1, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI19_0)(a2)
-; RV32IFD-NEXT:    and a0, s0, a0
-; RV32IFD-NEXT:    flt.d a2, ft0, fs0
-; RV32IFD-NEXT:    seqz a2, a2
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a0, a2, a0
-; RV32IFD-NEXT:    and a1, s0, a1
-; RV32IFD-NEXT:    or a1, a2, a1
+; RV32IFD-NEXT:    and a0, s1, a0
+; RV32IFD-NEXT:    or a0, s0, a0
+; RV32IFD-NEXT:    and a1, s1, a1
+; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_roundeven_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    seqz a1, a1

llvm/test/CodeGen/RISCV/float-convert.ll

 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s1, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    and s1, s1, a0
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB4_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB4_2: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, s1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill

 ; RV32IF-NEXT:    beqz a2, .LBB12_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB12_4: # %start
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfdi@plt
-; RV32I-NEXT:    mv s5, a0
-; RV32I-NEXT:    mv s2, a1
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui s4, 524288
+; RV32I-NEXT:    lui s3, 524288
+; RV32I-NEXT:    bltz s2, .LBB12_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:  .LBB12_2: # %start
+; RV32I-NEXT:    lui a0, 389120
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    blez a0, .LBB12_4
+; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:    addi s3, s4, -1
+; RV32I-NEXT:  .LBB12_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    addi s1, a0, -1
-; RV32I-NEXT:    lui a0, 389120
-; RV32I-NEXT:    addi s3, a0, -1
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bgtz a0, .LBB12_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    slti a0, s4, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s5
-; RV32I-NEXT:    and s1, s1, a0
-; RV32I-NEXT:  .LBB12_2: # %start
+; RV32I-NEXT:    and s3, a0, s3
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    lui s5, 524288
-; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    bltz a0, .LBB12_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s4, s2
-; RV32I-NEXT:  .LBB12_4: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and s1, a0, s1
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    blez a0, .LBB12_6
-; RV32I-NEXT:  # %bb.5:
-; RV32I-NEXT:    addi s4, s5, -1
-; RV32I-NEXT:  .LBB12_6: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or s1, a0, s1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s4
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_l_s_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill

 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI14_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a2)
 ; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    neg a2, a2
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a1, s0, a1
 ; RV32IF-NEXT:    or a1, a2, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret

 ; RV32I-LABEL: fcvt_lu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfdi@plt
+; RV32I-NEXT:    mv s1, a1
+; RV32I-NEXT:    and s3, s2, a0
 ; RV32I-NEXT:    lui a0, 391168
 ; RV32I-NEXT:    addi s2, a0, -1
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    call __fixunssfdi@plt
-; RV32I-NEXT:    mv s4, a0
-; RV32I-NEXT:    mv s3, a1
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or s3, a0, s3
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB14_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s4
-; RV32I-NEXT:  .LBB14_2: # %start
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and s1, a0, s1
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s2, a0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB14_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    or s2, s2, s3
-; RV32I-NEXT:  .LBB14_4: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a1, a0, s1
+; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_s_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    mv s0, a0
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    call __gesf2@plt
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    addi s1, a0, -1
+; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    call __fixunssfdi@plt
+; RV64I-NEXT:    and s1, s1, a0
 ; RV64I-NEXT:    lui a0, 391168
 ; RV64I-NEXT:    addiw a1, a0, -1
-; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    sgtz a0, a0
-; RV64I-NEXT:    neg s0, a0
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    call __fixunssfdi@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    bltz a0, .LBB14_2
-; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    or s0, s0, s1
-; RV64I-NEXT:  .LBB14_2: # %start
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %0
 }
 declare i64 @llvm.fptoui.sat.i64.f32(float)
 

 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat_zext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s1, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    and s1, s1, a0
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB31_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB31_2: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, s1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat_zext:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; RV32IF-NEXT:    beqz a2, .LBB1_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB1_4:
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call floorf@plt
-; RV32IF-NEXT:    fmv.s fs0, fa0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV32IF-NEXT:    flt.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s1, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    and a0, s1, a0
+; RV32IF-NEXT:    or a0, s0, a0
+; RV32IF-NEXT:    and a1, s1, a1
+; RV32IF-NEXT:    or a1, s0, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1

 ; RV32IF-NEXT:    beqz a2, .LBB5_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB5_4:
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call ceilf@plt
-; RV32IF-NEXT:    fmv.s fs0, fa0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
+; RV32IF-NEXT:    flt.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s1, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    and a0, s1, a0
+; RV32IF-NEXT:    or a0, s0, a0
+; RV32IF-NEXT:    and a1, s1, a1
+; RV32IF-NEXT:    or a1, s0, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1

 ; RV32IF-NEXT:    beqz a2, .LBB9_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB9_4:
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call truncf@plt
-; RV32IF-NEXT:    fmv.s fs0, fa0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
+; RV32IF-NEXT:    flt.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s1, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    and a0, s1, a0
+; RV32IF-NEXT:    or a0, s0, a0
+; RV32IF-NEXT:    and a1, s1, a1
+; RV32IF-NEXT:    or a1, s0, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1

 ; RV32IF-NEXT:    beqz a2, .LBB13_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB13_4:
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundf@plt
-; RV32IF-NEXT:    fmv.s fs0, fa0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
+; RV32IF-NEXT:    flt.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s1, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    and a0, s1, a0
+; RV32IF-NEXT:    or a0, s0, a0
+; RV32IF-NEXT:    and a1, s1, a1
+; RV32IF-NEXT:    or a1, s0, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1

 ; RV32IF-NEXT:    beqz a2, .LBB17_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB17_4:
 ; RV32IF-NEXT:    feq.s a3, fs0, fs0
 ; RV32IF-NEXT:    seqz a3, a3
 ; RV32IF-NEXT:    addi a3, a3, -1
 ; RV32IF-NEXT:    and a1, a3, a1
-; RV32IF-NEXT:    seqz a4, s0
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    neg a4, s0
 ; RV32IF-NEXT:    and a0, a4, a0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a3, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundevenf@plt
-; RV32IF-NEXT:    fmv.s fs0, fa0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
+; RV32IF-NEXT:    flt.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
 ; RV32IF-NEXT:    fle.s a0, ft0, fa0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi s0, a0, -1
+; RV32IF-NEXT:    neg s1, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, ft0, fs0
-; RV32IF-NEXT:    seqz a2, a2
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    and a0, s1, a0
+; RV32IF-NEXT:    or a0, s0, a0
+; RV32IF-NEXT:    and a1, s1, a1
+; RV32IF-NEXT:    or a1, s0, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1

llvm/test/CodeGen/RISCV/forced-atomics.ll

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    lw a1, 4(a0)
 ; RV32-NEXT:    lw a4, 0(a0)
 ; RV32-NEXT:    j .LBB49_2
 ; RV32-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV32-NEXT:    # in Loop: Header=BB49_2 Depth=1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a3, a0, a1
 ; RV32-NEXT:    sw a4, 0(sp)
 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    mv a1, sp
 ; RV32-NEXT:    li a4, 5
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call __atomic_compare_exchange_8@plt

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    lw a1, 4(a0)
 ; RV32-NEXT:    lw a4, 0(a0)
 ; RV32-NEXT:    j .LBB50_2
 ; RV32-NEXT:  .LBB50_1: # %atomicrmw.start
 ; RV32-NEXT:    # in Loop: Header=BB50_2 Depth=1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a3, a0, a1
 ; RV32-NEXT:    sw a4, 0(sp)
 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    mv a1, sp
 ; RV32-NEXT:    li a4, 5
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call __atomic_compare_exchange_8@plt

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    lw a1, 4(a0)
 ; RV32-NEXT:    lw a4, 0(a0)
 ; RV32-NEXT:    j .LBB51_2
 ; RV32-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV32-NEXT:    # in Loop: Header=BB51_2 Depth=1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a3, a0, a1
 ; RV32-NEXT:    sw a4, 0(sp)
 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    mv a1, sp
 ; RV32-NEXT:    li a4, 5
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call __atomic_compare_exchange_8@plt

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    lw a1, 4(a0)
 ; RV32-NEXT:    lw a4, 0(a0)
 ; RV32-NEXT:    j .LBB52_2
 ; RV32-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV32-NEXT:    # in Loop: Header=BB52_2 Depth=1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a3, a0, a1
 ; RV32-NEXT:    sw a4, 0(sp)
 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    mv a1, sp
 ; RV32-NEXT:    li a4, 5
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call __atomic_compare_exchange_8@plt

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    addi a3, a2, -1
 ; RV32IF-NEXT:    beqz a1, .LBB0_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a4, a1, 0
 ; RV32IF-NEXT:    j .LBB0_3
 ; RV32IF-NEXT:  .LBB0_2:
 ; RV32IF-NEXT:    sltu a4, a0, a3
 ; RV32IF-NEXT:  .LBB0_3: # %entry
-; RV32IF-NEXT:    seqz a5, a4
-; RV32IF-NEXT:    addi a5, a5, -1
+; RV32IF-NEXT:    neg a5, a4
 ; RV32IF-NEXT:    and a1, a5, a1
 ; RV32IF-NEXT:    bnez a4, .LBB0_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:  .LBB0_5: # %entry
 ; RV32IF-NEXT:    li a3, -1
 ; RV32IF-NEXT:    beq a1, a3, .LBB0_7
 ; RV32IF-NEXT:  # %bb.6: # %entry

 ; RV32IF-NEXT:    call __fixdfdi@plt
 ; RV32IF-NEXT:    beqz a1, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a2, a1, 0
 ; RV32IF-NEXT:    j .LBB2_3
 ; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    sltiu a2, a0, -1
 ; RV32IF-NEXT:  .LBB2_3: # %entry
-; RV32IF-NEXT:    snez a2, a2
 ; RV32IF-NEXT:    addi a3, a2, -1
 ; RV32IF-NEXT:    neg a2, a2
 ; RV32IF-NEXT:    and a1, a2, a1
 ; RV32IF-NEXT:    or a0, a3, a0
 ; RV32IF-NEXT:    beqz a1, .LBB2_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    sgtz a1, a1
 ; RV32IF-NEXT:    j .LBB2_6
 ; RV32IF-NEXT:  .LBB2_5:
 ; RV32IF-NEXT:    snez a1, a0
 ; RV32IF-NEXT:  .LBB2_6: # %entry
-; RV32IF-NEXT:    seqz a1, a1
-; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    neg a1, a1
 ; RV32IF-NEXT:    and a0, a1, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: ustest_f64i32:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16

 ; RV32-NEXT:    addi a3, a2, -1
 ; RV32-NEXT:    beqz a1, .LBB6_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a4, a1, 0
 ; RV32-NEXT:    j .LBB6_3
 ; RV32-NEXT:  .LBB6_2:
 ; RV32-NEXT:    sltu a4, a0, a3
 ; RV32-NEXT:  .LBB6_3: # %entry
-; RV32-NEXT:    seqz a5, a4
-; RV32-NEXT:    addi a5, a5, -1
+; RV32-NEXT:    neg a5, a4
 ; RV32-NEXT:    and a1, a5, a1
 ; RV32-NEXT:    bnez a4, .LBB6_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB6_5: # %entry
 ; RV32-NEXT:    li a3, -1
 ; RV32-NEXT:    beq a1, a3, .LBB6_7
 ; RV32-NEXT:  # %bb.6: # %entry

 ; RV32-NEXT:    call __fixsfdi@plt
 ; RV32-NEXT:    beqz a1, .LBB8_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB8_3
 ; RV32-NEXT:  .LBB8_2:
 ; RV32-NEXT:    sltiu a2, a0, -1
 ; RV32-NEXT:  .LBB8_3: # %entry
-; RV32-NEXT:    snez a2, a2
 ; RV32-NEXT:    addi a3, a2, -1
 ; RV32-NEXT:    neg a2, a2
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a3, a0
 ; RV32-NEXT:    beqz a1, .LBB8_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    sgtz a1, a1
 ; RV32-NEXT:    j .LBB8_6
 ; RV32-NEXT:  .LBB8_5:
 ; RV32-NEXT:    snez a1, a0
 ; RV32-NEXT:  .LBB8_6: # %entry
-; RV32-NEXT:    seqz a1, a1
-; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    neg a1, a1
 ; RV32-NEXT:    and a0, a1, a0
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16

 ; RV32IF-NEXT:    j .LBB18_4
 ; RV32IF-NEXT:  .LBB18_2:
 ; RV32IF-NEXT:    sltiu a6, a4, -1
 ; RV32IF-NEXT:    or a7, a2, a0
 ; RV32IF-NEXT:    beqz a7, .LBB18_4
 ; RV32IF-NEXT:  .LBB18_3: # %entry
 ; RV32IF-NEXT:    slti a6, a0, 0
 ; RV32IF-NEXT:  .LBB18_4: # %entry
-; RV32IF-NEXT:    seqz t0, a6
-; RV32IF-NEXT:    addi a7, t0, -1
-; RV32IF-NEXT:    neg t0, t0
+; RV32IF-NEXT:    neg a7, a6
+; RV32IF-NEXT:    addi t0, a6, -1
 ; RV32IF-NEXT:    bnez a6, .LBB18_6
 ; RV32IF-NEXT:  # %bb.5: # %entry
 ; RV32IF-NEXT:    mv a1, a5
 ; RV32IF-NEXT:  .LBB18_6: # %entry
 ; RV32IF-NEXT:    or a4, t0, a4
 ; RV32IF-NEXT:    and a5, a7, a0
 ; RV32IF-NEXT:    and a2, a7, a2
 ; RV32IF-NEXT:    beq a1, a3, .LBB18_8

 ; RV32IF-NEXT:  # %bb.10: # %entry
 ; RV32IF-NEXT:    slti a0, a5, 0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:  .LBB18_11: # %entry
 ; RV32IF-NEXT:    bnez a0, .LBB18_13
 ; RV32IF-NEXT:  # %bb.12: # %entry
 ; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB18_13: # %entry
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi a0, a0, -1
+; RV32IF-NEXT:    neg a0, a0
 ; RV32IF-NEXT:    and a0, a0, a4
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: stest_f64i64:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    .cfi_offset ra, -8
 ; RV64IF-NEXT:    call __fixdfti@plt
 ; RV64IF-NEXT:    li a2, -1
 ; RV64IF-NEXT:    srli a3, a2, 1
 ; RV64IF-NEXT:    beqz a1, .LBB18_2
 ; RV64IF-NEXT:  # %bb.1: # %entry
 ; RV64IF-NEXT:    slti a4, a1, 0
 ; RV64IF-NEXT:    j .LBB18_3
 ; RV64IF-NEXT:  .LBB18_2:
 ; RV64IF-NEXT:    sltu a4, a0, a3
 ; RV64IF-NEXT:  .LBB18_3: # %entry
-; RV64IF-NEXT:    seqz a5, a4
-; RV64IF-NEXT:    addi a5, a5, -1
+; RV64IF-NEXT:    neg a5, a4
 ; RV64IF-NEXT:    and a5, a5, a1
 ; RV64IF-NEXT:    bnez a4, .LBB18_5
 ; RV64IF-NEXT:  # %bb.4: # %entry
 ; RV64IF-NEXT:    mv a0, a3
 ; RV64IF-NEXT:  .LBB18_5: # %entry
 ; RV64IF-NEXT:    slli a1, a2, 63
 ; RV64IF-NEXT:    beq a5, a2, .LBB18_7
 ; RV64IF-NEXT:  # %bb.6: # %entry

 ; RV32IFD-NEXT:    j .LBB18_4
 ; RV32IFD-NEXT:  .LBB18_2:
 ; RV32IFD-NEXT:    sltiu a6, a4, -1
 ; RV32IFD-NEXT:    or a7, a2, a0
 ; RV32IFD-NEXT:    beqz a7, .LBB18_4
 ; RV32IFD-NEXT:  .LBB18_3: # %entry
 ; RV32IFD-NEXT:    slti a6, a0, 0
 ; RV32IFD-NEXT:  .LBB18_4: # %entry
-; RV32IFD-NEXT:    seqz t0, a6
-; RV32IFD-NEXT:    addi a7, t0, -1
-; RV32IFD-NEXT:    neg t0, t0
+; RV32IFD-NEXT:    neg a7, a6
+; RV32IFD-NEXT:    addi t0, a6, -1
 ; RV32IFD-NEXT:    bnez a6, .LBB18_6
 ; RV32IFD-NEXT:  # %bb.5: # %entry
 ; RV32IFD-NEXT:    mv a1, a5
 ; RV32IFD-NEXT:  .LBB18_6: # %entry
 ; RV32IFD-NEXT:    or a4, t0, a4
 ; RV32IFD-NEXT:    and a5, a7, a0
 ; RV32IFD-NEXT:    and a2, a7, a2
 ; RV32IFD-NEXT:    beq a1, a3, .LBB18_8

 ; RV32IFD-NEXT:  # %bb.10: # %entry
 ; RV32IFD-NEXT:    slti a0, a5, 0
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:  .LBB18_11: # %entry
 ; RV32IFD-NEXT:    bnez a0, .LBB18_13
 ; RV32IFD-NEXT:  # %bb.12: # %entry
 ; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB18_13: # %entry
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi a0, a0, -1
+; RV32IFD-NEXT:    neg a0, a0
 ; RV32IFD-NEXT:    and a0, a0, a4
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: stest_f64i64:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz

 ; RV32IF-NEXT:    snez a5, a1
 ; RV32IF-NEXT:    addi a5, a5, -1
 ; RV32IF-NEXT:    and a4, a5, a4
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    addi a0, a0, -1
 ; RV32IF-NEXT:    and a0, a0, a4
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi a1, a0, -1
+; RV32IF-NEXT:    neg a1, a0
 ; RV32IF-NEXT:    and a0, a1, a3
 ; RV32IF-NEXT:    and a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f64i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32IFD-NEXT:    snez a5, a1
 ; RV32IFD-NEXT:    addi a5, a5, -1
 ; RV32IFD-NEXT:    and a4, a5, a4
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    seqz a0, a0
 ; RV32IFD-NEXT:    addi a0, a0, -1
 ; RV32IFD-NEXT:    and a0, a0, a4
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi a1, a0, -1
+; RV32IFD-NEXT:    neg a1, a0
 ; RV32IFD-NEXT:    and a0, a1, a3
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptoui double %x to i128
   %0 = icmp ult i128 %conv, 18446744073709551616

 ; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    beqz a1, .LBB20_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a2, a1, 0
 ; RV32IF-NEXT:    j .LBB20_3
 ; RV32IF-NEXT:  .LBB20_2:
 ; RV32IF-NEXT:    seqz a2, a0
 ; RV32IF-NEXT:  .LBB20_3: # %entry
-; RV32IF-NEXT:    lw a4, 12(sp)
-; RV32IF-NEXT:    xori a3, a0, 1
-; RV32IF-NEXT:    or a3, a3, a1
-; RV32IF-NEXT:    seqz a3, a3
-; RV32IF-NEXT:    addi a3, a3, -1
-; RV32IF-NEXT:    and a2, a3, a2
-; RV32IF-NEXT:    seqz a3, a2
-; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    lw a3, 12(sp)
+; RV32IF-NEXT:    xori a4, a0, 1
+; RV32IF-NEXT:    or a4, a4, a1
+; RV32IF-NEXT:    seqz a4, a4
+; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    and a2, a4, a2
+; RV32IF-NEXT:    neg a4, a2
 ; RV32IF-NEXT:    bnez a2, .LBB20_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB20_5: # %entry
 ; RV32IF-NEXT:    lw a5, 8(sp)
-; RV32IF-NEXT:    and a2, a3, a1
-; RV32IF-NEXT:    and a1, a3, a4
+; RV32IF-NEXT:    and a2, a4, a1
+; RV32IF-NEXT:    and a1, a4, a3
 ; RV32IF-NEXT:    beqz a2, .LBB20_8
 ; RV32IF-NEXT:  # %bb.6: # %entry
-; RV32IF-NEXT:    sgtz a4, a2
-; RV32IF-NEXT:    and a3, a3, a5
+; RV32IF-NEXT:    sgtz a3, a2
+; RV32IF-NEXT:    and a4, a4, a5
 ; RV32IF-NEXT:    bnez a1, .LBB20_9
 ; RV32IF-NEXT:  .LBB20_7:
-; RV32IF-NEXT:    snez a5, a3
+; RV32IF-NEXT:    snez a5, a4
 ; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:    bnez a0, .LBB20_10
 ; RV32IF-NEXT:    j .LBB20_11
 ; RV32IF-NEXT:  .LBB20_8:
-; RV32IF-NEXT:    snez a4, a0
-; RV32IF-NEXT:    and a3, a3, a5
+; RV32IF-NEXT:    snez a3, a0
+; RV32IF-NEXT:    and a4, a4, a5
 ; RV32IF-NEXT:    beqz a1, .LBB20_7
 ; RV32IF-NEXT:  .LBB20_9: # %entry
 ; RV32IF-NEXT:    snez a5, a1
 ; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:    beqz a0, .LBB20_11
 ; RV32IF-NEXT:  .LBB20_10: # %entry
-; RV32IF-NEXT:    mv a5, a4
+; RV32IF-NEXT:    mv a5, a3
 ; RV32IF-NEXT:  .LBB20_11: # %entry
-; RV32IF-NEXT:    seqz a0, a5
-; RV32IF-NEXT:    addi a2, a0, -1
-; RV32IF-NEXT:    and a0, a2, a3
+; RV32IF-NEXT:    neg a2, a5
+; RV32IF-NEXT:    and a0, a2, a4
 ; RV32IF-NEXT:    and a1, a2, a1
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f64i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixdfti@plt
-; RV64-NEXT:    mv a2, a1
+; RV64-NEXT:    slti a2, a1, 1
 ; RV64-NEXT:    blez a1, .LBB20_2
 ; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    li a2, 1
+; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB20_2: # %entry
-; RV64-NEXT:    sgtz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
-; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB20_4
+; RV64-NEXT:    neg a2, a2
+; RV64-NEXT:    and a0, a2, a0
+; RV64-NEXT:    beqz a1, .LBB20_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
+; RV64-NEXT:    sgtz a1, a1
 ; RV64-NEXT:    j .LBB20_5
 ; RV64-NEXT:  .LBB20_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:  .LBB20_5: # %entry
-; RV64-NEXT:    seqz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
+; RV64-NEXT:    neg a1, a1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 ;
 ; RV32IFD-LABEL: ustest_f64i64:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixdfti@plt
 ; RV32IFD-NEXT:    lw a1, 20(sp)
 ; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    beqz a1, .LBB20_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    slti a2, a1, 0
 ; RV32IFD-NEXT:    j .LBB20_3
 ; RV32IFD-NEXT:  .LBB20_2:
 ; RV32IFD-NEXT:    seqz a2, a0
 ; RV32IFD-NEXT:  .LBB20_3: # %entry
-; RV32IFD-NEXT:    lw a4, 12(sp)
-; RV32IFD-NEXT:    xori a3, a0, 1
-; RV32IFD-NEXT:    or a3, a3, a1
-; RV32IFD-NEXT:    seqz a3, a3
-; RV32IFD-NEXT:    addi a3, a3, -1
-; RV32IFD-NEXT:    and a2, a3, a2
-; RV32IFD-NEXT:    seqz a3, a2
-; RV32IFD-NEXT:    addi a3, a3, -1
+; RV32IFD-NEXT:    lw a3, 12(sp)
+; RV32IFD-NEXT:    xori a4, a0, 1
+; RV32IFD-NEXT:    or a4, a4, a1
+; RV32IFD-NEXT:    seqz a4, a4
+; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    and a2, a4, a2
+; RV32IFD-NEXT:    neg a4, a2
 ; RV32IFD-NEXT:    bnez a2, .LBB20_5
 ; RV32IFD-NEXT:  # %bb.4: # %entry
 ; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB20_5: # %entry
 ; RV32IFD-NEXT:    lw a5, 8(sp)
-; RV32IFD-NEXT:    and a2, a3, a1
-; RV32IFD-NEXT:    and a1, a3, a4
+; RV32IFD-NEXT:    and a2, a4, a1
+; RV32IFD-NEXT:    and a1, a4, a3
 ; RV32IFD-NEXT:    beqz a2, .LBB20_8
 ; RV32IFD-NEXT:  # %bb.6: # %entry
-; RV32IFD-NEXT:    sgtz a4, a2
-; RV32IFD-NEXT:    and a3, a3, a5
+; RV32IFD-NEXT:    sgtz a3, a2
+; RV32IFD-NEXT:    and a4, a4, a5
 ; RV32IFD-NEXT:    bnez a1, .LBB20_9
 ; RV32IFD-NEXT:  .LBB20_7:
-; RV32IFD-NEXT:    snez a5, a3
+; RV32IFD-NEXT:    snez a5, a4
 ; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:    bnez a0, .LBB20_10
 ; RV32IFD-NEXT:    j .LBB20_11
 ; RV32IFD-NEXT:  .LBB20_8:
-; RV32IFD-NEXT:    snez a4, a0
-; RV32IFD-NEXT:    and a3, a3, a5
+; RV32IFD-NEXT:    snez a3, a0
+; RV32IFD-NEXT:    and a4, a4, a5
 ; RV32IFD-NEXT:    beqz a1, .LBB20_7
 ; RV32IFD-NEXT:  .LBB20_9: # %entry
 ; RV32IFD-NEXT:    snez a5, a1
 ; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:    beqz a0, .LBB20_11
 ; RV32IFD-NEXT:  .LBB20_10: # %entry
-; RV32IFD-NEXT:    mv a5, a4
+; RV32IFD-NEXT:    mv a5, a3
 ; RV32IFD-NEXT:  .LBB20_11: # %entry
-; RV32IFD-NEXT:    seqz a0, a5
-; RV32IFD-NEXT:    addi a2, a0, -1
-; RV32IFD-NEXT:    and a0, a2, a3
+; RV32IFD-NEXT:    neg a2, a5
+; RV32IFD-NEXT:    and a0, a2, a4
 ; RV32IFD-NEXT:    and a1, a2, a1
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptosi double %x to i128
   %0 = icmp slt i128 %conv, 18446744073709551616
   %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616

 ; RV32-NEXT:    j .LBB21_4
 ; RV32-NEXT:  .LBB21_2:
 ; RV32-NEXT:    sltiu a6, a4, -1
 ; RV32-NEXT:    or a7, a2, a0
 ; RV32-NEXT:    beqz a7, .LBB21_4
 ; RV32-NEXT:  .LBB21_3: # %entry
 ; RV32-NEXT:    slti a6, a0, 0
 ; RV32-NEXT:  .LBB21_4: # %entry
-; RV32-NEXT:    seqz t0, a6
-; RV32-NEXT:    addi a7, t0, -1
-; RV32-NEXT:    neg t0, t0
+; RV32-NEXT:    neg a7, a6
+; RV32-NEXT:    addi t0, a6, -1
 ; RV32-NEXT:    bnez a6, .LBB21_6
 ; RV32-NEXT:  # %bb.5: # %entry
 ; RV32-NEXT:    mv a1, a5
 ; RV32-NEXT:  .LBB21_6: # %entry
 ; RV32-NEXT:    or a4, t0, a4
 ; RV32-NEXT:    and a5, a7, a0
 ; RV32-NEXT:    and a2, a7, a2
 ; RV32-NEXT:    beq a1, a3, .LBB21_8

 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    slti a0, a5, 0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:  .LBB21_11: # %entry
 ; RV32-NEXT:    bnez a0, .LBB21_13
 ; RV32-NEXT:  # %bb.12: # %entry
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB21_13: # %entry
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a0, a0, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fcvt.l.s a0, fa0, rtz

 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    addi a5, a5, -1
 ; RV32-NEXT:    and a4, a5, a4
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a1, a0, -1
+; RV32-NEXT:    neg a1, a0
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a1, a1, a2
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f32i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    beqz a1, .LBB23_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB23_3
 ; RV32-NEXT:  .LBB23_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB23_3: # %entry
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    xori a3, a0, 1
-; RV32-NEXT:    or a3, a3, a1
-; RV32-NEXT:    seqz a3, a3
-; RV32-NEXT:    addi a3, a3, -1
-; RV32-NEXT:    and a2, a3, a2
-; RV32-NEXT:    seqz a3, a2
-; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    lw a3, 12(sp)
+; RV32-NEXT:    xori a4, a0, 1
+; RV32-NEXT:    or a4, a4, a1
+; RV32-NEXT:    seqz a4, a4
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    and a2, a4, a2
+; RV32-NEXT:    neg a4, a2
 ; RV32-NEXT:    bnez a2, .LBB23_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB23_5: # %entry
 ; RV32-NEXT:    lw a5, 8(sp)
-; RV32-NEXT:    and a2, a3, a1
-; RV32-NEXT:    and a1, a3, a4
+; RV32-NEXT:    and a2, a4, a1
+; RV32-NEXT:    and a1, a4, a3
 ; RV32-NEXT:    beqz a2, .LBB23_8
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    sgtz a4, a2
-; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    sgtz a3, a2
+; RV32-NEXT:    and a4, a4, a5
 ; RV32-NEXT:    bnez a1, .LBB23_9
 ; RV32-NEXT:  .LBB23_7:
-; RV32-NEXT:    snez a5, a3
+; RV32-NEXT:    snez a5, a4
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    bnez a0, .LBB23_10
 ; RV32-NEXT:    j .LBB23_11
 ; RV32-NEXT:  .LBB23_8:
-; RV32-NEXT:    snez a4, a0
-; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    snez a3, a0
+; RV32-NEXT:    and a4, a4, a5
 ; RV32-NEXT:    beqz a1, .LBB23_7
 ; RV32-NEXT:  .LBB23_9: # %entry
 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    beqz a0, .LBB23_11
 ; RV32-NEXT:  .LBB23_10: # %entry
-; RV32-NEXT:    mv a5, a4
+; RV32-NEXT:    mv a5, a3
 ; RV32-NEXT:  .LBB23_11: # %entry
-; RV32-NEXT:    seqz a0, a5
-; RV32-NEXT:    addi a2, a0, -1
-; RV32-NEXT:    and a0, a2, a3
+; RV32-NEXT:    neg a2, a5
+; RV32-NEXT:    and a0, a2, a4
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixsfti@plt
-; RV64-NEXT:    mv a2, a1
+; RV64-NEXT:    slti a2, a1, 1
 ; RV64-NEXT:    blez a1, .LBB23_2
 ; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    li a2, 1
+; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB23_2: # %entry
-; RV64-NEXT:    sgtz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
-; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB23_4
+; RV64-NEXT:    neg a2, a2
+; RV64-NEXT:    and a0, a2, a0
+; RV64-NEXT:    beqz a1, .LBB23_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
+; RV64-NEXT:    sgtz a1, a1
 ; RV64-NEXT:    j .LBB23_5
 ; RV64-NEXT:  .LBB23_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:  .LBB23_5: # %entry
-; RV64-NEXT:    seqz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
+; RV64-NEXT:    neg a1, a1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 entry:
   %conv = fptosi float %x to i128
   %0 = icmp slt i128 %conv, 18446744073709551616
   %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616

 ; RV32-NEXT:    j .LBB24_4
 ; RV32-NEXT:  .LBB24_2:
 ; RV32-NEXT:    sltiu a6, a4, -1
 ; RV32-NEXT:    or a7, a2, a0
 ; RV32-NEXT:    beqz a7, .LBB24_4
 ; RV32-NEXT:  .LBB24_3: # %entry
 ; RV32-NEXT:    slti a6, a0, 0
 ; RV32-NEXT:  .LBB24_4: # %entry
-; RV32-NEXT:    seqz t0, a6
-; RV32-NEXT:    addi a7, t0, -1
-; RV32-NEXT:    neg t0, t0
+; RV32-NEXT:    neg a7, a6
+; RV32-NEXT:    addi t0, a6, -1
 ; RV32-NEXT:    bnez a6, .LBB24_6
 ; RV32-NEXT:  # %bb.5: # %entry
 ; RV32-NEXT:    mv a1, a5
 ; RV32-NEXT:  .LBB24_6: # %entry
 ; RV32-NEXT:    or a4, t0, a4
 ; RV32-NEXT:    and a5, a7, a0
 ; RV32-NEXT:    and a2, a7, a2
 ; RV32-NEXT:    beq a1, a3, .LBB24_8

 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    slti a0, a5, 0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:  .LBB24_11: # %entry
 ; RV32-NEXT:    bnez a0, .LBB24_13
 ; RV32-NEXT:  # %bb.12: # %entry
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB24_13: # %entry
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    and a0, a0, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f16i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0
 ; RV64-NEXT:    call __extendhfsf2@plt
 ; RV64-NEXT:    call __fixsfti@plt
 ; RV64-NEXT:    li a2, -1
 ; RV64-NEXT:    srli a3, a2, 1
 ; RV64-NEXT:    beqz a1, .LBB24_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    slti a4, a1, 0
 ; RV64-NEXT:    j .LBB24_3
 ; RV64-NEXT:  .LBB24_2:
 ; RV64-NEXT:    sltu a4, a0, a3
 ; RV64-NEXT:  .LBB24_3: # %entry
-; RV64-NEXT:    seqz a5, a4
-; RV64-NEXT:    addi a5, a5, -1
+; RV64-NEXT:    neg a5, a4
 ; RV64-NEXT:    and a5, a5, a1
 ; RV64-NEXT:    bnez a4, .LBB24_5
 ; RV64-NEXT:  # %bb.4: # %entry
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:  .LBB24_5: # %entry
 ; RV64-NEXT:    slli a1, a2, 63
 ; RV64-NEXT:    beq a5, a2, .LBB24_7
 ; RV64-NEXT:  # %bb.6: # %entry

 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    addi a5, a5, -1
 ; RV32-NEXT:    and a4, a5, a4
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a1, a0, -1
+; RV32-NEXT:    neg a1, a0
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a1, a1, a2
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utesth_f16i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    beqz a1, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB26_3
 ; RV32-NEXT:  .LBB26_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB26_3: # %entry
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    xori a3, a0, 1
-; RV32-NEXT:    or a3, a3, a1
-; RV32-NEXT:    seqz a3, a3
-; RV32-NEXT:    addi a3, a3, -1
-; RV32-NEXT:    and a2, a3, a2
-; RV32-NEXT:    seqz a3, a2
-; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    lw a3, 12(sp)
+; RV32-NEXT:    xori a4, a0, 1
+; RV32-NEXT:    or a4, a4, a1
+; RV32-NEXT:    seqz a4, a4
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    and a2, a4, a2
+; RV32-NEXT:    neg a4, a2
 ; RV32-NEXT:    bnez a2, .LBB26_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB26_5: # %entry
 ; RV32-NEXT:    lw a5, 8(sp)
-; RV32-NEXT:    and a2, a3, a1
-; RV32-NEXT:    and a1, a3, a4
+; RV32-NEXT:    and a2, a4, a1
+; RV32-NEXT:    and a1, a4, a3
 ; RV32-NEXT:    beqz a2, .LBB26_8
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    sgtz a4, a2
-; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    sgtz a3, a2
+; RV32-NEXT:    and a4, a4, a5
 ; RV32-NEXT:    bnez a1, .LBB26_9
 ; RV32-NEXT:  .LBB26_7:
-; RV32-NEXT:    snez a5, a3
+; RV32-NEXT:    snez a5, a4
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    bnez a0, .LBB26_10
 ; RV32-NEXT:    j .LBB26_11
 ; RV32-NEXT:  .LBB26_8:
-; RV32-NEXT:    snez a4, a0
-; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    snez a3, a0
+; RV32-NEXT:    and a4, a4, a5
 ; RV32-NEXT:    beqz a1, .LBB26_7
 ; RV32-NEXT:  .LBB26_9: # %entry
 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    beqz a0, .LBB26_11
 ; RV32-NEXT:  .LBB26_10: # %entry
-; RV32-NEXT:    mv a5, a4
+; RV32-NEXT:    mv a5, a3
 ; RV32-NEXT:  .LBB26_11: # %entry
-; RV32-NEXT:    seqz a0, a5
-; RV32-NEXT:    addi a2, a0, -1
-; RV32-NEXT:    and a0, a2, a3
+; RV32-NEXT:    neg a2, a5
+; RV32-NEXT:    and a0, a2, a4
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0
 ; RV64-NEXT:    call __extendhfsf2@plt
 ; RV64-NEXT:    call __fixsfti@plt
-; RV64-NEXT:    mv a2, a1
+; RV64-NEXT:    slti a2, a1, 1
 ; RV64-NEXT:    blez a1, .LBB26_2
 ; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    li a2, 1
+; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB26_2: # %entry
-; RV64-NEXT:    sgtz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
-; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB26_4
+; RV64-NEXT:    neg a2, a2
+; RV64-NEXT:    and a0, a2, a0
+; RV64-NEXT:    beqz a1, .LBB26_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
+; RV64-NEXT:    sgtz a1, a1
 ; RV64-NEXT:    j .LBB26_5
 ; RV64-NEXT:  .LBB26_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:  .LBB26_5: # %entry
-; RV64-NEXT:    seqz a1, a1
-; RV64-NEXT:    addi a1, a1, -1
+; RV64-NEXT:    neg a1, a1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 entry:
   %conv = fptosi half %x to i128
   %0 = icmp slt i128 %conv, 18446744073709551616
   %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616

 ; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    lw a1, 20(sp)
 ; RV32IF-NEXT:    lw a2, 12(sp)
 ; RV32IF-NEXT:    lw a3, 8(sp)
 ; RV32IF-NEXT:    seqz a4, a0
 ; RV32IF-NEXT:    snez a5, a1
 ; RV32IF-NEXT:    addi a5, a5, -1
 ; RV32IF-NEXT:    and a4, a5, a4
-; RV32IF-NEXT:    seqz a4, a4
-; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    neg a4, a4
 ; RV32IF-NEXT:    and a3, a4, a3
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    addi a1, a0, -1
 ; RV32IF-NEXT:    and a0, a1, a3
 ; RV32IF-NEXT:    and a2, a4, a2
 ; RV32IF-NEXT:    and a1, a1, a2

 ; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    lw a1, 20(sp)
 ; RV32IFD-NEXT:    lw a2, 12(sp)
 ; RV32IFD-NEXT:    lw a3, 8(sp)
 ; RV32IFD-NEXT:    seqz a4, a0
 ; RV32IFD-NEXT:    snez a5, a1
 ; RV32IFD-NEXT:    addi a5, a5, -1
 ; RV32IFD-NEXT:    and a4, a5, a4
-; RV32IFD-NEXT:    seqz a4, a4
-; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    neg a4, a4
 ; RV32IFD-NEXT:    and a3, a4, a3
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    seqz a0, a0
 ; RV32IFD-NEXT:    addi a1, a0, -1
 ; RV32IFD-NEXT:    and a0, a1, a3
 ; RV32IFD-NEXT:    and a2, a4, a2
 ; RV32IFD-NEXT:    and a1, a1, a2

 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    li a6, 1
 ; RV32IF-NEXT:  .LBB47_2: # %entry
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:    bltu a1, a3, .LBB47_4
 ; RV32IF-NEXT:  # %bb.3: # %entry
 ; RV32IF-NEXT:    li a2, 1
 ; RV32IF-NEXT:  .LBB47_4: # %entry
-; RV32IF-NEXT:    lw a5, 12(sp)
+; RV32IF-NEXT:    lw a4, 12(sp)
 ; RV32IF-NEXT:    lw a3, 8(sp)
-; RV32IF-NEXT:    slti a4, a0, 0
+; RV32IF-NEXT:    slti a5, a0, 0
 ; RV32IF-NEXT:    beqz a0, .LBB47_6
 ; RV32IF-NEXT:  # %bb.5: # %entry
 ; RV32IF-NEXT:    mv a2, a6
-; RV32IF-NEXT:    mv a6, a4
+; RV32IF-NEXT:    mv a6, a5
 ; RV32IF-NEXT:    j .LBB47_7
 ; RV32IF-NEXT:  .LBB47_6:
 ; RV32IF-NEXT:    seqz a6, a1
 ; RV32IF-NEXT:  .LBB47_7: # %entry
-; RV32IF-NEXT:    seqz a6, a6
-; RV32IF-NEXT:    addi a6, a6, -1
+; RV32IF-NEXT:    neg a6, a6
 ; RV32IF-NEXT:    and a3, a6, a3
 ; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    or a1, a1, a0
 ; RV32IF-NEXT:    seqz a1, a1
 ; RV32IF-NEXT:    addi a1, a1, -1
 ; RV32IF-NEXT:    and a3, a1, a3
-; RV32IF-NEXT:    and a5, a6, a5
-; RV32IF-NEXT:    and a1, a1, a5
-; RV32IF-NEXT:    neg a4, a4
+; RV32IF-NEXT:    and a4, a6, a4
+; RV32IF-NEXT:    and a1, a1, a4
+; RV32IF-NEXT:    neg a4, a5
 ; RV32IF-NEXT:    and a4, a4, a0
 ; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:    beqz a1, .LBB47_9
 ; RV32IF-NEXT:  # %bb.8: # %entry
 ; RV32IF-NEXT:    seqz a0, a1
 ; RV32IF-NEXT:    addi a0, a0, -1
 ; RV32IF-NEXT:    and a0, a0, a3
 ; RV32IF-NEXT:  .LBB47_9: # %entry
 ; RV32IF-NEXT:    beqz a4, .LBB47_11
 ; RV32IF-NEXT:  # %bb.10: # %entry
 ; RV32IF-NEXT:    sgtz a5, a4
 ; RV32IF-NEXT:    or a2, a2, a4
 ; RV32IF-NEXT:    bnez a2, .LBB47_12
 ; RV32IF-NEXT:    j .LBB47_13
 ; RV32IF-NEXT:  .LBB47_11:
 ; RV32IF-NEXT:    snez a5, a2
 ; RV32IF-NEXT:    or a2, a2, a4
 ; RV32IF-NEXT:    beqz a2, .LBB47_13
 ; RV32IF-NEXT:  .LBB47_12: # %entry
-; RV32IF-NEXT:    seqz a0, a5
-; RV32IF-NEXT:    addi a2, a0, -1
+; RV32IF-NEXT:    neg a2, a5
 ; RV32IF-NEXT:    and a0, a2, a3
 ; RV32IF-NEXT:    and a1, a2, a1
 ; RV32IF-NEXT:  .LBB47_13: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f64i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixdfti@plt
 ; RV64-NEXT:    mv a2, a1
 ; RV64-NEXT:    blez a1, .LBB47_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a2, 1
 ; RV64-NEXT:  .LBB47_2: # %entry
-; RV64-NEXT:    sgtz a3, a1
-; RV64-NEXT:    addi a3, a3, -1
+; RV64-NEXT:    slti a3, a1, 1
+; RV64-NEXT:    neg a3, a3
 ; RV64-NEXT:    and a0, a3, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    beqz a2, .LBB47_4
 ; RV64-NEXT:  # %bb.3: # %entry
 ; RV64-NEXT:    sgtz a1, a2

 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    li a6, 1
 ; RV32IFD-NEXT:  .LBB47_2: # %entry
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:    bltu a1, a3, .LBB47_4
 ; RV32IFD-NEXT:  # %bb.3: # %entry
 ; RV32IFD-NEXT:    li a2, 1
 ; RV32IFD-NEXT:  .LBB47_4: # %entry
-; RV32IFD-NEXT:    lw a5, 12(sp)
+; RV32IFD-NEXT:    lw a4, 12(sp)
 ; RV32IFD-NEXT:    lw a3, 8(sp)
-; RV32IFD-NEXT:    slti a4, a0, 0
+; RV32IFD-NEXT:    slti a5, a0, 0
 ; RV32IFD-NEXT:    beqz a0, .LBB47_6
 ; RV32IFD-NEXT:  # %bb.5: # %entry
 ; RV32IFD-NEXT:    mv a2, a6
-; RV32IFD-NEXT:    mv a6, a4
+; RV32IFD-NEXT:    mv a6, a5
 ; RV32IFD-NEXT:    j .LBB47_7
 ; RV32IFD-NEXT:  .LBB47_6:
 ; RV32IFD-NEXT:    seqz a6, a1
 ; RV32IFD-NEXT:  .LBB47_7: # %entry
-; RV32IFD-NEXT:    seqz a6, a6
-; RV32IFD-NEXT:    addi a6, a6, -1
+; RV32IFD-NEXT:    neg a6, a6
 ; RV32IFD-NEXT:    and a3, a6, a3
 ; RV32IFD-NEXT:    xori a1, a1, 1
 ; RV32IFD-NEXT:    or a1, a1, a0
 ; RV32IFD-NEXT:    seqz a1, a1
 ; RV32IFD-NEXT:    addi a1, a1, -1
 ; RV32IFD-NEXT:    and a3, a1, a3
-; RV32IFD-NEXT:    and a5, a6, a5
-; RV32IFD-NEXT:    and a1, a1, a5
-; RV32IFD-NEXT:    neg a4, a4
+; RV32IFD-NEXT:    and a4, a6, a4
+; RV32IFD-NEXT:    and a1, a1, a4
+; RV32IFD-NEXT:    neg a4, a5
 ; RV32IFD-NEXT:    and a4, a4, a0
 ; RV32IFD-NEXT:    mv a0, a3
 ; RV32IFD-NEXT:    beqz a1, .LBB47_9
 ; RV32IFD-NEXT:  # %bb.8: # %entry
 ; RV32IFD-NEXT:    seqz a0, a1
 ; RV32IFD-NEXT:    addi a0, a0, -1
 ; RV32IFD-NEXT:    and a0, a0, a3
 ; RV32IFD-NEXT:  .LBB47_9: # %entry
 ; RV32IFD-NEXT:    beqz a4, .LBB47_11
 ; RV32IFD-NEXT:  # %bb.10: # %entry
 ; RV32IFD-NEXT:    sgtz a5, a4
 ; RV32IFD-NEXT:    or a2, a2, a4
 ; RV32IFD-NEXT:    bnez a2, .LBB47_12
 ; RV32IFD-NEXT:    j .LBB47_13
 ; RV32IFD-NEXT:  .LBB47_11:
 ; RV32IFD-NEXT:    snez a5, a2
 ; RV32IFD-NEXT:    or a2, a2, a4
 ; RV32IFD-NEXT:    beqz a2, .LBB47_13
 ; RV32IFD-NEXT:  .LBB47_12: # %entry
-; RV32IFD-NEXT:    seqz a0, a5
-; RV32IFD-NEXT:    addi a2, a0, -1
+; RV32IFD-NEXT:    neg a2, a5
 ; RV32IFD-NEXT:    and a0, a2, a3
 ; RV32IFD-NEXT:    and a1, a2, a1
 ; RV32IFD-NEXT:  .LBB47_13: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptosi double %x to i128

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
 ; RV32-NEXT:    seqz a4, a0
 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    addi a5, a5, -1
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    neg a4, a4
 ; RV32-NEXT:    and a3, a4, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a2, a4, a2
 ; RV32-NEXT:    and a1, a1, a2

 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    li a6, 1
 ; RV32-NEXT:  .LBB50_2: # %entry
 ; RV32-NEXT:    mv a2, a1
 ; RV32-NEXT:    bltu a1, a3, .LBB50_4
 ; RV32-NEXT:  # %bb.3: # %entry
 ; RV32-NEXT:    li a2, 1
 ; RV32-NEXT:  .LBB50_4: # %entry
-; RV32-NEXT:    lw a5, 12(sp)
+; RV32-NEXT:    lw a4, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    slti a4, a0, 0
+; RV32-NEXT:    slti a5, a0, 0
 ; RV32-NEXT:    beqz a0, .LBB50_6
 ; RV32-NEXT:  # %bb.5: # %entry
 ; RV32-NEXT:    mv a2, a6
-; RV32-NEXT:    mv a6, a4
+; RV32-NEXT:    mv a6, a5
 ; RV32-NEXT:    j .LBB50_7
 ; RV32-NEXT:  .LBB50_6:
 ; RV32-NEXT:    seqz a6, a1
 ; RV32-NEXT:  .LBB50_7: # %entry
-; RV32-NEXT:    seqz a6, a6
-; RV32-NEXT:    addi a6, a6, -1
+; RV32-NEXT:    neg a6, a6
 ; RV32-NEXT:    and a3, a6, a3
 ; RV32-NEXT:    xori a1, a1, 1
 ; RV32-NEXT:    or a1, a1, a0
 ; RV32-NEXT:    seqz a1, a1
 ; RV32-NEXT:    addi a1, a1, -1
 ; RV32-NEXT:    and a3, a1, a3
-; RV32-NEXT:    and a5, a6, a5
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    neg a4, a4
+; RV32-NEXT:    and a4, a6, a4
+; RV32-NEXT:    and a1, a1, a4
+; RV32-NEXT:    neg a4, a5
 ; RV32-NEXT:    and a4, a4, a0
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    beqz a1, .LBB50_9
 ; RV32-NEXT:  # %bb.8: # %entry
 ; RV32-NEXT:    seqz a0, a1
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    and a0, a0, a3
 ; RV32-NEXT:  .LBB50_9: # %entry
 ; RV32-NEXT:    beqz a4, .LBB50_11
 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    sgtz a5, a4
 ; RV32-NEXT:    or a2, a2, a4
 ; RV32-NEXT:    bnez a2, .LBB50_12
 ; RV32-NEXT:    j .LBB50_13
 ; RV32-NEXT:  .LBB50_11:
 ; RV32-NEXT:    snez a5, a2
 ; RV32-NEXT:    or a2, a2, a4
 ; RV32-NEXT:    beqz a2, .LBB50_13
 ; RV32-NEXT:  .LBB50_12: # %entry
-; RV32-NEXT:    seqz a0, a5
-; RV32-NEXT:    addi a2, a0, -1
+; RV32-NEXT:    neg a2, a5
 ; RV32-NEXT:    and a0, a2, a3
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:  .LBB50_13: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixsfti@plt
 ; RV64-NEXT:    mv a2, a1
 ; RV64-NEXT:    blez a1, .LBB50_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a2, 1
 ; RV64-NEXT:  .LBB50_2: # %entry
-; RV64-NEXT:    sgtz a3, a1
-; RV64-NEXT:    addi a3, a3, -1
+; RV64-NEXT:    slti a3, a1, 1
+; RV64-NEXT:    neg a3, a3
 ; RV64-NEXT:    and a0, a3, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    beqz a2, .LBB50_4
 ; RV64-NEXT:  # %bb.3: # %entry
 ; RV64-NEXT:    sgtz a1, a2

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
 ; RV32-NEXT:    seqz a4, a0
 ; RV32-NEXT:    snez a5, a1
 ; RV32-NEXT:    addi a5, a5, -1
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    neg a4, a4
 ; RV32-NEXT:    and a3, a4, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a2, a4, a2
 ; RV32-NEXT:    and a1, a1, a2

 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    li a6, 1
 ; RV32-NEXT:  .LBB53_2: # %entry
 ; RV32-NEXT:    mv a2, a1
 ; RV32-NEXT:    bltu a1, a3, .LBB53_4
 ; RV32-NEXT:  # %bb.3: # %entry
 ; RV32-NEXT:    li a2, 1
 ; RV32-NEXT:  .LBB53_4: # %entry
-; RV32-NEXT:    lw a5, 12(sp)
+; RV32-NEXT:    lw a4, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    slti a4, a0, 0
+; RV32-NEXT:    slti a5, a0, 0
 ; RV32-NEXT:    beqz a0, .LBB53_6
 ; RV32-NEXT:  # %bb.5: # %entry
 ; RV32-NEXT:    mv a2, a6
-; RV32-NEXT:    mv a6, a4
+; RV32-NEXT:    mv a6, a5
 ; RV32-NEXT:    j .LBB53_7
 ; RV32-NEXT:  .LBB53_6:
 ; RV32-NEXT:    seqz a6, a1
 ; RV32-NEXT:  .LBB53_7: # %entry
-; RV32-NEXT:    seqz a6, a6
-; RV32-NEXT:    addi a6, a6, -1
+; RV32-NEXT:    neg a6, a6
 ; RV32-NEXT:    and a3, a6, a3
 ; RV32-NEXT:    xori a1, a1, 1
 ; RV32-NEXT:    or a1, a1, a0
 ; RV32-NEXT:    seqz a1, a1
 ; RV32-NEXT:    addi a1, a1, -1
 ; RV32-NEXT:    and a3, a1, a3
-; RV32-NEXT:    and a5, a6, a5
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    neg a4, a4
+; RV32-NEXT:    and a4, a6, a4
+; RV32-NEXT:    and a1, a1, a4
+; RV32-NEXT:    neg a4, a5
 ; RV32-NEXT:    and a4, a4, a0
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    beqz a1, .LBB53_9
 ; RV32-NEXT:  # %bb.8: # %entry
 ; RV32-NEXT:    seqz a0, a1
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    and a0, a0, a3
 ; RV32-NEXT:  .LBB53_9: # %entry
 ; RV32-NEXT:    beqz a4, .LBB53_11
 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    sgtz a5, a4
 ; RV32-NEXT:    or a2, a2, a4
 ; RV32-NEXT:    bnez a2, .LBB53_12
 ; RV32-NEXT:    j .LBB53_13
 ; RV32-NEXT:  .LBB53_11:
 ; RV32-NEXT:    snez a5, a2
 ; RV32-NEXT:    or a2, a2, a4
 ; RV32-NEXT:    beqz a2, .LBB53_13
 ; RV32-NEXT:  .LBB53_12: # %entry
-; RV32-NEXT:    seqz a0, a5
-; RV32-NEXT:    addi a2, a0, -1
+; RV32-NEXT:    neg a2, a5
 ; RV32-NEXT:    and a0, a2, a3
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:  .LBB53_13: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0
 ; RV64-NEXT:    call __extendhfsf2@plt
 ; RV64-NEXT:    call __fixsfti@plt
 ; RV64-NEXT:    mv a2, a1
 ; RV64-NEXT:    blez a1, .LBB53_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a2, 1
 ; RV64-NEXT:  .LBB53_2: # %entry
-; RV64-NEXT:    sgtz a3, a1
-; RV64-NEXT:    addi a3, a3, -1
+; RV64-NEXT:    slti a3, a1, 1
+; RV64-NEXT:    neg a3, a3
 ; RV64-NEXT:    and a0, a3, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
 ; RV64-NEXT:    beqz a2, .LBB53_4
 ; RV64-NEXT:  # %bb.3: # %entry
 ; RV64-NEXT:    sgtz a1, a2

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

entry:
   %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
   %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
   ret <2 x i32> %conv6
 }
 
 define <2 x i32> @ustest_f64i32(<2 x double> %x) {
 ; CHECK-NOV-LABEL: ustest_f64i32:
 ; CHECK-NOV:       # %bb.0: # %entry
-; CHECK-NOV-NEXT:    fcvt.l.d a1, fa1, rtz
-; CHECK-NOV-NEXT:    li a0, -1
-; CHECK-NOV-NEXT:    srli a2, a0, 32
 ; CHECK-NOV-NEXT:    fcvt.l.d a0, fa0, rtz
-; CHECK-NOV-NEXT:    blt a1, a2, .LBB2_2
+; CHECK-NOV-NEXT:    li a1, -1
+; CHECK-NOV-NEXT:    srli a2, a1, 32
+; CHECK-NOV-NEXT:    fcvt.l.d a1, fa1, rtz
+; CHECK-NOV-NEXT:    blt a0, a2, .LBB2_2
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
-; CHECK-NOV-NEXT:    mv a1, a2
+; CHECK-NOV-NEXT:    mv a0, a2
 ; CHECK-NOV-NEXT:  .LBB2_2: # %entry
-; CHECK-NOV-NEXT:    blt a0, a2, .LBB2_4
+; CHECK-NOV-NEXT:    blt a1, a2, .LBB2_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    mv a0, a2
+; CHECK-NOV-NEXT:    mv a1, a2
 ; CHECK-NOV-NEXT:  .LBB2_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a2, a0
-; CHECK-NOV-NEXT:    neg a2, a2
-; CHECK-NOV-NEXT:    and a0, a2, a0
 ; CHECK-NOV-NEXT:    sgtz a2, a1
+; CHECK-NOV-NEXT:    sgtz a3, a0
+; CHECK-NOV-NEXT:    neg a3, a3
+; CHECK-NOV-NEXT:    and a0, a3, a0
 ; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a1, a2, a1
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: ustest_f64i32:
 ; CHECK-V:       # %bb.0: # %entry
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vfcvt.rtz.x.f.v v8, v8
entry:
   %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
   %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
   ret <4 x i32> %conv6
 }
 
 define <4 x i32> @ustest_f32i32(<4 x float> %x) {
 ; CHECK-NOV-LABEL: ustest_f32i32:
 ; CHECK-NOV:       # %bb.0: # %entry
-; CHECK-NOV-NEXT:    fcvt.l.s a1, fa3, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a1, fa0, rtz
 ; CHECK-NOV-NEXT:    li a2, -1
 ; CHECK-NOV-NEXT:    srli a4, a2, 32
-; CHECK-NOV-NEXT:    fcvt.l.s a2, fa2, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a2, fa1, rtz
 ; CHECK-NOV-NEXT:    bge a1, a4, .LBB5_6
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
-; CHECK-NOV-NEXT:    fcvt.l.s a3, fa1, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a3, fa2, rtz
 ; CHECK-NOV-NEXT:    bge a2, a4, .LBB5_7
 ; CHECK-NOV-NEXT:  .LBB5_2: # %entry
-; CHECK-NOV-NEXT:    fcvt.l.s a5, fa0, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a5, fa3, rtz
 ; CHECK-NOV-NEXT:    bge a3, a4, .LBB5_8
 ; CHECK-NOV-NEXT:  .LBB5_3: # %entry
 ; CHECK-NOV-NEXT:    blt a5, a4, .LBB5_5
 ; CHECK-NOV-NEXT:  .LBB5_4: # %entry
 ; CHECK-NOV-NEXT:    mv a5, a4
 ; CHECK-NOV-NEXT:  .LBB5_5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a4, a5
+; CHECK-NOV-NEXT:    sgtz a6, a3
+; CHECK-NOV-NEXT:    sgtz a7, a2
+; CHECK-NOV-NEXT:    sgtz t0, a1
+; CHECK-NOV-NEXT:    neg t0, t0
+; CHECK-NOV-NEXT:    and a1, t0, a1
+; CHECK-NOV-NEXT:    neg a7, a7
+; CHECK-NOV-NEXT:    and a2, a7, a2
+; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    and a3, a6, a3
 ; CHECK-NOV-NEXT:    neg a4, a4
 ; CHECK-NOV-NEXT:    and a4, a4, a5
-; CHECK-NOV-NEXT:    sgtz a5, a3
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a3, a5, a3
-; CHECK-NOV-NEXT:    sgtz a5, a2
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a2, a5, a2
-; CHECK-NOV-NEXT:    sgtz a5, a1
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a1, a5, a1
-; CHECK-NOV-NEXT:    sw a1, 12(a0)
-; CHECK-NOV-NEXT:    sw a2, 8(a0)
-; CHECK-NOV-NEXT:    sw a3, 4(a0)
-; CHECK-NOV-NEXT:    sw a4, 0(a0)
+; CHECK-NOV-NEXT:    sw a4, 12(a0)
+; CHECK-NOV-NEXT:    sw a3, 8(a0)
+; CHECK-NOV-NEXT:    sw a2, 4(a0)
+; CHECK-NOV-NEXT:    sw a1, 0(a0)
 ; CHECK-NOV-NEXT:    ret
 ; CHECK-NOV-NEXT:  .LBB5_6: # %entry
 ; CHECK-NOV-NEXT:    mv a1, a4
-; CHECK-NOV-NEXT:    fcvt.l.s a3, fa1, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a3, fa2, rtz
 ; CHECK-NOV-NEXT:    blt a2, a4, .LBB5_2
 ; CHECK-NOV-NEXT:  .LBB5_7: # %entry
 ; CHECK-NOV-NEXT:    mv a2, a4
-; CHECK-NOV-NEXT:    fcvt.l.s a5, fa0, rtz
+; CHECK-NOV-NEXT:    fcvt.l.s a5, fa3, rtz
 ; CHECK-NOV-NEXT:    blt a3, a4, .LBB5_3
 ; CHECK-NOV-NEXT:  .LBB5_8: # %entry
 ; CHECK-NOV-NEXT:    mv a3, a4
 ; CHECK-NOV-NEXT:    bge a5, a4, .LBB5_4
 ; CHECK-NOV-NEXT:    j .LBB5_5
 ;
 ; CHECK-V-LABEL: ustest_f32i32:
 ; CHECK-V:       # %bb.0: # %entry

 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset s2, -32
 ; CHECK-NOV-NEXT:    .cfi_offset s3, -40
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -48
 ; CHECK-NOV-NEXT:    .cfi_offset fs1, -56
 ; CHECK-NOV-NEXT:    .cfi_offset fs2, -64
-; CHECK-NOV-NEXT:    lhu s1, 24(a1)
-; CHECK-NOV-NEXT:    lhu s2, 0(a1)
-; CHECK-NOV-NEXT:    lhu s3, 8(a1)
-; CHECK-NOV-NEXT:    lhu a1, 16(a1)
+; CHECK-NOV-NEXT:    lhu s1, 0(a1)
+; CHECK-NOV-NEXT:    lhu s2, 24(a1)
+; CHECK-NOV-NEXT:    lhu s3, 16(a1)
+; CHECK-NOV-NEXT:    lhu a1, 8(a1)
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv a0, a1
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    fmv.s fs2, fa0
 ; CHECK-NOV-NEXT:    mv a0, s3
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    fmv.s fs1, fa0
 ; CHECK-NOV-NEXT:    mv a0, s2

 ; CHECK-NOV-NEXT:    fcvt.l.s a3, fs0, rtz
 ; CHECK-NOV-NEXT:    bge a1, a2, .LBB8_8
 ; CHECK-NOV-NEXT:  .LBB8_3: # %entry
 ; CHECK-NOV-NEXT:    blt a3, a2, .LBB8_5
 ; CHECK-NOV-NEXT:  .LBB8_4: # %entry
 ; CHECK-NOV-NEXT:    mv a3, a2
 ; CHECK-NOV-NEXT:  .LBB8_5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a2, a3
+; CHECK-NOV-NEXT:    sgtz a4, a1
+; CHECK-NOV-NEXT:    sgtz a5, s2
+; CHECK-NOV-NEXT:    sgtz a6, a0
+; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    and a0, a6, a0
+; CHECK-NOV-NEXT:    neg a5, a5
+; CHECK-NOV-NEXT:    and a5, a5, s2
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    and a1, a4, a1
 ; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a2, a2, a3
-; CHECK-NOV-NEXT:    sgtz a3, a1
-; CHECK-NOV-NEXT:    neg a3, a3
-; CHECK-NOV-NEXT:    and a1, a3, a1
-; CHECK-NOV-NEXT:    sgtz a3, s2
-; CHECK-NOV-NEXT:    neg a3, a3
-; CHECK-NOV-NEXT:    and a3, a3, s2
-; CHECK-NOV-NEXT:    sgtz a4, a0
-; CHECK-NOV-NEXT:    neg a4, a4
-; CHECK-NOV-NEXT:    and a0, a4, a0
-; CHECK-NOV-NEXT:    sw a0, 12(s0)
-; CHECK-NOV-NEXT:    sw a3, 8(s0)
-; CHECK-NOV-NEXT:    sw a1, 4(s0)
-; CHECK-NOV-NEXT:    sw a2, 0(s0)
+; CHECK-NOV-NEXT:    sw a2, 12(s0)
+; CHECK-NOV-NEXT:    sw a1, 8(s0)
+; CHECK-NOV-NEXT:    sw a5, 4(s0)
+; CHECK-NOV-NEXT:    sw a0, 0(s0)
 ; CHECK-NOV-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s2, 32(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s3, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs2, 0(sp) # 8-byte Folded Reload
entry:
   %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
   %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>
   ret <2 x i16> %conv6
 }
 
 define <2 x i16> @ustest_f64i16(<2 x double> %x) {
 ; CHECK-NOV-LABEL: ustest_f64i16:
 ; CHECK-NOV:       # %bb.0: # %entry
-; CHECK-NOV-NEXT:    fcvt.w.d a1, fa1, rtz
-; CHECK-NOV-NEXT:    lui a0, 16
-; CHECK-NOV-NEXT:    addiw a2, a0, -1
 ; CHECK-NOV-NEXT:    fcvt.w.d a0, fa0, rtz
-; CHECK-NOV-NEXT:    blt a1, a2, .LBB11_2
+; CHECK-NOV-NEXT:    lui a1, 16
+; CHECK-NOV-NEXT:    addiw a2, a1, -1
+; CHECK-NOV-NEXT:    fcvt.w.d a1, fa1, rtz
+; CHECK-NOV-NEXT:    blt a0, a2, .LBB11_2
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
-; CHECK-NOV-NEXT:    mv a1, a2
+; CHECK-NOV-NEXT:    mv a0, a2
 ; CHECK-NOV-NEXT:  .LBB11_2: # %entry
-; CHECK-NOV-NEXT:    blt a0, a2, .LBB11_4
+; CHECK-NOV-NEXT:    blt a1, a2, .LBB11_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    mv a0, a2
+; CHECK-NOV-NEXT:    mv a1, a2
 ; CHECK-NOV-NEXT:  .LBB11_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a2, a0
-; CHECK-NOV-NEXT:    neg a2, a2
-; CHECK-NOV-NEXT:    and a0, a2, a0
 ; CHECK-NOV-NEXT:    sgtz a2, a1
+; CHECK-NOV-NEXT:    sgtz a3, a0
+; CHECK-NOV-NEXT:    neg a3, a3
+; CHECK-NOV-NEXT:    and a0, a3, a0
 ; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a1, a2, a1
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: ustest_f64i16:
 ; CHECK-V:       # %bb.0: # %entry
 ; CHECK-V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-V-NEXT:    vfncvt.rtz.x.f.w v9, v8
entry:
   %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
   %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
   ret <4 x i16> %conv6
 }
 
 define <4 x i16> @ustest_f32i16(<4 x float> %x) {
 ; CHECK-NOV-LABEL: ustest_f32i16:
 ; CHECK-NOV:       # %bb.0: # %entry
-; CHECK-NOV-NEXT:    fcvt.w.s a1, fa3, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a1, fa0, rtz
 ; CHECK-NOV-NEXT:    lui a2, 16
 ; CHECK-NOV-NEXT:    addiw a4, a2, -1
-; CHECK-NOV-NEXT:    fcvt.w.s a2, fa2, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a2, fa1, rtz
 ; CHECK-NOV-NEXT:    bge a1, a4, .LBB14_6
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
-; CHECK-NOV-NEXT:    fcvt.w.s a3, fa1, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a3, fa2, rtz
 ; CHECK-NOV-NEXT:    bge a2, a4, .LBB14_7
 ; CHECK-NOV-NEXT:  .LBB14_2: # %entry
-; CHECK-NOV-NEXT:    fcvt.w.s a5, fa0, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a5, fa3, rtz
 ; CHECK-NOV-NEXT:    bge a3, a4, .LBB14_8
 ; CHECK-NOV-NEXT:  .LBB14_3: # %entry
 ; CHECK-NOV-NEXT:    blt a5, a4, .LBB14_5
 ; CHECK-NOV-NEXT:  .LBB14_4: # %entry
 ; CHECK-NOV-NEXT:    mv a5, a4
 ; CHECK-NOV-NEXT:  .LBB14_5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a4, a5
+; CHECK-NOV-NEXT:    sgtz a6, a3
+; CHECK-NOV-NEXT:    sgtz a7, a2
+; CHECK-NOV-NEXT:    sgtz t0, a1
+; CHECK-NOV-NEXT:    neg t0, t0
+; CHECK-NOV-NEXT:    and a1, t0, a1
+; CHECK-NOV-NEXT:    neg a7, a7
+; CHECK-NOV-NEXT:    and a2, a7, a2
+; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    and a3, a6, a3
 ; CHECK-NOV-NEXT:    neg a4, a4
 ; CHECK-NOV-NEXT:    and a4, a4, a5
-; CHECK-NOV-NEXT:    sgtz a5, a3
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a3, a5, a3
-; CHECK-NOV-NEXT:    sgtz a5, a2
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a2, a5, a2
-; CHECK-NOV-NEXT:    sgtz a5, a1
-; CHECK-NOV-NEXT:    neg a5, a5
-; CHECK-NOV-NEXT:    and a1, a5, a1
-; CHECK-NOV-NEXT:    sh a1, 6(a0)
-; CHECK-NOV-NEXT:    sh a2, 4(a0)
-; CHECK-NOV-NEXT:    sh a3, 2(a0)
-; CHECK-NOV-NEXT:    sh a4, 0(a0)
+; CHECK-NOV-NEXT:    sh a4, 6(a0)
+; CHECK-NOV-NEXT:    sh a3, 4(a0)
+; CHECK-NOV-NEXT:    sh a2, 2(a0)
+; CHECK-NOV-NEXT:    sh a1, 0(a0)
 ; CHECK-NOV-NEXT:    ret
 ; CHECK-NOV-NEXT:  .LBB14_6: # %entry
 ; CHECK-NOV-NEXT:    mv a1, a4
-; CHECK-NOV-NEXT:    fcvt.w.s a3, fa1, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a3, fa2, rtz
 ; CHECK-NOV-NEXT:    blt a2, a4, .LBB14_2
 ; CHECK-NOV-NEXT:  .LBB14_7: # %entry
 ; CHECK-NOV-NEXT:    mv a2, a4
-; CHECK-NOV-NEXT:    fcvt.w.s a5, fa0, rtz
+; CHECK-NOV-NEXT:    fcvt.w.s a5, fa3, rtz
 ; CHECK-NOV-NEXT:    blt a3, a4, .LBB14_3
 ; CHECK-NOV-NEXT:  .LBB14_8: # %entry
 ; CHECK-NOV-NEXT:    mv a3, a4
 ; CHECK-NOV-NEXT:    bge a5, a4, .LBB14_4
 ; CHECK-NOV-NEXT:    j .LBB14_5
 ;
 ; CHECK-V-LABEL: ustest_f32i16:
 ; CHECK-V:       # %bb.0: # %entry

 ; CHECK-NOV-NEXT:    .cfi_offset s7, -72
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -80
 ; CHECK-NOV-NEXT:    .cfi_offset fs1, -88
 ; CHECK-NOV-NEXT:    .cfi_offset fs2, -96
 ; CHECK-NOV-NEXT:    .cfi_offset fs3, -104
 ; CHECK-NOV-NEXT:    .cfi_offset fs4, -112
 ; CHECK-NOV-NEXT:    .cfi_offset fs5, -120
 ; CHECK-NOV-NEXT:    .cfi_offset fs6, -128
-; CHECK-NOV-NEXT:    lhu s1, 56(a1)
-; CHECK-NOV-NEXT:    lhu s2, 0(a1)
-; CHECK-NOV-NEXT:    lhu s3, 8(a1)
-; CHECK-NOV-NEXT:    lhu s4, 16(a1)
-; CHECK-NOV-NEXT:    lhu s5, 24(a1)
-; CHECK-NOV-NEXT:    lhu s6, 32(a1)
-; CHECK-NOV-NEXT:    lhu s7, 40(a1)
-; CHECK-NOV-NEXT:    lhu a1, 48(a1)
+; CHECK-NOV-NEXT:    lhu s1, 0(a1)
+; CHECK-NOV-NEXT:    lhu s2, 56(a1)
+; CHECK-NOV-NEXT:    lhu s3, 48(a1)
+; CHECK-NOV-NEXT:    lhu s4, 40(a1)
+; CHECK-NOV-NEXT:    lhu s5, 32(a1)
+; CHECK-NOV-NEXT:    lhu s6, 24(a1)
+; CHECK-NOV-NEXT:    lhu s7, 16(a1)
+; CHECK-NOV-NEXT:    lhu a1, 8(a1)
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv a0, a1
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    fmv.s fs6, fa0
 ; CHECK-NOV-NEXT:    mv a0, s7
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    fmv.s fs5, fa0
 ; CHECK-NOV-NEXT:    mv a0, s6

 ; CHECK-NOV-NEXT:    fcvt.l.s a7, fs0, rtz
 ; CHECK-NOV-NEXT:    bge a6, a3, .LBB17_16
 ; CHECK-NOV-NEXT:  .LBB17_7: # %entry
 ; CHECK-NOV-NEXT:    blt a7, a3, .LBB17_9
 ; CHECK-NOV-NEXT:  .LBB17_8: # %entry
 ; CHECK-NOV-NEXT:    mv a7, a3
 ; CHECK-NOV-NEXT:  .LBB17_9: # %entry
 ; CHECK-NOV-NEXT:    sgtz a3, a7
+; CHECK-NOV-NEXT:    sgtz t0, a6
+; CHECK-NOV-NEXT:    sgtz t1, a5
+; CHECK-NOV-NEXT:    sgtz t2, a4
+; CHECK-NOV-NEXT:    sgtz t3, a2
+; CHECK-NOV-NEXT:    sgtz t4, a1
+; CHECK-NOV-NEXT:    sgtz t5, s2
+; CHECK-NOV-NEXT:    sgtz t6, a0
+; CHECK-NOV-NEXT:    neg t6, t6
+; CHECK-NOV-NEXT:    and a0, t6, a0
+; CHECK-NOV-NEXT:    neg t5, t5
+; CHECK-NOV-NEXT:    and t5, t5, s2
+; CHECK-NOV-NEXT:    neg t4, t4
+; CHECK-NOV-NEXT:    and a1, t4, a1
+; CHECK-NOV-NEXT:    neg t3, t3
+; CHECK-NOV-NEXT:    and a2, t3, a2
+; CHECK-NOV-NEXT:    neg t2, t2
+; CHECK-NOV-NEXT:    and a4, t2, a4
+; CHECK-NOV-NEXT:    neg t1, t1
+; CHECK-NOV-NEXT:    and a5, t1, a5
+; CHECK-NOV-NEXT:    neg t0, t0
+; CHECK-NOV-NEXT:    and a6, t0, a6
 ; CHECK-NOV-NEXT:    neg a3, a3
 ; CHECK-NOV-NEXT:    and a3, a3, a7
-; CHECK-NOV-NEXT:    sgtz a7, a6
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a6, a7, a6
-; CHECK-NOV-NEXT:    sgtz a7, a5
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a5, a7, a5
-; CHECK-NOV-NEXT:    sgtz a7, a4
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a4, a7, a4
-; CHECK-NOV-NEXT:    sgtz a7, a2
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a2, a7, a2
-; CHECK-NOV-NEXT:    sgtz a7, a1
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a1, a7, a1
-; CHECK-NOV-NEXT:    sgtz a7, s2
-; CHECK-NOV-NEXT:    neg a7, a7
-; CHECK-NOV-NEXT:    and a7, a7, s2
-; CHECK-NOV-NEXT:    sgtz t0, a0
-; CHECK-NOV-NEXT:    neg t0, t0
-; CHECK-NOV-NEXT:    and a0, t0, a0
-; CHECK-NOV-NEXT:    sh a0, 14(s0)
-; CHECK-NOV-NEXT:    sh a7, 12(s0)
-; CHECK-NOV-NEXT:    sh a1, 10(s0)
-; CHECK-NOV-NEXT:    sh a2, 8(s0)
-; CHECK-NOV-NEXT:    sh a4, 6(s0)
-; CHECK-NOV-NEXT:    sh a5, 4(s0)
-; CHECK-NOV-NEXT:    sh a6, 2(s0)
-; CHECK-NOV-NEXT:    sh a3, 0(s0)
+; CHECK-NOV-NEXT:    sh a3, 14(s0)
+; CHECK-NOV-NEXT:    sh a6, 12(s0)
+; CHECK-NOV-NEXT:    sh a5, 10(s0)
+; CHECK-NOV-NEXT:    sh a4, 8(s0)
+; CHECK-NOV-NEXT:    sh a2, 6(s0)
+; CHECK-NOV-NEXT:    sh a1, 4(s0)
+; CHECK-NOV-NEXT:    sh t5, 2(s0)
+; CHECK-NOV-NEXT:    sh a0, 0(s0)
 ; CHECK-NOV-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 104(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s2, 96(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s3, 88(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s4, 80(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s5, 72(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s6, 64(sp) # 8-byte Folded Reload

 ; CHECK-NOV-NEXT:    li a0, -1
 ; CHECK-NOV-NEXT:    srli a3, a0, 1
 ; CHECK-NOV-NEXT:    beqz a1, .LBB18_3
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    slti a4, a1, 0
 ; CHECK-NOV-NEXT:    bnez s1, .LBB18_4
 ; CHECK-NOV-NEXT:  .LBB18_2:
 ; CHECK-NOV-NEXT:    sltu a5, s0, a3
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    beqz a5, .LBB18_5
 ; CHECK-NOV-NEXT:    j .LBB18_6
 ; CHECK-NOV-NEXT:  .LBB18_3:
 ; CHECK-NOV-NEXT:    sltu a4, a2, a3
 ; CHECK-NOV-NEXT:    beqz s1, .LBB18_2
 ; CHECK-NOV-NEXT:  .LBB18_4: # %entry
 ; CHECK-NOV-NEXT:    slti a5, s1, 0
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    bnez a5, .LBB18_6
 ; CHECK-NOV-NEXT:  .LBB18_5: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:  .LBB18_6: # %entry
-; CHECK-NOV-NEXT:    addi a6, a6, -1
-; CHECK-NOV-NEXT:    seqz a5, a4
-; CHECK-NOV-NEXT:    addi a5, a5, -1
+; CHECK-NOV-NEXT:    neg a6, a5
+; CHECK-NOV-NEXT:    neg a5, a4
 ; CHECK-NOV-NEXT:    and a5, a5, a1
 ; CHECK-NOV-NEXT:    bnez a4, .LBB18_8
 ; CHECK-NOV-NEXT:  # %bb.7: # %entry
 ; CHECK-NOV-NEXT:    mv a2, a3
 ; CHECK-NOV-NEXT:  .LBB18_8: # %entry
 ; CHECK-NOV-NEXT:    and a4, a6, s1
 ; CHECK-NOV-NEXT:    slli a1, a0, 63
 ; CHECK-NOV-NEXT:    beq a5, a0, .LBB18_11

 ; CHECK-V-NEXT:    li a2, -1
 ; CHECK-V-NEXT:    srli a3, a2, 1
 ; CHECK-V-NEXT:    beqz s1, .LBB18_3
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    slti a4, s1, 0
 ; CHECK-V-NEXT:    bnez a1, .LBB18_4
 ; CHECK-V-NEXT:  .LBB18_2:
 ; CHECK-V-NEXT:    sltu a5, a0, a3
-; CHECK-V-NEXT:    j .LBB18_5
+; CHECK-V-NEXT:    neg a6, a4
+; CHECK-V-NEXT:    beqz a4, .LBB18_5
+; CHECK-V-NEXT:    j .LBB18_6
 ; CHECK-V-NEXT:  .LBB18_3:
 ; CHECK-V-NEXT:    sltu a4, s0, a3
 ; CHECK-V-NEXT:    beqz a1, .LBB18_2
 ; CHECK-V-NEXT:  .LBB18_4: # %entry
 ; CHECK-V-NEXT:    slti a5, a1, 0
+; CHECK-V-NEXT:    neg a6, a4
+; CHECK-V-NEXT:    bnez a4, .LBB18_6
 ; CHECK-V-NEXT:  .LBB18_5: # %entry
-; CHECK-V-NEXT:    seqz a6, a4
-; CHECK-V-NEXT:    addi a6, a6, -1
-; CHECK-V-NEXT:    bnez a4, .LBB18_7
-; CHECK-V-NEXT:  # %bb.6: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
-; CHECK-V-NEXT:  .LBB18_7: # %entry
+; CHECK-V-NEXT:  .LBB18_6: # %entry
 ; CHECK-V-NEXT:    and a6, a6, s1
-; CHECK-V-NEXT:    seqz a4, a5
-; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    bnez a5, .LBB18_9
-; CHECK-V-NEXT:  # %bb.8: # %entry
+; CHECK-V-NEXT:    neg a4, a5
+; CHECK-V-NEXT:    bnez a5, .LBB18_8
+; CHECK-V-NEXT:  # %bb.7: # %entry
 ; CHECK-V-NEXT:    mv a0, a3
-; CHECK-V-NEXT:  .LBB18_9: # %entry
+; CHECK-V-NEXT:  .LBB18_8: # %entry
 ; CHECK-V-NEXT:    and a4, a4, a1
 ; CHECK-V-NEXT:    slli a1, a2, 63
-; CHECK-V-NEXT:    beq a6, a2, .LBB18_12
-; CHECK-V-NEXT:  # %bb.10: # %entry
+; CHECK-V-NEXT:    beq a6, a2, .LBB18_11
+; CHECK-V-NEXT:  # %bb.9: # %entry
 ; CHECK-V-NEXT:    slti a3, a6, 0
 ; CHECK-V-NEXT:    xori a3, a3, 1
-; CHECK-V-NEXT:    bne a4, a2, .LBB18_13
-; CHECK-V-NEXT:  .LBB18_11:
+; CHECK-V-NEXT:    bne a4, a2, .LBB18_12
+; CHECK-V-NEXT:  .LBB18_10:
 ; CHECK-V-NEXT:    sltu a2, a1, a0
-; CHECK-V-NEXT:    beqz a3, .LBB18_14
-; CHECK-V-NEXT:    j .LBB18_15
-; CHECK-V-NEXT:  .LBB18_12:
+; CHECK-V-NEXT:    beqz a3, .LBB18_13
+; CHECK-V-NEXT:    j .LBB18_14
+; CHECK-V-NEXT:  .LBB18_11:
 ; CHECK-V-NEXT:    sltu a3, a1, s0
-; CHECK-V-NEXT:    beq a4, a2, .LBB18_11
-; CHECK-V-NEXT:  .LBB18_13: # %entry
+; CHECK-V-NEXT:    beq a4, a2, .LBB18_10
+; CHECK-V-NEXT:  .LBB18_12: # %entry
 ; CHECK-V-NEXT:    slti a2, a4, 0
 ; CHECK-V-NEXT:    xori a2, a2, 1
-; CHECK-V-NEXT:    bnez a3, .LBB18_15
-; CHECK-V-NEXT:  .LBB18_14: # %entry
+; CHECK-V-NEXT:    bnez a3, .LBB18_14
+; CHECK-V-NEXT:  .LBB18_13: # %entry
 ; CHECK-V-NEXT:    mv s0, a1
-; CHECK-V-NEXT:  .LBB18_15: # %entry
-; CHECK-V-NEXT:    bnez a2, .LBB18_17
-; CHECK-V-NEXT:  # %bb.16: # %entry
+; CHECK-V-NEXT:  .LBB18_14: # %entry
+; CHECK-V-NEXT:    bnez a2, .LBB18_16
+; CHECK-V-NEXT:  # %bb.15: # %entry
 ; CHECK-V-NEXT:    mv a0, a1
-; CHECK-V-NEXT:  .LBB18_17: # %entry
+; CHECK-V-NEXT:  .LBB18_16: # %entry
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd s0, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -32
-; CHECK-NOV-NEXT:    fmv.d fs0, fa0
-; CHECK-NOV-NEXT:    fmv.d fa0, fa1
+; CHECK-NOV-NEXT:    fmv.d fs0, fa1
 ; CHECK-NOV-NEXT:    call __fixunsdfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.d fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixunsdfti@plt
 ; CHECK-NOV-NEXT:    snez a1, a1
+; CHECK-NOV-NEXT:    snez a2, s1
+; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a0, a1, a0
-; CHECK-NOV-NEXT:    snez a1, s1
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
+; CHECK-NOV-NEXT:    and a1, a1, a0
+; CHECK-NOV-NEXT:    mv a0, a2
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: utest_f64i64:

 ; CHECK-V-NEXT:    mv s0, a0
 ; CHECK-V-NEXT:    mv s1, a1
 ; CHECK-V-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
 ; CHECK-V-NEXT:    addi a0, sp, 48
 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixunsdfti@plt
 ; CHECK-V-NEXT:    snez a2, s1
+; CHECK-V-NEXT:    snez a1, a1
 ; CHECK-V-NEXT:    addi a2, a2, -1
 ; CHECK-V-NEXT:    and a2, a2, s0
-; CHECK-V-NEXT:    snez a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -32
-; CHECK-NOV-NEXT:    fmv.d fs0, fa0
-; CHECK-NOV-NEXT:    fmv.d fa0, fa1
+; CHECK-NOV-NEXT:    fmv.d fs0, fa1
 ; CHECK-NOV-NEXT:    call __fixdfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.d fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixdfti@plt
-; CHECK-NOV-NEXT:    mv a2, a1
-; CHECK-NOV-NEXT:    blez a1, .LBB20_2
+; CHECK-NOV-NEXT:    mv a2, s1
+; CHECK-NOV-NEXT:    blez s1, .LBB20_2
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB20_2: # %entry
-; CHECK-NOV-NEXT:    mv a3, s1
-; CHECK-NOV-NEXT:    blez s1, .LBB20_4
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    slti a4, s1, 1
+; CHECK-NOV-NEXT:    blez a1, .LBB20_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a3, 1
+; CHECK-NOV-NEXT:    li a1, 1
 ; CHECK-NOV-NEXT:  .LBB20_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a1, a1
-; CHECK-NOV-NEXT:    addi a4, a1, -1
-; CHECK-NOV-NEXT:    sgtz a1, s1
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
-; CHECK-NOV-NEXT:    beqz a3, .LBB20_7
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    neg a3, a3
+; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    beqz a1, .LBB20_7
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a3
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    sgtz a1, a1
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    bnez a2, .LBB20_8
 ; CHECK-NOV-NEXT:  .LBB20_6:
 ; CHECK-NOV-NEXT:    snez a2, a0
 ; CHECK-NOV-NEXT:    j .LBB20_9
 ; CHECK-NOV-NEXT:  .LBB20_7:
-; CHECK-NOV-NEXT:    snez a3, a1
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    snez a1, a3
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    beqz a2, .LBB20_6
 ; CHECK-NOV-NEXT:  .LBB20_8: # %entry
 ; CHECK-NOV-NEXT:    sgtz a2, a2
 ; CHECK-NOV-NEXT:  .LBB20_9: # %entry
-; CHECK-NOV-NEXT:    seqz a2, a2
-; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a0, a2, a0
-; CHECK-NOV-NEXT:    seqz a2, a3
-; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a1, a2, a1
+; CHECK-NOV-NEXT:    neg a1, a1
+; CHECK-NOV-NEXT:    and a1, a1, a3
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: ustest_f64i64:

 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixdfti@plt
 ; CHECK-V-NEXT:    mv a2, a1
 ; CHECK-V-NEXT:    blez a1, .LBB20_2
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB20_2: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
+; CHECK-V-NEXT:    slti a3, s0, 1
+; CHECK-V-NEXT:    slti a1, a1, 1
 ; CHECK-V-NEXT:    blez s0, .LBB20_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB20_4: # %entry
-; CHECK-V-NEXT:    addi a3, a3, -1
-; CHECK-V-NEXT:    sgtz a1, a1
-; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    neg a3, a3
+; CHECK-V-NEXT:    neg a1, a1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    beqz a2, .LBB20_7
 ; CHECK-V-NEXT:  # %bb.5: # %entry
 ; CHECK-V-NEXT:    sgtz a1, a2
 ; CHECK-V-NEXT:    and a2, a3, s1
 ; CHECK-V-NEXT:    bnez s0, .LBB20_8
 ; CHECK-V-NEXT:  .LBB20_6:
 ; CHECK-V-NEXT:    snez a3, a2
 ; CHECK-V-NEXT:    j .LBB20_9
 ; CHECK-V-NEXT:  .LBB20_7:
 ; CHECK-V-NEXT:    snez a1, a0
 ; CHECK-V-NEXT:    and a2, a3, s1
 ; CHECK-V-NEXT:    beqz s0, .LBB20_6
 ; CHECK-V-NEXT:  .LBB20_8: # %entry
 ; CHECK-V-NEXT:    sgtz a3, s0
 ; CHECK-V-NEXT:  .LBB20_9: # %entry
-; CHECK-V-NEXT:    seqz a3, a3
-; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    neg a3, a3
 ; CHECK-V-NEXT:    and a2, a3, a2
-; CHECK-V-NEXT:    seqz a1, a1
-; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    neg a1, a1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)

 ; CHECK-NOV-NEXT:    li a0, -1
 ; CHECK-NOV-NEXT:    srli a3, a0, 1
 ; CHECK-NOV-NEXT:    beqz a1, .LBB21_3
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    slti a4, a1, 0
 ; CHECK-NOV-NEXT:    bnez s1, .LBB21_4
 ; CHECK-NOV-NEXT:  .LBB21_2:
 ; CHECK-NOV-NEXT:    sltu a5, s0, a3
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    beqz a5, .LBB21_5
 ; CHECK-NOV-NEXT:    j .LBB21_6
 ; CHECK-NOV-NEXT:  .LBB21_3:
 ; CHECK-NOV-NEXT:    sltu a4, a2, a3
 ; CHECK-NOV-NEXT:    beqz s1, .LBB21_2
 ; CHECK-NOV-NEXT:  .LBB21_4: # %entry
 ; CHECK-NOV-NEXT:    slti a5, s1, 0
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    bnez a5, .LBB21_6
 ; CHECK-NOV-NEXT:  .LBB21_5: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:  .LBB21_6: # %entry
-; CHECK-NOV-NEXT:    addi a6, a6, -1
-; CHECK-NOV-NEXT:    seqz a5, a4
-; CHECK-NOV-NEXT:    addi a5, a5, -1
+; CHECK-NOV-NEXT:    neg a6, a5
+; CHECK-NOV-NEXT:    neg a5, a4
 ; CHECK-NOV-NEXT:    and a5, a5, a1
 ; CHECK-NOV-NEXT:    bnez a4, .LBB21_8
 ; CHECK-NOV-NEXT:  # %bb.7: # %entry
 ; CHECK-NOV-NEXT:    mv a2, a3
 ; CHECK-NOV-NEXT:  .LBB21_8: # %entry
 ; CHECK-NOV-NEXT:    and a4, a6, s1
 ; CHECK-NOV-NEXT:    slli a1, a0, 63
 ; CHECK-NOV-NEXT:    beq a5, a0, .LBB21_11

 ; CHECK-V-NEXT:    li a2, -1
 ; CHECK-V-NEXT:    srli a3, a2, 1
 ; CHECK-V-NEXT:    beqz s1, .LBB21_3
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    slti a4, s1, 0
 ; CHECK-V-NEXT:    bnez a1, .LBB21_4
 ; CHECK-V-NEXT:  .LBB21_2:
 ; CHECK-V-NEXT:    sltu a5, a0, a3
-; CHECK-V-NEXT:    j .LBB21_5
+; CHECK-V-NEXT:    neg a6, a4
+; CHECK-V-NEXT:    beqz a4, .LBB21_5
+; CHECK-V-NEXT:    j .LBB21_6
 ; CHECK-V-NEXT:  .LBB21_3:
 ; CHECK-V-NEXT:    sltu a4, s0, a3
 ; CHECK-V-NEXT:    beqz a1, .LBB21_2
 ; CHECK-V-NEXT:  .LBB21_4: # %entry
 ; CHECK-V-NEXT:    slti a5, a1, 0
+; CHECK-V-NEXT:    neg a6, a4
+; CHECK-V-NEXT:    bnez a4, .LBB21_6
 ; CHECK-V-NEXT:  .LBB21_5: # %entry
-; CHECK-V-NEXT:    seqz a6, a4
-; CHECK-V-NEXT:    addi a6, a6, -1
-; CHECK-V-NEXT:    bnez a4, .LBB21_7
-; CHECK-V-NEXT:  # %bb.6: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
-; CHECK-V-NEXT:  .LBB21_7: # %entry
+; CHECK-V-NEXT:  .LBB21_6: # %entry
 ; CHECK-V-NEXT:    and a6, a6, s1
-; CHECK-V-NEXT:    seqz a4, a5
-; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    bnez a5, .LBB21_9
-; CHECK-V-NEXT:  # %bb.8: # %entry
+; CHECK-V-NEXT:    neg a4, a5
+; CHECK-V-NEXT:    bnez a5, .LBB21_8
+; CHECK-V-NEXT:  # %bb.7: # %entry
 ; CHECK-V-NEXT:    mv a0, a3
-; CHECK-V-NEXT:  .LBB21_9: # %entry
+; CHECK-V-NEXT:  .LBB21_8: # %entry
 ; CHECK-V-NEXT:    and a4, a4, a1
 ; CHECK-V-NEXT:    slli a1, a2, 63
-; CHECK-V-NEXT:    beq a6, a2, .LBB21_12
-; CHECK-V-NEXT:  # %bb.10: # %entry
+; CHECK-V-NEXT:    beq a6, a2, .LBB21_11
+; CHECK-V-NEXT:  # %bb.9: # %entry
 ; CHECK-V-NEXT:    slti a3, a6, 0
 ; CHECK-V-NEXT:    xori a3, a3, 1
-; CHECK-V-NEXT:    bne a4, a2, .LBB21_13
-; CHECK-V-NEXT:  .LBB21_11:
+; CHECK-V-NEXT:    bne a4, a2, .LBB21_12
+; CHECK-V-NEXT:  .LBB21_10:
 ; CHECK-V-NEXT:    sltu a2, a1, a0
-; CHECK-V-NEXT:    beqz a3, .LBB21_14
-; CHECK-V-NEXT:    j .LBB21_15
-; CHECK-V-NEXT:  .LBB21_12:
+; CHECK-V-NEXT:    beqz a3, .LBB21_13
+; CHECK-V-NEXT:    j .LBB21_14
+; CHECK-V-NEXT:  .LBB21_11:
 ; CHECK-V-NEXT:    sltu a3, a1, s0
-; CHECK-V-NEXT:    beq a4, a2, .LBB21_11
-; CHECK-V-NEXT:  .LBB21_13: # %entry
+; CHECK-V-NEXT:    beq a4, a2, .LBB21_10
+; CHECK-V-NEXT:  .LBB21_12: # %entry
 ; CHECK-V-NEXT:    slti a2, a4, 0
 ; CHECK-V-NEXT:    xori a2, a2, 1
-; CHECK-V-NEXT:    bnez a3, .LBB21_15
-; CHECK-V-NEXT:  .LBB21_14: # %entry
+; CHECK-V-NEXT:    bnez a3, .LBB21_14
+; CHECK-V-NEXT:  .LBB21_13: # %entry
 ; CHECK-V-NEXT:    mv s0, a1
-; CHECK-V-NEXT:  .LBB21_15: # %entry
-; CHECK-V-NEXT:    bnez a2, .LBB21_17
-; CHECK-V-NEXT:  # %bb.16: # %entry
+; CHECK-V-NEXT:  .LBB21_14: # %entry
+; CHECK-V-NEXT:    bnez a2, .LBB21_16
+; CHECK-V-NEXT:  # %bb.15: # %entry
 ; CHECK-V-NEXT:    mv a0, a1
-; CHECK-V-NEXT:  .LBB21_17: # %entry
+; CHECK-V-NEXT:  .LBB21_16: # %entry
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd s0, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -32
-; CHECK-NOV-NEXT:    fmv.s fs0, fa0
-; CHECK-NOV-NEXT:    fmv.s fa0, fa1
+; CHECK-NOV-NEXT:    fmv.s fs0, fa1
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.s fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    snez a1, a1
+; CHECK-NOV-NEXT:    snez a2, s1
+; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a0, a1, a0
-; CHECK-NOV-NEXT:    snez a1, s1
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
+; CHECK-NOV-NEXT:    and a1, a1, a0
+; CHECK-NOV-NEXT:    mv a0, a2
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: utest_f32i64:

 ; CHECK-V-NEXT:    mv s0, a0
 ; CHECK-V-NEXT:    mv s1, a1
 ; CHECK-V-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
 ; CHECK-V-NEXT:    addi a0, sp, 48
 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    snez a2, s1
+; CHECK-V-NEXT:    snez a1, a1
 ; CHECK-V-NEXT:    addi a2, a2, -1
 ; CHECK-V-NEXT:    and a2, a2, s0
-; CHECK-V-NEXT:    snez a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset fs0, -32
-; CHECK-NOV-NEXT:    fmv.s fs0, fa0
-; CHECK-NOV-NEXT:    fmv.s fa0, fa1
+; CHECK-NOV-NEXT:    fmv.s fs0, fa1
 ; CHECK-NOV-NEXT:    call __fixsfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.s fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixsfti@plt
-; CHECK-NOV-NEXT:    mv a2, a1
-; CHECK-NOV-NEXT:    blez a1, .LBB23_2
+; CHECK-NOV-NEXT:    mv a2, s1
+; CHECK-NOV-NEXT:    blez s1, .LBB23_2
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB23_2: # %entry
-; CHECK-NOV-NEXT:    mv a3, s1
-; CHECK-NOV-NEXT:    blez s1, .LBB23_4
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    slti a4, s1, 1
+; CHECK-NOV-NEXT:    blez a1, .LBB23_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a3, 1
+; CHECK-NOV-NEXT:    li a1, 1
 ; CHECK-NOV-NEXT:  .LBB23_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a1, a1
-; CHECK-NOV-NEXT:    addi a4, a1, -1
-; CHECK-NOV-NEXT:    sgtz a1, s1
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
-; CHECK-NOV-NEXT:    beqz a3, .LBB23_7
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    neg a3, a3
+; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    beqz a1, .LBB23_7
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a3
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    sgtz a1, a1
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    bnez a2, .LBB23_8
 ; CHECK-NOV-NEXT:  .LBB23_6:
 ; CHECK-NOV-NEXT:    snez a2, a0
 ; CHECK-NOV-NEXT:    j .LBB23_9
 ; CHECK-NOV-NEXT:  .LBB23_7:
-; CHECK-NOV-NEXT:    snez a3, a1
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    snez a1, a3
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    beqz a2, .LBB23_6
 ; CHECK-NOV-NEXT:  .LBB23_8: # %entry
 ; CHECK-NOV-NEXT:    sgtz a2, a2
 ; CHECK-NOV-NEXT:  .LBB23_9: # %entry
-; CHECK-NOV-NEXT:    seqz a2, a2
-; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a0, a2, a0
-; CHECK-NOV-NEXT:    seqz a2, a3
-; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a1, a2, a1
+; CHECK-NOV-NEXT:    neg a1, a1
+; CHECK-NOV-NEXT:    and a1, a1, a3
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: ustest_f32i64:

 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixsfti@plt
 ; CHECK-V-NEXT:    mv a2, a1
 ; CHECK-V-NEXT:    blez a1, .LBB23_2
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB23_2: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
+; CHECK-V-NEXT:    slti a3, s0, 1
+; CHECK-V-NEXT:    slti a1, a1, 1
 ; CHECK-V-NEXT:    blez s0, .LBB23_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB23_4: # %entry
-; CHECK-V-NEXT:    addi a3, a3, -1
-; CHECK-V-NEXT:    sgtz a1, a1
-; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    neg a3, a3
+; CHECK-V-NEXT:    neg a1, a1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    beqz a2, .LBB23_7
 ; CHECK-V-NEXT:  # %bb.5: # %entry
 ; CHECK-V-NEXT:    sgtz a1, a2
 ; CHECK-V-NEXT:    and a2, a3, s1
 ; CHECK-V-NEXT:    bnez s0, .LBB23_8
 ; CHECK-V-NEXT:  .LBB23_6:
 ; CHECK-V-NEXT:    snez a3, a2
 ; CHECK-V-NEXT:    j .LBB23_9
 ; CHECK-V-NEXT:  .LBB23_7:
 ; CHECK-V-NEXT:    snez a1, a0
 ; CHECK-V-NEXT:    and a2, a3, s1
 ; CHECK-V-NEXT:    beqz s0, .LBB23_6
 ; CHECK-V-NEXT:  .LBB23_8: # %entry
 ; CHECK-V-NEXT:    sgtz a3, s0
 ; CHECK-V-NEXT:  .LBB23_9: # %entry
-; CHECK-V-NEXT:    seqz a3, a3
-; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    neg a3, a3
 ; CHECK-V-NEXT:    and a2, a3, a2
-; CHECK-V-NEXT:    seqz a1, a1
-; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    neg a1, a1
 ; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)

 ; CHECK-NOV-NEXT:    li a0, -1
 ; CHECK-NOV-NEXT:    srli a3, a0, 1
 ; CHECK-NOV-NEXT:    beqz a1, .LBB24_3
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    slti a4, a1, 0
 ; CHECK-NOV-NEXT:    bnez s1, .LBB24_4
 ; CHECK-NOV-NEXT:  .LBB24_2:
 ; CHECK-NOV-NEXT:    sltu a5, s0, a3
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    beqz a5, .LBB24_5
 ; CHECK-NOV-NEXT:    j .LBB24_6
 ; CHECK-NOV-NEXT:  .LBB24_3:
 ; CHECK-NOV-NEXT:    sltu a4, a2, a3
 ; CHECK-NOV-NEXT:    beqz s1, .LBB24_2
 ; CHECK-NOV-NEXT:  .LBB24_4: # %entry
 ; CHECK-NOV-NEXT:    slti a5, s1, 0
-; CHECK-NOV-NEXT:    seqz a6, a5
 ; CHECK-NOV-NEXT:    bnez a5, .LBB24_6
 ; CHECK-NOV-NEXT:  .LBB24_5: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:  .LBB24_6: # %entry
-; CHECK-NOV-NEXT:    addi a6, a6, -1
-; CHECK-NOV-NEXT:    seqz a5, a4
-; CHECK-NOV-NEXT:    addi a5, a5, -1
+; CHECK-NOV-NEXT:    neg a6, a5
+; CHECK-NOV-NEXT:    neg a5, a4
 ; CHECK-NOV-NEXT:    and a5, a5, a1
 ; CHECK-NOV-NEXT:    bnez a4, .LBB24_8
 ; CHECK-NOV-NEXT:  # %bb.7: # %entry
 ; CHECK-NOV-NEXT:    mv a2, a3
 ; CHECK-NOV-NEXT:  .LBB24_8: # %entry
 ; CHECK-NOV-NEXT:    and a4, a6, s1
 ; CHECK-NOV-NEXT:    slli a1, a0, 63
 ; CHECK-NOV-NEXT:    beq a5, a0, .LBB24_11

 ; CHECK-V-NEXT:    li a2, -1
 ; CHECK-V-NEXT:    srli a3, a2, 1
 ; CHECK-V-NEXT:    beqz a1, .LBB24_3
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    slti a4, a1, 0
 ; CHECK-V-NEXT:    bnez s1, .LBB24_4
 ; CHECK-V-NEXT:  .LBB24_2:
 ; CHECK-V-NEXT:    sltu a5, s0, a3
-; CHECK-V-NEXT:    seqz a6, a5
 ; CHECK-V-NEXT:    beqz a5, .LBB24_5
 ; CHECK-V-NEXT:    j .LBB24_6
 ; CHECK-V-NEXT:  .LBB24_3:
 ; CHECK-V-NEXT:    sltu a4, a0, a3
 ; CHECK-V-NEXT:    beqz s1, .LBB24_2
 ; CHECK-V-NEXT:  .LBB24_4: # %entry
 ; CHECK-V-NEXT:    slti a5, s1, 0
-; CHECK-V-NEXT:    seqz a6, a5
 ; CHECK-V-NEXT:    bnez a5, .LBB24_6
 ; CHECK-V-NEXT:  .LBB24_5: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
 ; CHECK-V-NEXT:  .LBB24_6: # %entry
-; CHECK-V-NEXT:    addi a6, a6, -1
-; CHECK-V-NEXT:    seqz a5, a4
-; CHECK-V-NEXT:    addi a5, a5, -1
+; CHECK-V-NEXT:    neg a6, a5
+; CHECK-V-NEXT:    neg a5, a4
 ; CHECK-V-NEXT:    and a5, a5, a1
 ; CHECK-V-NEXT:    bnez a4, .LBB24_8
 ; CHECK-V-NEXT:  # %bb.7: # %entry
 ; CHECK-V-NEXT:    mv a0, a3
 ; CHECK-V-NEXT:  .LBB24_8: # %entry
 ; CHECK-V-NEXT:    and a4, a6, s1
 ; CHECK-V-NEXT:    slli a1, a2, 63
 ; CHECK-V-NEXT:    beq a5, a2, .LBB24_11

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset s2, -32
-; CHECK-NOV-NEXT:    mv s0, a0
-; CHECK-NOV-NEXT:    mv a0, a1
+; CHECK-NOV-NEXT:    mv s0, a1
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    mv s1, a0
 ; CHECK-NOV-NEXT:    mv s2, a1
 ; CHECK-NOV-NEXT:    mv a0, s0
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    snez a1, a1
+; CHECK-NOV-NEXT:    snez a2, s2
+; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a0, a1, a0
-; CHECK-NOV-NEXT:    snez a1, s2
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s1
+; CHECK-NOV-NEXT:    and a1, a1, a0
+; CHECK-NOV-NEXT:    mv a0, a2
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: utesth_f16i64:
 ; CHECK-V:       # %bb.0: # %entry
 ; CHECK-V-NEXT:    addi sp, sp, -48
 ; CHECK-V-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-V-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    .cfi_offset ra, -8
 ; CHECK-V-NEXT:    .cfi_offset s0, -16
 ; CHECK-V-NEXT:    .cfi_offset s1, -24
 ; CHECK-V-NEXT:    .cfi_offset s2, -32
-; CHECK-V-NEXT:    mv s0, a0
-; CHECK-V-NEXT:    mv a0, a1
+; CHECK-V-NEXT:    mv s0, a1
 ; CHECK-V-NEXT:    call __extendhfsf2@plt
 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    mv s1, a0
 ; CHECK-V-NEXT:    mv s2, a1
 ; CHECK-V-NEXT:    mv a0, s0
 ; CHECK-V-NEXT:    call __extendhfsf2@plt
 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    snez a1, a1
+; CHECK-V-NEXT:    snez a2, s2
+; CHECK-V-NEXT:    addi a2, a2, -1
+; CHECK-V-NEXT:    and a2, a2, s1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
-; CHECK-V-NEXT:    snez a1, s2
-; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    and a1, a1, s1
-; CHECK-V-NEXT:    sd a1, 8(sp)
-; CHECK-V-NEXT:    sd a0, 0(sp)
+; CHECK-V-NEXT:    sd a0, 8(sp)
+; CHECK-V-NEXT:    sd a2, 0(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 8
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    mv a0, sp
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
 ; CHECK-V-NEXT:    vslideup.vi v8, v9, 1
 ; CHECK-V-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload

 ; CHECK-NOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; CHECK-NOV-NEXT:    .cfi_offset ra, -8
 ; CHECK-NOV-NEXT:    .cfi_offset s0, -16
 ; CHECK-NOV-NEXT:    .cfi_offset s1, -24
 ; CHECK-NOV-NEXT:    .cfi_offset s2, -32
-; CHECK-NOV-NEXT:    mv s2, a0
-; CHECK-NOV-NEXT:    mv a0, a1
+; CHECK-NOV-NEXT:    mv s2, a1
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    call __fixsfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    mv a0, s2
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    call __fixsfti@plt
-; CHECK-NOV-NEXT:    mv a2, a1
-; CHECK-NOV-NEXT:    blez a1, .LBB26_2
+; CHECK-NOV-NEXT:    mv a2, s1
+; CHECK-NOV-NEXT:    blez s1, .LBB26_2
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB26_2: # %entry
-; CHECK-NOV-NEXT:    mv a3, s1
-; CHECK-NOV-NEXT:    blez s1, .LBB26_4
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    slti a4, s1, 1
+; CHECK-NOV-NEXT:    blez a1, .LBB26_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a3, 1
+; CHECK-NOV-NEXT:    li a1, 1
 ; CHECK-NOV-NEXT:  .LBB26_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a1, a1
-; CHECK-NOV-NEXT:    addi a4, a1, -1
-; CHECK-NOV-NEXT:    sgtz a1, s1
-; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
-; CHECK-NOV-NEXT:    beqz a3, .LBB26_7
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    neg a3, a3
+; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    beqz a1, .LBB26_7
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a3
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    sgtz a1, a1
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    bnez a2, .LBB26_8
 ; CHECK-NOV-NEXT:  .LBB26_6:
 ; CHECK-NOV-NEXT:    snez a2, a0
 ; CHECK-NOV-NEXT:    j .LBB26_9
 ; CHECK-NOV-NEXT:  .LBB26_7:
-; CHECK-NOV-NEXT:    snez a3, a1
-; CHECK-NOV-NEXT:    and a0, a4, a0
+; CHECK-NOV-NEXT:    snez a1, a3
+; CHECK-NOV-NEXT:    and a0, a4, s0
 ; CHECK-NOV-NEXT:    beqz a2, .LBB26_6
 ; CHECK-NOV-NEXT:  .LBB26_8: # %entry
 ; CHECK-NOV-NEXT:    sgtz a2, a2
 ; CHECK-NOV-NEXT:  .LBB26_9: # %entry
-; CHECK-NOV-NEXT:    seqz a2, a2
-; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    neg a2, a2
 ; CHECK-NOV-NEXT:    and a0, a2, a0
-; CHECK-NOV-NEXT:    seqz a2, a3
-; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a1, a2, a1
+; CHECK-NOV-NEXT:    neg a1, a1
+; CHECK-NOV-NEXT:    and a1, a1, a3
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: ustest_f16i64:
 ; CHECK-V:       # %bb.0: # %entry
 ; CHECK-V-NEXT:    addi sp, sp, -48
 ; CHECK-V-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-V-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; CHECK-V-NEXT:    .cfi_offset ra, -8
 ; CHECK-V-NEXT:    .cfi_offset s0, -16
 ; CHECK-V-NEXT:    .cfi_offset s1, -24
 ; CHECK-V-NEXT:    .cfi_offset s2, -32
-; CHECK-V-NEXT:    mv s2, a0
-; CHECK-V-NEXT:    mv a0, a1
+; CHECK-V-NEXT:    mv s2, a1
 ; CHECK-V-NEXT:    call __extendhfsf2@plt
 ; CHECK-V-NEXT:    call __fixsfti@plt
 ; CHECK-V-NEXT:    mv s0, a0
 ; CHECK-V-NEXT:    mv s1, a1
 ; CHECK-V-NEXT:    mv a0, s2
 ; CHECK-V-NEXT:    call __extendhfsf2@plt
 ; CHECK-V-NEXT:    call __fixsfti@plt
-; CHECK-V-NEXT:    mv a2, a1
-; CHECK-V-NEXT:    blez a1, .LBB26_2
+; CHECK-V-NEXT:    mv a2, s1
+; CHECK-V-NEXT:    blez s1, .LBB26_2
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB26_2: # %entry
-; CHECK-V-NEXT:    mv a3, s1
-; CHECK-V-NEXT:    blez s1, .LBB26_4
+; CHECK-V-NEXT:    slti a4, a1, 1
+; CHECK-V-NEXT:    slti a3, s1, 1
+; CHECK-V-NEXT:    blez a1, .LBB26_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
-; CHECK-V-NEXT:    li a3, 1
+; CHECK-V-NEXT:    li a1, 1
 ; CHECK-V-NEXT:  .LBB26_4: # %entry
-; CHECK-V-NEXT:    sgtz a1, a1
-; CHECK-V-NEXT:    addi a4, a1, -1
-; CHECK-V-NEXT:    sgtz a1, s1
-; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    and a1, a1, s0
-; CHECK-V-NEXT:    beqz a3, .LBB26_7
-; CHECK-V-NEXT:  # %bb.5: # %entry
-; CHECK-V-NEXT:    sgtz a3, a3
+; CHECK-V-NEXT:    neg a3, a3
+; CHECK-V-NEXT:    neg a4, a4
 ; CHECK-V-NEXT:    and a0, a4, a0
+; CHECK-V-NEXT:    beqz a1, .LBB26_7
+; CHECK-V-NEXT:  # %bb.5: # %entry
+; CHECK-V-NEXT:    sgtz a1, a1
+; CHECK-V-NEXT:    and a3, a3, s0
 ; CHECK-V-NEXT:    bnez a2, .LBB26_8
 ; CHECK-V-NEXT:  .LBB26_6:
-; CHECK-V-NEXT:    snez a2, a0
+; CHECK-V-NEXT:    snez a2, a3
 ; CHECK-V-NEXT:    j .LBB26_9
 ; CHECK-V-NEXT:  .LBB26_7:
-; CHECK-V-NEXT:    snez a3, a1
-; CHECK-V-NEXT:    and a0, a4, a0
+; CHECK-V-NEXT:    snez a1, a0
+; CHECK-V-NEXT:    and a3, a3, s0
 ; CHECK-V-NEXT:    beqz a2, .LBB26_6
 ; CHECK-V-NEXT:  .LBB26_8: # %entry
 ; CHECK-V-NEXT:    sgtz a2, a2
 ; CHECK-V-NEXT:  .LBB26_9: # %entry
-; CHECK-V-NEXT:    seqz a2, a2
-; CHECK-V-NEXT:    addi a2, a2, -1
-; CHECK-V-NEXT:    and a0, a2, a0
-; CHECK-V-NEXT:    seqz a2, a3
-; CHECK-V-NEXT:    addi a2, a2, -1
-; CHECK-V-NEXT:    and a1, a2, a1
-; CHECK-V-NEXT:    sd a1, 8(sp)
-; CHECK-V-NEXT:    sd a0, 0(sp)
+; CHECK-V-NEXT:    neg a2, a2
+; CHECK-V-NEXT:    and a2, a2, a3
+; CHECK-V-NEXT:    neg a1, a1
+; CHECK-V-NEXT:    and a0, a1, a0
+; CHECK-V-NEXT:    sd a0, 8(sp)
+; CHECK-V-NEXT:    sd a2, 0(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 8
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    mv a0, sp
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
 ; CHECK-V-NEXT:    vslideup.vi v8, v9, 1
 ; CHECK-V-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload

 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB47_2: # %entry
 ; CHECK-NOV-NEXT:    mv a4, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB47_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
 ; CHECK-NOV-NEXT:    li a4, 1
 ; CHECK-NOV-NEXT:  .LBB47_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a1
-; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    neg a3, a3
 ; CHECK-NOV-NEXT:    and a3, a3, a0
 ; CHECK-NOV-NEXT:    addi a0, a1, -1
 ; CHECK-NOV-NEXT:    seqz a0, a0
 ; CHECK-NOV-NEXT:    addi a1, a0, -1
-; CHECK-NOV-NEXT:    sgtz a0, s1
-; CHECK-NOV-NEXT:    addi a0, a0, -1
+; CHECK-NOV-NEXT:    slti a0, s1, 1
+; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi a5, s1, -1
 ; CHECK-NOV-NEXT:    seqz a5, a5
 ; CHECK-NOV-NEXT:    addi a5, a5, -1
 ; CHECK-NOV-NEXT:    and a0, a5, a0
 ; CHECK-NOV-NEXT:    beqz a4, .LBB47_6
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a4, a4

 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixdfti@plt
 ; CHECK-V-NEXT:    mv a2, a1
 ; CHECK-V-NEXT:    blez a1, .LBB47_2
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB47_2: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
-; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    slti a3, s0, 1
+; CHECK-V-NEXT:    neg a3, a3
 ; CHECK-V-NEXT:    and a3, a3, s1
 ; CHECK-V-NEXT:    addi a4, s0, -1
 ; CHECK-V-NEXT:    seqz a4, a4
 ; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    sgtz a5, a1
-; CHECK-V-NEXT:    addi a5, a5, -1
+; CHECK-V-NEXT:    slti a5, a1, 1
+; CHECK-V-NEXT:    neg a5, a5
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a6, a1
 ; CHECK-V-NEXT:    blez s0, .LBB47_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB47_4: # %entry
 ; CHECK-V-NEXT:    and a1, a5, a0
 ; CHECK-V-NEXT:    addi a5, a6, -1

 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB50_2: # %entry
 ; CHECK-NOV-NEXT:    mv a4, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB50_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
 ; CHECK-NOV-NEXT:    li a4, 1
 ; CHECK-NOV-NEXT:  .LBB50_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a1
-; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    neg a3, a3
 ; CHECK-NOV-NEXT:    and a3, a3, a0
 ; CHECK-NOV-NEXT:    addi a0, a1, -1
 ; CHECK-NOV-NEXT:    seqz a0, a0
 ; CHECK-NOV-NEXT:    addi a1, a0, -1
-; CHECK-NOV-NEXT:    sgtz a0, s1
-; CHECK-NOV-NEXT:    addi a0, a0, -1
+; CHECK-NOV-NEXT:    slti a0, s1, 1
+; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi a5, s1, -1
 ; CHECK-NOV-NEXT:    seqz a5, a5
 ; CHECK-NOV-NEXT:    addi a5, a5, -1
 ; CHECK-NOV-NEXT:    and a0, a5, a0
 ; CHECK-NOV-NEXT:    beqz a4, .LBB50_6
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a4, a4

 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixsfti@plt
 ; CHECK-V-NEXT:    mv a2, a1
 ; CHECK-V-NEXT:    blez a1, .LBB50_2
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB50_2: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
-; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    slti a3, s0, 1
+; CHECK-V-NEXT:    neg a3, a3
 ; CHECK-V-NEXT:    and a3, a3, s1
 ; CHECK-V-NEXT:    addi a4, s0, -1
 ; CHECK-V-NEXT:    seqz a4, a4
 ; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    sgtz a5, a1
-; CHECK-V-NEXT:    addi a5, a5, -1
+; CHECK-V-NEXT:    slti a5, a1, 1
+; CHECK-V-NEXT:    neg a5, a5
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a6, a1
 ; CHECK-V-NEXT:    blez s0, .LBB50_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB50_4: # %entry
 ; CHECK-V-NEXT:    and a1, a5, a0
 ; CHECK-V-NEXT:    addi a5, a6, -1

 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB53_2: # %entry
 ; CHECK-NOV-NEXT:    mv a4, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB53_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
 ; CHECK-NOV-NEXT:    li a4, 1
 ; CHECK-NOV-NEXT:  .LBB53_4: # %entry
-; CHECK-NOV-NEXT:    sgtz a3, a1
-; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    slti a3, a1, 1
+; CHECK-NOV-NEXT:    neg a3, a3
 ; CHECK-NOV-NEXT:    and a3, a3, a0
 ; CHECK-NOV-NEXT:    addi a0, a1, -1
 ; CHECK-NOV-NEXT:    seqz a0, a0
 ; CHECK-NOV-NEXT:    addi a1, a0, -1
-; CHECK-NOV-NEXT:    sgtz a0, s1
-; CHECK-NOV-NEXT:    addi a0, a0, -1
+; CHECK-NOV-NEXT:    slti a0, s1, 1
+; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi a5, s1, -1
 ; CHECK-NOV-NEXT:    seqz a5, a5
 ; CHECK-NOV-NEXT:    addi a5, a5, -1
 ; CHECK-NOV-NEXT:    and a0, a5, a0
 ; CHECK-NOV-NEXT:    beqz a4, .LBB53_6
 ; CHECK-NOV-NEXT:  # %bb.5: # %entry
 ; CHECK-NOV-NEXT:    sgtz a4, a4

 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB53_2: # %entry
 ; CHECK-V-NEXT:    mv a4, s1
 ; CHECK-V-NEXT:    blez s1, .LBB53_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li a4, 1
 ; CHECK-V-NEXT:  .LBB53_4: # %entry
-; CHECK-V-NEXT:    sgtz a3, a1
-; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    slti a3, a1, 1
+; CHECK-V-NEXT:    neg a3, a3
 ; CHECK-V-NEXT:    and a3, a3, a0
 ; CHECK-V-NEXT:    addi a0, a1, -1
 ; CHECK-V-NEXT:    seqz a0, a0
 ; CHECK-V-NEXT:    addi a1, a0, -1
-; CHECK-V-NEXT:    sgtz a0, s1
-; CHECK-V-NEXT:    addi a0, a0, -1
+; CHECK-V-NEXT:    slti a0, s1, 1
+; CHECK-V-NEXT:    neg a0, a0
 ; CHECK-V-NEXT:    and a0, a0, s0
 ; CHECK-V-NEXT:    addi a5, s1, -1
 ; CHECK-V-NEXT:    seqz a5, a5
 ; CHECK-V-NEXT:    addi a5, a5, -1
 ; CHECK-V-NEXT:    and a0, a5, a0
 ; CHECK-V-NEXT:    beqz a4, .LBB53_6
 ; CHECK-V-NEXT:  # %bb.5: # %entry
 ; CHECK-V-NEXT:    sgtz a4, a4

llvm/test/CodeGen/RISCV/half-convert.ll

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    neg s1, a0
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB8_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB8_2: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s2, a0, -1
 ; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    and a0, s2, a0
+; RV32I-NEXT:    or a0, s1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_h_sat:

 ; RV32IZFH-NEXT:    beqz a2, .LBB10_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB10_4: # %start
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 ; RV32IDZFH-NEXT:    beqz a2, .LBB10_4
 ; RV32IDZFH-NEXT:  # %bb.3:
 ; RV32IDZFH-NEXT:    addi a1, a3, -1
 ; RV32IDZFH-NEXT:  .LBB10_4: # %start
 ; RV32IDZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IDZFH-NEXT:    seqz a3, a3
 ; RV32IDZFH-NEXT:    addi a3, a3, -1
 ; RV32IDZFH-NEXT:    and a1, a3, a1
-; RV32IDZFH-NEXT:    seqz a4, s0
-; RV32IDZFH-NEXT:    addi a4, a4, -1
+; RV32IDZFH-NEXT:    neg a2, a2
+; RV32IDZFH-NEXT:    neg a4, s0
 ; RV32IDZFH-NEXT:    and a0, a4, a0
-; RV32IDZFH-NEXT:    seqz a2, a2
-; RV32IDZFH-NEXT:    addi a2, a2, -1
 ; RV32IDZFH-NEXT:    or a0, a2, a0
 ; RV32IDZFH-NEXT:    and a0, a3, a0
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;

 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfdi@plt
-; RV32I-NEXT:    mv s5, a0
-; RV32I-NEXT:    mv s2, a1
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui s4, 524288
+; RV32I-NEXT:    lui s3, 524288
+; RV32I-NEXT:    bltz s2, .LBB10_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:  .LBB10_2: # %start
+; RV32I-NEXT:    lui a0, 389120
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    blez a0, .LBB10_4
+; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:    addi s3, s4, -1
+; RV32I-NEXT:  .LBB10_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
-; RV32I-NEXT:    addi s1, a0, -1
-; RV32I-NEXT:    lui a0, 389120
-; RV32I-NEXT:    addi s3, a0, -1
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and s3, a0, s3
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bgtz a0, .LBB10_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    slti a0, s4, 0
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s5
-; RV32I-NEXT:    and s1, s1, a0
-; RV32I-NEXT:  .LBB10_2: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s2, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    lui s5, 524288
-; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    bltz a0, .LBB10_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s4, s2
-; RV32I-NEXT:  .LBB10_4: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    blez a0, .LBB10_6
-; RV32I-NEXT:  # %bb.5:
-; RV32I-NEXT:    addi s4, s5, -1
-; RV32I-NEXT:  .LBB10_6: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    or s1, s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s4
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_l_h_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill

 }
 
 define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
+; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI12_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
-; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
+; RV32IDZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
+; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IDZFH-NEXT:    neg s0, a0
 ; RV32IDZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IDZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IDZFH-NEXT:    seqz a0, a0
-; RV32IDZFH-NEXT:    addi s0, a0, -1
-; RV32IDZFH-NEXT:    fmv.s fa0, fs0
+; RV32IDZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IDZFH-NEXT:    neg s1, a0
 ; RV32IDZFH-NEXT:    call __fixunssfdi@plt
-; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI12_0)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a2)
-; RV32IDZFH-NEXT:    and a0, s0, a0
-; RV32IDZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IDZFH-NEXT:    seqz a2, a2
-; RV32IDZFH-NEXT:    addi a2, a2, -1
-; RV32IDZFH-NEXT:    or a0, a2, a0
-; RV32IDZFH-NEXT:    and a1, s0, a1
-; RV32IDZFH-NEXT:    or a1, a2, a1
+; RV32IDZFH-NEXT:    and a0, s1, a0
+; RV32IDZFH-NEXT:    or a0, s0, a0
+; RV32IDZFH-NEXT:    and a1, s1, a1
+; RV32IDZFH-NEXT:    or a1, s0, a1
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
+; RV32IDZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addi a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a1, a0
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a0, 391168
-; RV32I-NEXT:    addi s2, a0, -1
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    addi s1, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    call __fixunssfdi@plt
-; RV32I-NEXT:    mv s4, a0
-; RV32I-NEXT:    mv s3, a1
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    neg s3, a0
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB12_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s4
-; RV32I-NEXT:  .LBB12_2: # %start
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s4, a0, -1
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfdi@plt
+; RV32I-NEXT:    mv s2, a1
+; RV32I-NEXT:    and a0, s4, a0
+; RV32I-NEXT:    or s3, s3, a0
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s2, a0
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    neg s1, a0
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB12_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    or s2, s2, s3
-; RV32I-NEXT:  .LBB12_4: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    or a1, s1, a0
+; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_h_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a0, 391168
 ; RV64I-NEXT:    addiw a1, a0, -1
-; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    sgtz a0, a0
-; RV64I-NEXT:    neg s0, a0
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    call __fixunssfdi@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    neg s1, a0
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    bltz a0, .LBB12_2
-; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    or s0, s0, s1
-; RV64I-NEXT:  .LBB12_2: # %start
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    addi s2, a0, -1
 ; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    call __fixunssfdi@plt
+; RV64I-NEXT:    and a0, s2, a0
+; RV64I-NEXT:    or a0, s1, a0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    neg s1, a0
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    bltz a0, .LBB39_2
-; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    or s0, s0, s1
-; RV32I-NEXT:  .LBB39_2: # %start
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    addi s2, a0, -1
 ; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    and a0, s2, a0
+; RV32I-NEXT:    or a0, s1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_h_sat_zext:

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; RV32IZFH-NEXT:    beqz a2, .LBB1_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB1_4:
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call floorf@plt
-; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
+; RV32IZFH-NEXT:    fcvt.s.h fa0, ft1
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1

 ; RV32IZFH-NEXT:    beqz a2, .LBB5_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB5_4:
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call ceilf@plt
-; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI7_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
+; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
+; RV32IZFH-NEXT:    fcvt.s.h fa0, ft1
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI7_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1

 ; RV32IZFH-NEXT:    beqz a2, .LBB9_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB9_4:
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call truncf@plt
-; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
+; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
+; RV32IZFH-NEXT:    fcvt.s.h fa0, ft1
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1

 ; RV32IZFH-NEXT:    beqz a2, .LBB13_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB13_4:
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call roundf@plt
-; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI15_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
+; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
+; RV32IZFH-NEXT:    fcvt.s.h fa0, ft1
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI15_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1

 ; RV32IZFH-NEXT:    beqz a2, .LBB17_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB17_4:
 ; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
 ; RV32IZFH-NEXT:    seqz a3, a3
 ; RV32IZFH-NEXT:    addi a3, a3, -1
 ; RV32IZFH-NEXT:    and a1, a3, a1
-; RV32IZFH-NEXT:    seqz a4, s0
-; RV32IZFH-NEXT:    addi a4, a4, -1
+; RV32IZFH-NEXT:    neg a2, a2
+; RV32IZFH-NEXT:    neg a4, s0
 ; RV32IZFH-NEXT:    and a0, a4, a0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a3, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call roundevenf@plt
-; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI19_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
+; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
+; RV32IZFH-NEXT:    fcvt.s.h fa0, ft1
+; RV32IZFH-NEXT:    flt.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    addi s0, a0, -1
-; RV32IZFH-NEXT:    fmv.s fa0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fa0
+; RV32IZFH-NEXT:    neg s1, a0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI19_0)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
-; RV32IZFH-NEXT:    seqz a2, a2
-; RV32IZFH-NEXT:    addi a2, a2, -1
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    and a0, s1, a0
+; RV32IZFH-NEXT:    or a0, s0, a0
+; RV32IZFH-NEXT:    and a1, s1, a1
+; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1

llvm/test/CodeGen/RISCV/min-max.ll

; ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 %b, i32 16)
   %d = and i32 %c, -4
   ret i32 %d
 }
 
 define signext i32 @smin_i32_negone(i32 signext %a) {
 ; NOZBB-LABEL: smin_i32_negone:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    slti a1, a0, 0
+; NOZBB-NEXT:    slti a1, a0, -1
 ; NOZBB-NEXT:    addi a1, a1, -1
 ; NOZBB-NEXT:    or a0, a1, a0
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: smin_i32_negone:
 ; ZBB:       # %bb.0:
 ; ZBB-NEXT:    li a1, -1
 ; ZBB-NEXT:    min a0, a0, a1
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)
   ret i32 %c
 }
 
 define i64 @smin_i64_negone(i64 %a) {
 ; RV32I-LABEL: smin_i64_negone:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    beq a1, a2, .LBB27_2
-; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slti a2, a1, -1
+; RV32I-NEXT:    li a3, -1
 ; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    beq a1, a3, .LBB27_2
+; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:  .LBB27_2:
-; RV32I-NEXT:    slti a2, a1, 0
-; RV32I-NEXT:    addi a2, a2, -1
 ; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: smin_i64_negone:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slti a1, a0, 0
+; RV64I-NEXT:    slti a1, a0, -1
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: smin_i64_negone:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    li a2, -1
 ; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2

llvm/test/CodeGen/RISCV/rv64zbb.ll

 ; RV64I-NEXT:    beqz s0, .LBB9_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srliw a0, a0, 27
 ; RV64I-NEXT:    lui a1, %hi(.LCPI9_0)
 ; RV64I-NEXT:    addi a1, a1, %lo(.LCPI9_0)
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lbu a1, 0(a0)
 ; RV64I-NEXT:  .LBB9_2:
-; RV64I-NEXT:    addi a0, a1, 1
-; RV64I-NEXT:    seqz a1, s0
-; RV64I-NEXT:    addi a1, a1, -1
-; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    seqz a0, s0
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: ffs_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ctzw a1, a0

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

; RV64ZBB-NEXT:    ret
   %sel = select i1 %cmp, i32 %sub, i32 0
   ret i32 %sel
 }
 
 define i8 @sel_shift_bool_i8(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    andi a0, a0, -128
 ; CHECK-NEXT:    ret
   %shl = select i1 %t, i8 128, i8 0
   ret i8 %shl
 }
 
 define i16 @sel_shift_bool_i16(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i16:

llvm/test/CodeGen/RISCV/uadd_sat.ll

 ; RV32I-NEXT:    add a3, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    neg a1, a0
 ; RV32I-NEXT:    or a0, a1, a2
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a1, a0, a1
 ; RV64I-NEXT:    sltu a0, a1, a0
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a3
 ; RV32IZbb-NEXT:    add a2, a0, a2
 ; RV32IZbb-NEXT:    sltu a0, a2, a0
 ; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    seqz a0, a0
-; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    neg a1, a0
 ; RV32IZbb-NEXT:    or a0, a1, a2
 ; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func2:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    not a2, a1
 ; RV64IZbb-NEXT:    minu a0, a0, a2

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

 ; RV32I-NEXT:    add a3, a1, a5
 ; RV32I-NEXT:    add a2, a0, a4
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    neg a1, a0
 ; RV32I-NEXT:    or a0, a1, a2
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a1, a0, a2
 ; RV64I-NEXT:    sltu a0, a1, a0
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a5
 ; RV32IZbb-NEXT:    add a2, a0, a4
 ; RV32IZbb-NEXT:    sltu a0, a2, a0
 ; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    seqz a0, a0
-; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    neg a1, a0
 ; RV32IZbb-NEXT:    or a0, a1, a2
 ; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func64:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    not a1, a2
 ; RV64IZbb-NEXT:    minu a0, a0, a1

llvm/test/CodeGen/RISCV/usub_sat.ll

 ; RV32I-NEXT:    sub a2, a0, a2
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
 ; RV32I-NEXT:    j .LBB1_3
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
 ; RV32I-NEXT:  .LBB1_3:
-; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    and a0, a1, a2
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a1

 ; RV32IZbb-NEXT:    sub a2, a0, a2
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a1, a3
 ; RV32IZbb-NEXT:    j .LBB1_3
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    sltu a0, a0, a2
 ; RV32IZbb-NEXT:  .LBB1_3:
-; RV32IZbb-NEXT:    snez a0, a0
 ; RV32IZbb-NEXT:    addi a1, a0, -1
 ; RV32IZbb-NEXT:    and a0, a1, a2
 ; RV32IZbb-NEXT:    and a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func2:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    maxu a0, a0, a1

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

 ; RV32I-NEXT:    sub a3, a0, a4
 ; RV32I-NEXT:    beq a2, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a2
 ; RV32I-NEXT:    j .LBB1_3
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    sltu a0, a0, a3
 ; RV32I-NEXT:  .LBB1_3:
-; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    and a0, a1, a3
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a2

 ; RV32IZbb-NEXT:    sub a3, a0, a4
 ; RV32IZbb-NEXT:    beq a2, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a1, a2
 ; RV32IZbb-NEXT:    j .LBB1_3
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    sltu a0, a0, a3
 ; RV32IZbb-NEXT:  .LBB1_3:
-; RV32IZbb-NEXT:    snez a0, a0
 ; RV32IZbb-NEXT:    addi a1, a0, -1
 ; RV32IZbb-NEXT:    and a0, a1, a3
 ; RV32IZbb-NEXT:    and a1, a1, a2
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func64:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    maxu a0, a0, a2

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
 ; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
 ; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV64
 
 ; This test would lead one of the DAGCombiner's visitVSELECT optimizations to
 ; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>)
 ; upon seeing that the V extension is enabled. The invalid MVT has a null
 ; Type*, which then segfaulted when accessed (as an EVT).
 define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
 ; RV32-LABEL: vec3_setcc_crash:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lw a0, 0(a0)
 ; RV32-NEXT:    srli a2, a0, 16
-; RV32-NEXT:    slli a3, a0, 8
-; RV32-NEXT:    srai a3, a3, 24
-; RV32-NEXT:    slli a4, a0, 24
+; RV32-NEXT:    srli a3, a0, 8
+; RV32-NEXT:    slli a4, a0, 16
 ; RV32-NEXT:    srai a4, a4, 24
-; RV32-NEXT:    srli a5, a0, 8
-; RV32-NEXT:    slli a6, a0, 16
+; RV32-NEXT:    slli a5, a0, 24
+; RV32-NEXT:    srai a5, a5, 24
+; RV32-NEXT:    slli a6, a0, 8
 ; RV32-NEXT:    srai a6, a6, 24
 ; RV32-NEXT:    sgtz a6, a6
-; RV32-NEXT:    neg a6, a6
-; RV32-NEXT:    and a5, a6, a5
-; RV32-NEXT:    slli a5, a5, 8
+; RV32-NEXT:    sgtz a5, a5
 ; RV32-NEXT:    sgtz a4, a4
 ; RV32-NEXT:    neg a4, a4
+; RV32-NEXT:    and a3, a4, a3
+; RV32-NEXT:    slli a3, a3, 8
+; RV32-NEXT:    neg a4, a5
 ; RV32-NEXT:    and a0, a4, a0
 ; RV32-NEXT:    andi a0, a0, 255
-; RV32-NEXT:    or a0, a0, a5
-; RV32-NEXT:    sgtz a3, a3
-; RV32-NEXT:    neg a3, a3
+; RV32-NEXT:    or a0, a0, a3
+; RV32-NEXT:    neg a3, a6
 ; RV32-NEXT:    and a2, a3, a2
 ; RV32-NEXT:    sb a2, 2(a1)
 ; RV32-NEXT:    sh a0, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vec3_setcc_crash:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lw a0, 0(a0)
 ; RV64-NEXT:    srli a2, a0, 16
-; RV64-NEXT:    slli a3, a0, 40
-; RV64-NEXT:    srai a3, a3, 56
-; RV64-NEXT:    slli a4, a0, 56
+; RV64-NEXT:    srli a3, a0, 8
+; RV64-NEXT:    slli a4, a0, 48
 ; RV64-NEXT:    srai a4, a4, 56
-; RV64-NEXT:    srli a5, a0, 8
-; RV64-NEXT:    slli a6, a0, 48
+; RV64-NEXT:    slli a5, a0, 56
+; RV64-NEXT:    srai a5, a5, 56
+; RV64-NEXT:    slli a6, a0, 40
 ; RV64-NEXT:    srai a6, a6, 56
 ; RV64-NEXT:    sgtz a6, a6
-; RV64-NEXT:    neg a6, a6
-; RV64-NEXT:    and a5, a6, a5
-; RV64-NEXT:    slli a5, a5, 8
+; RV64-NEXT:    sgtz a5, a5
 ; RV64-NEXT:    sgtz a4, a4
 ; RV64-NEXT:    neg a4, a4
+; RV64-NEXT:    and a3, a4, a3
+; RV64-NEXT:    slli a3, a3, 8
+; RV64-NEXT:    neg a4, a5
 ; RV64-NEXT:    and a0, a4, a0
 ; RV64-NEXT:    andi a0, a0, 255
-; RV64-NEXT:    or a0, a0, a5
-; RV64-NEXT:    sgtz a3, a3
-; RV64-NEXT:    neg a3, a3
+; RV64-NEXT:    or a0, a0, a3
+; RV64-NEXT:    neg a3, a6
 ; RV64-NEXT:    and a2, a3, a2
 ; RV64-NEXT:    sb a2, 2(a1)
 ; RV64-NEXT:    sh a0, 0(a1)
 ; RV64-NEXT:    ret
   %a = load <3 x i8>, <3 x i8>* %in
   %cmp = icmp sgt <3 x i8> %a, zeroinitializer
   %c = select <3 x i1> %cmp, <3 x i8> %a, <3 x i8> zeroinitializer
   store <3 x i8> %c, <3 x i8>* %out
   ret void
 }