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Differential D135588

[AArch64]SME2 multi-vec FP/INT down convert 2/4 registers
ClosedPublic

Authored by CarolineConcatto on Oct 10 2022, 8:04 AM.

Details

Reviewers
sdesmalen
paulwalker-arm
aemerson
david-arm
kmclaughlin
Commits
rG830b5e823af0: [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers
Summary

This patch implements
Int:

SQCVT: Multi-vector signed saturating extract narrow for 2 and 4 registers.
UQCVT: Multi-vector unsigned saturating extract narrow for 2 and 4 registers.
SQCVTU: Multi-vector signed saturating unsigned extract narrow for 2 and 4 registers
SQCVTN:  Multi-vector signed saturating extract narrow and interleave.
SQCVTUN: Multi-vector signed saturating unsigned extract narrow and interleave.
UQCVTN: Multi-vector unsigned saturating extract narrow and interleave.

FP:

FCVT(narrowing): Multi-vector floating-point convert from single-precision to
                packed half-precision.
FCVTN: Multi-vector floating-point convert from single-precision to
         interleaved half-precision.
BFCVT: Multi-vector floating-point convert from single-precision to packed
       BFloat16 format.
BFCVTN: : Multi-vector floating-point convert from single-precision to
          interleaved BFloat16 format.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Diff Detail

Event Timeline

CarolineConcatto created this revision.Oct 10 2022, 8:04 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 8:04 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
CarolineConcatto requested review of this revision.Oct 10 2022, 8:04 AM
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Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B191281: Diff 466507.Oct 10 2022, 8:05 AM
Matt added a subscriber: Matt.Oct 10 2022, 10:53 PM
CarolineConcatto added reviewers: sdesmalen, paulwalker-arm, aemerson, david-arm, kmclaughlin.Oct 19 2022, 6:44 AM
sdesmalen accepted this revision.Oct 19 2022, 9:40 AM
sdesmalen added inline comments.
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
281

nit: can you group all the ones using sme2_cvt_vg2_single together?

This revision is now accepted and ready to land.Oct 19 2022, 9:40 AM
CarolineConcatto added a child revision: D135593: [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers.Oct 21 2022, 5:04 AM
This revision was landed with ongoing or failed builds.Oct 21 2022, 6:36 AM
Closed by commit rG830b5e823af0: [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers (authored by CarolineConcatto). · Explain Why
This revision was automatically updated to reflect the committed changes.
CarolineConcatto marked an inline comment as done.
CarolineConcatto added a commit: rG830b5e823af0: [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
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test/
MC/
AArch64/
SME2/
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Diff 469578

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>; defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>; defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
defm FMLAL_MZZI : sme2_mla_long_array_index<"fmlal", 0b10, 0b00>; defm FMLAL_MZZI : sme2_mla_long_array_index<"fmlal", 0b10, 0b00>;
defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal", 0b00>; defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal", 0b00>;
defm FMLAL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlal", 0b00>; defm FMLAL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlal", 0b00>;
defm FMLAL_MZZ : sme2_mla_long_array_single<"fmlal", 0b00, 0b00>; defm FMLAL_MZZ : sme2_mla_long_array_single<"fmlal", 0b00, 0b00>;
defm FMLAL_VG2_M2ZZ : sme2_fp_mla_long_array_vg2_single<"fmlal", 0b00>; defm FMLAL_VG2_M2ZZ : sme2_fp_mla_long_array_vg2_single<"fmlal", 0b00>;
defm FMLAL_VG4_M4ZZ : sme2_fp_mla_long_array_vg4_single<"fmlal", 0b00>; defm FMLAL_VG4_M4ZZ : sme2_fp_mla_long_array_vg4_single<"fmlal", 0b00>;
sdesmalenUnsubmitted
Done
ReplyInline Actions

nit: can you group all the ones using sme2_cvt_vg2_single together?

sdesmalen: nit: can you group all the ones using `sme2_cvt_vg2_single` together?
defm FMLAL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"fmlal", 0b00>; defm FMLAL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"fmlal", 0b00>;
defm FMLAL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"fmlal", 0b00>; defm FMLAL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"fmlal", 0b00>;
defm FMLSL_MZZI : sme2_mla_long_array_index<"fmlsl", 0b10, 0b01>; defm FMLSL_MZZI : sme2_mla_long_array_index<"fmlsl", 0b10, 0b01>;
defm FMLSL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlsl", 0b01>; defm FMLSL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlsl", 0b01>;
defm FMLSL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlsl", 0b01>; defm FMLSL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlsl", 0b01>;
defm FMLSL_MZZ : sme2_mla_long_array_single<"fmlsl", 0b00, 0b01>; defm FMLSL_MZZ : sme2_mla_long_array_single<"fmlsl", 0b00, 0b01>;
defm FMLSL_VG2_M2ZZ : sme2_fp_mla_long_array_vg2_single<"fmlsl", 0b01>; defm FMLSL_VG2_M2ZZ : sme2_fp_mla_long_array_vg2_single<"fmlsl", 0b01>;
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
defm UMLSL_MZZI : sme2_mla_long_array_index<"umlsl", 0b11, 0b11>; defm UMLSL_MZZI : sme2_mla_long_array_index<"umlsl", 0b11, 0b11>;
defm UMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlsl", 0b11>; defm UMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlsl", 0b11>;
defm UMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlsl", 0b11>; defm UMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlsl", 0b11>;
defm UMLSL_MZZ : sme2_mla_long_array_single<"umlsl",0b01, 0b11>; defm UMLSL_MZZ : sme2_mla_long_array_single<"umlsl",0b01, 0b11>;
defm UMLSL_VG2_M2ZZ : sme2_int_mla_long_array_vg2_single<"umlsl", 0b11>; defm UMLSL_VG2_M2ZZ : sme2_int_mla_long_array_vg2_single<"umlsl", 0b11>;
defm UMLSL_VG4_M4ZZ : sme2_int_mla_long_array_vg4_single<"umlsl", 0b11>; defm UMLSL_VG4_M4ZZ : sme2_int_mla_long_array_vg4_single<"umlsl", 0b11>;
defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl", 0b11>; defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl", 0b11>;
defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl", 0b11>; defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl", 0b11>;
def FCVT_Z2Z_StoH : sme2_cvt_vg2_single<"fcvt", 0b00, 0b00>;
def FCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"fcvtn", 0b01, 0b00>;
def BFCVT_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvt", 0b10, 0b00>;
def BFCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvtn", 0b11, 0b00>;
def SQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvt", 0b00, 0b11>;
def UQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"uqcvt", 0b01, 0b11>;
def SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b10, 0b11>;
defm SQCVT_Z4Z : sme2_int_cvt_vg4_single<"sqcvt", 0b000>;
defm UQCVT_Z4Z : sme2_int_cvt_vg4_single<"uqcvt", 0b001>;
defm SQCVTU_Z4Z : sme2_int_cvt_vg4_single<"sqcvtu", 0b100>;
defm SQCVTN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtn", 0b010>;
defm SQCVTUN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtun", 0b110>;
defm UQCVTN_Z4Z : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>;
} }
let Predicates = [HasSME2, HasSMEI16I64] in { let Predicates = [HasSME2, HasSMEI16I64] in {
defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>; defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>; defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>; defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>; defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;
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llvm/lib/Target/AArch64/SMEInstrFormats.td

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} }
multiclass sme2_int_mla_long_array_vg4_multi<string mnemonic, bits<2> op> { multiclass sme2_int_mla_long_array_vg4_multi<string mnemonic, bits<2> op> {
def _S : sme2_mla_long_array_vg4_multi<mnemonic, 0b11, op>; def _S : sme2_mla_long_array_vg4_multi<mnemonic, 0b11, op>;
def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm2], $Zn, $Zm", def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm2], $Zn, $Zm",
(!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm2, ZZZZ_h_mul_r:$Zn, ZZZZ_h_mul_r:$Zm), 0>; (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm2, ZZZZ_h_mul_r:$Zn, ZZZZ_h_mul_r:$Zm), 0>;
} }
//===----------------------------------------------------------------------===//
// SME2 multi-vec INT/ FP down convert
class sme2_cvt_vg2_single<string mnemonic, bits<2> op, bits<2> is_int>
: I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
bits<4> Zn;
bits<5> Zd;
let Inst{31-23} = 0b110000010;
let Inst{22} = op{1};
let Inst{21-18} = 0b1000;
let Inst{17-16} = is_int;
let Inst{15-10} = 0b111000;
let Inst{9-6} = Zn;
let Inst{5} = op{0};
let Inst{4-0} = Zd;
}
class sme2_cvt_vg4_single<bit sz,bits<3> op, ZPRRegOp zpr_ty, RegisterOperand vector_ty,
string mnemonic>
: I<(outs zpr_ty:$Zd), (ins vector_ty:$Zn),
mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
bits<3> Zn;
bits<5> Zd;
let Inst{31-24} = 0b11000001;
let Inst{23} = sz;
let Inst{22} = op{2};
let Inst{21-16} = 0b110011;
let Inst{15-10} = 0b111000;
let Inst{9-7} = Zn;
let Inst{6-5} = op{1-0};
let Inst{4-0} = Zd;
}
multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> {
def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
}

llvm/test/MC/AArch64/SME2/bfcvt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
bfcvt z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: bfcvt z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bfcvt z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: bfcvt z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
bfcvt z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bfcvt z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bfcvt z0.h, {z0.h-z1.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: bfcvt z0.h, {z0.h-z1.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/bfcvt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
bfcvt z0.h, {z0.s, z1.s} // 11000001-01100000-11100000-00000000
// CHECK-INST: bfcvt z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e000 <unknown>
bfcvt z21.h, {z10.s, z11.s} // 11000001-01100000-11100001-01010101
// CHECK-INST: bfcvt z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e155 <unknown>
bfcvt z23.h, {z12.s, z13.s} // 11000001-01100000-11100001-10010111
// CHECK-INST: bfcvt z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0xe1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e197 <unknown>
bfcvt z31.h, {z30.s, z31.s} // 11000001-01100000-11100011-11011111
// CHECK-INST: bfcvt z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e3df <unknown>

llvm/test/MC/AArch64/SME2/bfcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
bfcvtn z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: bfcvtn z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bfcvtn z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fcvtn z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
bfcvtn z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bfcvtn z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bfcvtn z0.h, {z0.h-z1.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: bfcvtn z0.h, {z0.h-z1.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/bfcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
bfcvtn z0.h, {z0.s, z1.s} // 11000001-01100000-11100000-00100000
// CHECK-INST: bfcvtn z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x20,0xe0,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e020 <unknown>
bfcvtn z21.h, {z10.s, z11.s} // 11000001-01100000-11100001-01110101
// CHECK-INST: bfcvtn z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x75,0xe1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e175 <unknown>
bfcvtn z23.h, {z12.s, z13.s} // 11000001-01100000-11100001-10110111
// CHECK-INST: bfcvtn z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0xb7,0xe1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e1b7 <unknown>
bfcvtn z31.h, {z30.s, z31.s} // 11000001-01100000-11100011-11111111
// CHECK-INST: bfcvtn z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xff,0xe3,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160e3ff <unknown>

llvm/test/MC/AArch64/SME2/fcvt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
fcvt z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvt z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fcvt z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
fcvt z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvt z0.h, {z0.h-z1.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.h, {z0.h-z1.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fcvt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fcvt z0.h, {z0.s, z1.s} // 11000001-00100000-11100000-00000000
// CHECK-INST: fcvt z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e000 <unknown>
fcvt z21.h, {z10.s, z11.s} // 11000001-00100000-11100001-01010101
// CHECK-INST: fcvt z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e155 <unknown>
fcvt z23.h, {z12.s, z13.s} // 11000001-00100000-11100001-10010111
// CHECK-INST: fcvt z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0xe1,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e197 <unknown>
fcvt z31.h, {z30.s, z31.s} // 11000001-00100000-11100011-11011111
// CHECK-INST: fcvt z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e3df <unknown>

llvm/test/MC/AArch64/SME2/fcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
fcvtn z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtn z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtn z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fcvtn z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
fcvtn z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtn z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtn z0.h, {z0.h-z1.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtn z0.h, {z0.h-z1.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fcvtn z0.h, {z0.s, z1.s} // 11000001-00100000-11100000-00100000
// CHECK-INST: fcvtn z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x20,0xe0,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e020 <unknown>
fcvtn z21.h, {z10.s, z11.s} // 11000001-00100000-11100001-01110101
// CHECK-INST: fcvtn z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x75,0xe1,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e175 <unknown>
fcvtn z23.h, {z12.s, z13.s} // 11000001-00100000-11100001-10110111
// CHECK-INST: fcvtn z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0xb7,0xe1,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e1b7 <unknown>
fcvtn z31.h, {z30.s, z31.s} // 11000001-00100000-11100011-11111111
// CHECK-INST: fcvtn z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xff,0xe3,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120e3ff <unknown>

llvm/test/MC/AArch64/SME2/sqcvt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvt z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvt z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvt z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
// CHECK-NEXT: sqcvt z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvt z0.h, {z1.d-z2.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvt z0.h, {z1.d-z2.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqcvt z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqcvt z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqcvt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvt z0.h, {z0.s, z1.s} // 11000001-00100011-11100000-00000000
// CHECK-INST: sqcvt z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e000 <unknown>
sqcvt z21.h, {z10.s, z11.s} // 11000001-00100011-11100001-01010101
// CHECK-INST: sqcvt z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e155 <unknown>
sqcvt z23.h, {z12.s, z13.s} // 11000001-00100011-11100001-10010111
// CHECK-INST: sqcvt z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0xe1,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e197 <unknown>
sqcvt z31.h, {z30.s, z31.s} // 11000001-00100011-11100011-11011111
// CHECK-INST: sqcvt z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e3df <unknown>
sqcvt z0.b, {z0.s - z3.s} // 11000001-00110011-11100000-00000000
// CHECK-INST: sqcvt z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x00,0xe0,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e000 <unknown>
sqcvt z21.b, {z8.s - z11.s} // 11000001-00110011-11100001-00010101
// CHECK-INST: sqcvt z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x15,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e115 <unknown>
sqcvt z23.b, {z12.s - z15.s} // 11000001-00110011-11100001-10010111
// CHECK-INST: sqcvt z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0x97,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e197 <unknown>
sqcvt z31.b, {z28.s - z31.s} // 11000001-00110011-11100011-10011111
// CHECK-INST: sqcvt z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0x9f,0xe3,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e39f <unknown>
sqcvt z0.h, {z0.d - z3.d} // 11000001-10110011-11100000-00000000
// CHECK-INST: sqcvt z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x00,0xe0,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e000 <unknown>
sqcvt z21.h, {z8.d - z11.d} // 11000001-10110011-11100001-00010101
// CHECK-INST: sqcvt z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x15,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e115 <unknown>
sqcvt z23.h, {z12.d - z15.d} // 11000001-10110011-11100001-10010111
// CHECK-INST: sqcvt z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0x97,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e197 <unknown>
sqcvt z31.h, {z28.d - z31.d} // 11000001-10110011-11100011-10011111
// CHECK-INST: sqcvt z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0x9f,0xe3,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e39f <unknown>

llvm/test/MC/AArch64/SME2/sqcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvtn z0.h, {z0.d-z4.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqcvtn z0.h, {z0.d-z4.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtn z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
// CHECK-NEXT: sqcvtn z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqcvtn z0.h, {z0.s-z3.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtn z0.h, {z0.s-z3.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvtn z0.b, {z0.s - z3.s} // 11000001-00110011-11100000-01000000
// CHECK-INST: sqcvtn z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x40,0xe0,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e040 <unknown>
sqcvtn z21.b, {z8.s - z11.s} // 11000001-00110011-11100001-01010101
// CHECK-INST: sqcvtn z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e155 <unknown>
sqcvtn z23.b, {z12.s - z15.s} // 11000001-00110011-11100001-11010111
// CHECK-INST: sqcvtn z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0xd7,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e1d7 <unknown>
sqcvtn z31.b, {z28.s - z31.s} // 11000001-00110011-11100011-11011111
// CHECK-INST: sqcvtn z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e3df <unknown>
sqcvtn z0.h, {z0.d - z3.d} // 11000001-10110011-11100000-01000000
// CHECK-INST: sqcvtn z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x40,0xe0,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e040 <unknown>
sqcvtn z21.h, {z8.d - z11.d} // 11000001-10110011-11100001-01010101
// CHECK-INST: sqcvtn z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x55,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e155 <unknown>
sqcvtn z23.h, {z12.d - z15.d} // 11000001-10110011-11100001-11010111
// CHECK-INST: sqcvtn z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0xd7,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e1d7 <unknown>
sqcvtn z31.h, {z28.d - z31.d} // 11000001-10110011-11100011-11011111
// CHECK-INST: sqcvtn z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0xdf,0xe3,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e3df <unknown>

llvm/test/MC/AArch64/SME2/sqcvtu-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvtu z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtu z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtu z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
// CHECK-NEXT: sqcvtu z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtu z0.h, {z1.d-z2.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtu z0.h, {z1.d-z2.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqcvtu z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqcvtu z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqcvtu.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvtu z0.h, {z0.s, z1.s} // 11000001-01100011-11100000-00000000
// CHECK-INST: sqcvtu z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x63,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c163e000 <unknown>
sqcvtu z21.h, {z10.s, z11.s} // 11000001-01100011-11100001-01010101
// CHECK-INST: sqcvtu z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x63,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c163e155 <unknown>
sqcvtu z23.h, {z12.s, z13.s} // 11000001-01100011-11100001-10010111
// CHECK-INST: sqcvtu z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0xe1,0x63,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c163e197 <unknown>
sqcvtu z31.h, {z30.s, z31.s} // 11000001-01100011-11100011-11011111
// CHECK-INST: sqcvtu z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x63,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c163e3df <unknown>
sqcvtu z0.b, {z0.s - z3.s} // 11000001-01110011-11100000-00000000
// CHECK-INST: sqcvtu z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x00,0xe0,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e000 <unknown>
sqcvtu z21.b, {z8.s - z11.s} // 11000001-01110011-11100001-00010101
// CHECK-INST: sqcvtu z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x15,0xe1,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e115 <unknown>
sqcvtu z23.b, {z12.s - z15.s} // 11000001-01110011-11100001-10010111
// CHECK-INST: sqcvtu z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0x97,0xe1,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e197 <unknown>
sqcvtu z31.b, {z28.s - z31.s} // 11000001-01110011-11100011-10011111
// CHECK-INST: sqcvtu z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0x9f,0xe3,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e39f <unknown>
sqcvtu z0.h, {z0.d - z3.d} // 11000001-11110011-11100000-00000000
// CHECK-INST: sqcvtu z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x00,0xe0,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e000 <unknown>
sqcvtu z21.h, {z8.d - z11.d} // 11000001-11110011-11100001-00010101
// CHECK-INST: sqcvtu z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x15,0xe1,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e115 <unknown>
sqcvtu z23.h, {z12.d - z15.d} // 11000001-11110011-11100001-10010111
// CHECK-INST: sqcvtu z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0x97,0xe1,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e197 <unknown>
sqcvtu z31.h, {z28.d - z31.d} // 11000001-11110011-11100011-10011111
// CHECK-INST: sqcvtu z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0x9f,0xe3,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e39f <unknown>

llvm/test/MC/AArch64/SME2/sqcvtun-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvtun z0.h, {z0.d-z4.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqcvtun z0.h, {z0.d-z4.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtun z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqcvtun z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqcvtun z0.h, {z0.s-z3.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtun z0.h, {z0.s-z3.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqcvtun.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvtun z0.b, {z0.s - z3.s} // 11000001-01110011-11100000-01000000
// CHECK-INST: sqcvtun z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x40,0xe0,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e040 <unknown>
sqcvtun z21.b, {z8.s - z11.s} // 11000001-01110011-11100001-01010101
// CHECK-INST: sqcvtun z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x55,0xe1,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e155 <unknown>
sqcvtun z23.b, {z12.s - z15.s} // 11000001-01110011-11100001-11010111
// CHECK-INST: sqcvtun z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0xd7,0xe1,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e1d7 <unknown>
sqcvtun z31.b, {z28.s - z31.s} // 11000001-01110011-11100011-11011111
// CHECK-INST: sqcvtun z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0xdf,0xe3,0x73,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c173e3df <unknown>
sqcvtun z0.h, {z0.d - z3.d} // 11000001-11110011-11100000-01000000
// CHECK-INST: sqcvtun z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x40,0xe0,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e040 <unknown>
sqcvtun z21.h, {z8.d - z11.d} // 11000001-11110011-11100001-01010101
// CHECK-INST: sqcvtun z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x55,0xe1,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e155 <unknown>
sqcvtun z23.h, {z12.d - z15.d} // 11000001-11110011-11100001-11010111
// CHECK-INST: sqcvtun z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0xd7,0xe1,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e1d7 <unknown>
sqcvtun z31.h, {z28.d - z31.d} // 11000001-11110011-11100011-11011111
// CHECK-INST: sqcvtun z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0xdf,0xe3,0xf3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f3e3df <unknown>

llvm/test/MC/AArch64/SME2/uqcvt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvt z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvt z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvt z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
// CHECK-NEXT: sqcvt z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvt z0.h, {z1.d-z2.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvt z0.h, {z1.d-z2.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqcvt z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqcvt z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/uqcvt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqcvt z0.h, {z0.s, z1.s} // 11000001-00100011-11100000-00100000
// CHECK-INST: uqcvt z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x20,0xe0,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e020 <unknown>
uqcvt z21.h, {z10.s, z11.s} // 11000001-00100011-11100001-01110101
// CHECK-INST: uqcvt z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x75,0xe1,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e175 <unknown>
uqcvt z23.h, {z12.s, z13.s} // 11000001-00100011-11100001-10110111
// CHECK-INST: uqcvt z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0xb7,0xe1,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e1b7 <unknown>
uqcvt z31.h, {z30.s, z31.s} // 11000001-00100011-11100011-11111111
// CHECK-INST: uqcvt z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xff,0xe3,0x23,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c123e3ff <unknown>
uqcvt z0.b, {z0.s - z3.s} // 11000001-00110011-11100000-00100000
// CHECK-INST: uqcvt z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x20,0xe0,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e020 <unknown>
uqcvt z21.b, {z8.s - z11.s} // 11000001-00110011-11100001-00110101
// CHECK-INST: uqcvt z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x35,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e135 <unknown>
uqcvt z23.b, {z12.s - z15.s} // 11000001-00110011-11100001-10110111
// CHECK-INST: uqcvt z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0xb7,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e1b7 <unknown>
uqcvt z31.b, {z28.s - z31.s} // 11000001-00110011-11100011-10111111
// CHECK-INST: uqcvt z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0xbf,0xe3,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e3bf <unknown>
uqcvt z0.h, {z0.d - z3.d} // 11000001-10110011-11100000-00100000
// CHECK-INST: uqcvt z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x20,0xe0,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e020 <unknown>
uqcvt z21.h, {z8.d - z11.d} // 11000001-10110011-11100001-00110101
// CHECK-INST: uqcvt z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x35,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e135 <unknown>
uqcvt z23.h, {z12.d - z15.d} // 11000001-10110011-11100001-10110111
// CHECK-INST: uqcvt z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0xb7,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e1b7 <unknown>
uqcvt z31.h, {z28.d - z31.d} // 11000001-10110011-11100011-10111111
// CHECK-INST: uqcvt z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0xbf,0xe3,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e3bf <unknown>

llvm/test/MC/AArch64/SME2/uqcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
uqcvtn z0.h, {z0.d-z4.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: uqcvtn z0.h, {z0.d-z4.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqcvtn z0.b, {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
// CHECK-NEXT: uqcvtn z0.b, {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
uqcvtn z0.h, {z0.s-z3.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqcvtn z0.h, {z0.s-z3.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/uqcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqcvtn z0.b, {z0.s - z3.s} // 11000001-00110011-11100000-01100000
// CHECK-INST: uqcvtn z0.b, { z0.s - z3.s }
// CHECK-ENCODING: [0x60,0xe0,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e060 <unknown>
uqcvtn z21.b, {z8.s - z11.s} // 11000001-00110011-11100001-01110101
// CHECK-INST: uqcvtn z21.b, { z8.s - z11.s }
// CHECK-ENCODING: [0x75,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e175 <unknown>
uqcvtn z23.b, {z12.s - z15.s} // 11000001-00110011-11100001-11110111
// CHECK-INST: uqcvtn z23.b, { z12.s - z15.s }
// CHECK-ENCODING: [0xf7,0xe1,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e1f7 <unknown>
uqcvtn z31.b, {z28.s - z31.s} // 11000001-00110011-11100011-11111111
// CHECK-INST: uqcvtn z31.b, { z28.s - z31.s }
// CHECK-ENCODING: [0xff,0xe3,0x33,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c133e3ff <unknown>
uqcvtn z0.h, {z0.d - z3.d} // 11000001-10110011-11100000-01100000
// CHECK-INST: uqcvtn z0.h, { z0.d - z3.d }
// CHECK-ENCODING: [0x60,0xe0,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e060 <unknown>
uqcvtn z21.h, {z8.d - z11.d} // 11000001-10110011-11100001-01110101
// CHECK-INST: uqcvtn z21.h, { z8.d - z11.d }
// CHECK-ENCODING: [0x75,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e175 <unknown>
uqcvtn z23.h, {z12.d - z15.d} // 11000001-10110011-11100001-11110111
// CHECK-INST: uqcvtn z23.h, { z12.d - z15.d }
// CHECK-ENCODING: [0xf7,0xe1,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e1f7 <unknown>
uqcvtn z31.h, {z28.d - z31.d} // 11000001-10110011-11100011-11111111
// CHECK-INST: uqcvtn z31.h, { z28.d - z31.d }
// CHECK-ENCODING: [0xff,0xe3,0xb3,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b3e3ff <unknown>