[RISCV] Optimize 2x SELECT for floating-point types

[liaolucy]

Summary

Including the following opcode:
Select_FPR16_Using_CC_GPR
Select_FPR32_Using_CC_GPR
Select_FPR64_Using_CC_GPR

[liaolucy]

The asm of testcase before this patch:

        auipc   a0, %pcrel_hi(.LCPI0_0)
        addi    a0, a0, %pcrel_lo(.LBB0_5)
        flw     ft0, 0(a0)
        fmv.w.x ft1, zero
        flt.s   a1, fa0, ft1
        flt.s   a0, ft0, fa0
        beqz    a1, .LBB0_3
# %bb.1:                                # %entry
        beqz    a0, .LBB0_4
.LBB0_2:                                # %entry
        fmv.s   fa0, ft0
        ret
.LBB0_3:                                # %entry
        fmv.s   ft1, fa0
        bnez    a0, .LBB0_2
.LBB0_4:                                # %entry
        fmv.s   ft0, ft1
        fmv.s   fa0, ft0
        ret

after this patch :

# %bb.0:                                # %entry
        fmv.w.x ft0, zero
        flt.s   a0, fa0, ft0
        bnez    a0, .LBB0_3
# %bb.1:                                # %entry
.LBB0_4:                                # %entry
                                        # Label of block must be emitted
        auipc   a0, %pcrel_hi(.LCPI0_0)
        addi    a0, a0, %pcrel_lo(.LBB0_4)
        flw     ft0, 0(a0)
        flt.s   a0, ft0, fa0
        bnez    a0, .LBB0_3
# %bb.2:                                # %entry
        fmv.s   ft0, fa0
.LBB0_3:                                # %entry
        fmv.s   fa0, ft0
        ret

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9892

Variable names should start with a capital letter

9899

Why do we need an explicit PseudoBR? Can't we let it fallthrough?

9969

Should this use next_nodbg to increment?

9971

Shouldn't we be checking NextMIIt != BB->end() before checking the opcode of NextMIIt?

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

537

Drop dso_local and local_unnamed_addr and #0

[liaolucy]

address craig.topper's comments and thanks

[craig.topper]

LGTM

[dcaballe]

Hi!

This commit is causing a correctness regression in one of the ML models in IREE. Please, find attach the LLVM IR after Codegen Prepare. Hopefully, you can easily identify where this change is triggering.
To reproduce: llc bug.ll -mcpu=generic-rv64 -mattr=+m,+a,+f,+d,+c -target-abi=lp64d. Please, note that no +v is provided. Could we please consider a revert while this is being investigated?

Thanks,
Diego

bug.ll1 MBDownload

[liaolucy]

In D127871#3634472, @dcaballe wrote:

Hi!

This commit is causing a correctness regression in one of the ML models in IREE. Please, find attach the LLVM IR after Codegen Prepare. Hopefully, you can easily identify where this change is triggering.
To reproduce: llc bug.ll -mcpu=generic-rv64 -mattr=+m,+a,+f,+d,+c -target-abi=lp64d. Please, note that no +v is provided. Could we please consider a revert while this is being investigated?

Thanks,
Diego

bug.ll1 MBDownload

@dcaballe Can you provide a file that can be compiled and run? Help me to debug.

[dcaballe]

I was able to reduce the test case to:

target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"                                                                                                                                
target triple = "riscv64-unknown-unknown-eabi-elf"                                                                                                                                          
                                                                                                                                                                                            
; Function Attrs: nofree nosync nounwind                                                                                                                                                    
define internal i32 @main_dispatch_72(i8* %i5, <2 x float> %i44, <2 x float> %i61, <2 x i32> %i65) {                                                                                        
bbi:                                                                                                                                                                                        
  %i45 = fcmp uno <2 x float> %i44, zeroinitializer                                                                                                                                         
  %i62 = fcmp oeq <2 x float> %i44, <float 0xFFF0000000000000, float 0xFFF0000000000000>                                                                                                    
  %i63 = fcmp oeq <2 x float> %i44, <float 0x7FF0000000000000, float 0x7FF0000000000000>                                                                                                    
  %i64 = fcmp ogt <2 x float> %i44, zeroinitializer                                                                                                                                         
  %i66 = icmp ult <2 x i32> %i65, <i32 255, i32 255>                                                                                                                                        
  %i67 = select <2 x i1> %i64, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> <float 0x3810000000000000, float 0x3810000000000000>                           
  %i68 = select <2 x i1> %i66, <2 x float> %i61, <2 x float> %i67                                                                                                                           
  %i69 = select <2 x i1> %i63, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> %i68                                                                           
  %i70 = select <2 x i1> %i62, <2 x float> zeroinitializer, <2 x float> %i69                                                                                                                
  %i71 = select <2 x i1> %i45, <2 x float> %i44, <2 x float> %i70                                                                                                                           
  %i72 = bitcast i8* %i5 to <2 x float>*                                                                                                                                                    
  store <2 x float> %i71, <2 x float>* %i72, align 64                                                                                                                                       
  ret i32 0                                                                                                                                                                                 
}

Your code should trigger with llc bug.ll -mcpu=generic-rv64 -mattr=+m,+a,+f,+d,+c -target-abi=lp64d.

It looks like it's a case where your transformation is applied multiple times on the output produced by previous instances.

I'll revert this commit while this is being investigated.

Thanks,
Diego

[craig.topper]

I think the expanded branches are emitted in the wrong order. The condition for the last Select_FPR32_Using_CC_GPR needs to be checked first.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

I think we also need to make sure the condition for the second select doesn't use the output from the first select.

[liaolucy]

In D127871#3637493, @craig.topper wrote:

I think the expanded branches are emitted in the wrong order. The condition for the last Select_FPR32_Using_CC_GPR needs to be checked first.

Thanks, Craig. I dump all select, The middle three pairs of instructions can be optimized

  %25:fpr32 = Select_FPR32_Using_CC_GPR killed %21:gpr, %24:gpr, 1, %16:fpr32, %23:fpr32
  %26:fpr32 = Select_FPR32_Using_CC_GPR killed %20:gpr, %24:gpr, 1, %16:fpr32, %23:fpr32
  %28:fpr32 = Select_FPR32_Using_CC_GPR killed %8:gpr, %27:gpr, 4, %4:fpr32, killed %26:fpr32

optimize1 
 1.1 %29:fpr32 = Select_FPR32_Using_CC_GPR killed %7:gpr, %27:gpr, 4, %3:fpr32, killed %25:fpr3
 2.1 %30:fpr32 = Select_FPR32_Using_CC_GPR killed %18:gpr, %24:gpr, 1, %16:fpr32, killed %29:fpr32
optimize2
 1.2 %31:fpr32 = Select_FPR32_Using_CC_GPR killed %17:gpr, %24:gpr, 1, %16:fpr32, killed %28:fpr32
 2.2 %32:fpr32 = Select_FPR32_Using_CC_GPR killed %14:gpr, %24:gpr, 1, %19:fpr32, killed %31:fpr32
optimize3
 1.3 %33:fpr32 = Select_FPR32_Using_CC_GPR killed %13:gpr, %24:gpr, 1, %19:fpr32, killed %30:fpr32
 2.3 %34:fpr32 = Select_FPR32_Using_CC_GPR killed %10:gpr, %24:gpr, 0, %1:fpr32, killed %33:fpr32

  %35:fpr32 = Select_FPR32_Using_CC_GPR killed %9:gpr, %24:gpr, 0, %2:fpr32, killed %32:fpr32

I think we should check select1-rs2 == select2-rs2, then 1.1 and 2.1 can not be optimized. I will update patch later

[craig.topper]

In D127871#3637829, @liaolucy wrote:

In D127871#3637493, @craig.topper wrote:

I think the expanded branches are emitted in the wrong order. The condition for the last Select_FPR32_Using_CC_GPR needs to be checked first.

Thanks, Craig. I dump all select, The middle three pairs of instructions can be optimized

  %25:fpr32 = Select_FPR32_Using_CC_GPR killed %21:gpr, %24:gpr, 1, %16:fpr32, %23:fpr32
  %26:fpr32 = Select_FPR32_Using_CC_GPR killed %20:gpr, %24:gpr, 1, %16:fpr32, %23:fpr32
  %28:fpr32 = Select_FPR32_Using_CC_GPR killed %8:gpr, %27:gpr, 4, %4:fpr32, killed %26:fpr32

optimize1 
 1.1 %29:fpr32 = Select_FPR32_Using_CC_GPR killed %7:gpr, %27:gpr, 4, %3:fpr32, killed %25:fpr3
 2.1 %30:fpr32 = Select_FPR32_Using_CC_GPR killed %18:gpr, %24:gpr, 1, %16:fpr32, killed %29:fpr32
optimize2
 1.2 %31:fpr32 = Select_FPR32_Using_CC_GPR killed %17:gpr, %24:gpr, 1, %16:fpr32, killed %28:fpr32
 2.2 %32:fpr32 = Select_FPR32_Using_CC_GPR killed %14:gpr, %24:gpr, 1, %19:fpr32, killed %31:fpr32
optimize3
 1.3 %33:fpr32 = Select_FPR32_Using_CC_GPR killed %13:gpr, %24:gpr, 1, %19:fpr32, killed %30:fpr32
 2.3 %34:fpr32 = Select_FPR32_Using_CC_GPR killed %10:gpr, %24:gpr, 0, %1:fpr32, killed %33:fpr32

  %35:fpr32 = Select_FPR32_Using_CC_GPR killed %9:gpr, %24:gpr, 0, %2:fpr32, killed %32:fpr32

I think we should check select1-rs2 == select2-rs2, then 1.1 and 2.1 can not be optimized. I will update patch later

I dont' think checking select1-rs2 == select2-rs2 solves the problem. When the condition of the second select is true, the true value of that select has priority. That means when the select2 condition is true, the select1 condition matter. The patch is trying to prioritize one of the compares to skip the other the other. That means you need to check the select2 condition first to maintain the priority.

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

I'm still confused. You mean, should I need to add: Next->getOperand(4).getReg() != MI.getOperand(0).getReg() ?

But, the assembly of the bug.ll file has not changed.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

I was theorizing another possible bug. If either rs1 or rs2 of the second select is the result of the first select. Meaning one of the compare operands is also the false operand. It’s not safe to do the optimization. Is that already protected?

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

If either rs1 or rs2 of the second select is the result of the first select.

This condition does not hold.

eg: fpr32 = Select_FPR32_Using_CC_GPR killed %13:gpr, %24:gpr, 1, %19:fpr32, killed %30:fpr32

rs1 and rs2 are gpr, but dst is fpr.

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

If either rs1 or rs2 of the second select is the result of the first select.

This condition does not hold.

eg: fpr32 = Select_FPR32_Using_CC_GPR killed %13:gpr, %24:gpr, 1, %19:fpr32, killed %30:fpr32

rs1 and rs2 are gpr, but dst is fpr,

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9969

You're right. I forgot this was FP only.

[dcaballe]

Happy to run any tentative fix that you may have on the full model to know if it fixes the problem.

[liaolucy]

Try to fix according to my guess. @dcaballe Could you help test it? If it can't be solved, I may need to spend more time to analyze.

[dcaballe]

It works! I must have messed up the test when trimming it. I'm attaching the whole function for your reference. Your code was invoked four times on this function with the previous version of the code. It's only invoked twice with the fixed one.

function.ll8 KBDownload

Thanks!

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9971

I don't understand the new check. Why was it wrong to optimize 1.1 and 2.1 in the failed case?

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9971

Yesterday, I saw that x86 has this check.

// CMOV ((CMOV F, T, cc1), T, cc2) is checked here and handled by a separate
// function - EmitLoweredCascadedSelect

// This checks for case 2, but only do this if we didn't already find
// case 1, as indicated by LastCMOV == MI.
if (LastCMOV == &MI && NextMIIt != ThisMBB->end() &&
    NextMIIt->getOpcode() == MI.getOpcode() &&
    NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
    NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
    NextMIIt->getOperand(1).isKill()) {
  return EmitLoweredCascadedSelect(MI, *NextMIIt, ThisMBB);
}

Try to understand：
1.1 %29:fpr32 = Select_FPR32_Using_CC_GPR killed %7:gpr, %27:gpr, 4, %3:fpr32, killed %25:fpr3
2.1 %30:fpr32 = Select_FPR32_Using_CC_GPR killed %18:gpr, %24:gpr, 1, %16:fpr32, killed %29:fpr32

%7 (a), %27 (b)
%18 (c), %24 (d)
Eg:

a=b , c=d,
 a=b , c!=d
 a!=b, c=d,
 a!=b, c!=d

b=d:

%7 (a), %27 (b), 
%18 (c), %24 (b) 
a=b,  c=b     a=b=c
a=b,  c!=b 
                a!= c (optimize)   
a!=b, c=b
a!=b, c!=b   a!=b!=c

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9971

X86 has the CMP done has a separate instruction that writes EFLAGS. The getOperand(2) check for X86 is making sure that the EFLAGS come from the same CMP instruction. RISC-V has does the comparison has part of the branch so it's different.

For
1.1 %29:fpr32 = Select_FPR32_Using_CC_GPR killed %7:gpr, %27:gpr, 4, %3:fpr32, killed %25:fpr3
2.1 %30:fpr32 = Select_FPR32_Using_CC_GPR killed %18:gpr, %24:gpr, 1, %16:fpr32, killed %29:fpr32

The original code is
(%18 != %24) ? %16 : ((%7 < %27) ? %3 : %25)

The transform this patch is trying to do needs to be

bb1:
  BNE %18, %24, bb4
bb2:
  BLTU %7, %27, bb4
bb3:
  // fallthrough
bb4
  phi %16, bb1, %3, bb2, %25 bb3

The condition of the second select needs to be checked first.

[liaolucy]

address craig.topper's comments and thanks

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static MachineBasicBlock *emitQuietFCMP(MachineInstr &MI, MachineBasicBlock *BB,
   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
     MIB2->setFlag(MachineInstr::MIFlag::NoFPExcept);
 
   // Erase the pseudoinstruction.
   MI.eraseFromParent();
   return BB;
 }
 
+static MachineBasicBlock *
+EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
+                          MachineBasicBlock *ThisMBB,
+                          const RISCVSubtarget &Subtarget) {
+  // Select_FPRX_ (rs1, rs2, imm, rs4, (Select_FPRX_ rs1, rs2, imm, rs4, rs5)
+  // Without this, custom-inserter would have generated:
+  //
+  //   A
+  //   | \
+  //   |  B
+  //   | /
+  //   C
+  //   | \
+  //   |  D
+  //   | /
+  //   E
+  //
+  // A: X = ...; Y = ...
+  // B: empty
+  // C: Z = PHI [X, A], [Y, B]
+  // D: empty
+  // E: PHI [X, C], [Z, D]
+  //
+  // If we lower both Select_FPRX_ in a single step, we can instead generate:
+  //
+  //   A
+  //   | \
+  //   |  C
+  //   | /|
+  //   |/ |
+  //   |  |
+  //   |  D
+  //   | /
+  //   E
+  //
+  // A: X = ...; Y = ...
+  // D: empty
+  // E: PHI [X, A], [X, C], [Y, D]
+
+  const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
+  const DebugLoc &DL = First.getDebugLoc();
+  const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
+  MachineFunction *F = ThisMBB->getParent();
+  MachineBasicBlock *FirstMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SecondMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineFunction::iterator It = ++ThisMBB->getIterator();
+  F->insert(It, FirstMBB);
+  F->insert(It, SecondMBB);
+  F->insert(It, SinkMBB);
+
+  // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
+  SinkMBB->splice(SinkMBB->begin(), ThisMBB,
+                  std::next(MachineBasicBlock::iterator(First)),
+                  ThisMBB->end());
+  SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
+
+  // Fallthrough block for ThisMBB.
+  ThisMBB->addSuccessor(FirstMBB);
+  // Fallthrough block for FirstMBB.
+  FirstMBB->addSuccessor(SecondMBB);
+  ThisMBB->addSuccessor(SinkMBB);
+  FirstMBB->addSuccessor(SinkMBB);
+  // This is fallthrough.
+  SecondMBB->addSuccessor(SinkMBB);
+
+  auto FirstCC = static_cast<RISCVCC::CondCode>(First.getOperand(3).getImm());
+  Register FLHS = First.getOperand(1).getReg();
+  Register FRHS = First.getOperand(2).getReg();
+  // Insert appropriate branch.
+  BuildMI(FirstMBB, DL, TII.getBrCond(FirstCC))
+      .addReg(FLHS)
+      .addReg(FRHS)
+      .addMBB(SinkMBB);
+
+  Register SLHS = Second.getOperand(1).getReg();
+  Register SRHS = Second.getOperand(2).getReg();
+  Register Op1Reg4 = First.getOperand(4).getReg();
+  Register Op1Reg5 = First.getOperand(5).getReg();
+
+  auto SecondCC = static_cast<RISCVCC::CondCode>(Second.getOperand(3).getImm());
+  // Insert appropriate branch.
+  BuildMI(ThisMBB, DL, TII.getBrCond(SecondCC))
+      .addReg(SLHS)
+      .addReg(SRHS)
+      .addMBB(SinkMBB);
+
+  Register DestReg = Second.getOperand(0).getReg();
+  Register Op2Reg4 = Second.getOperand(4).getReg();
+  BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII.get(RISCV::PHI), DestReg)
+      .addReg(Op2Reg4)
+      .addMBB(ThisMBB)
+      .addReg(Op1Reg4)
+      .addMBB(FirstMBB)
+      .addReg(Op1Reg5)
+      .addMBB(SecondMBB);
+
+  // Now remove the Select_FPRX_s.
+  First.eraseFromParent();
+  Second.eraseFromParent();
+  return SinkMBB;
+}
+
 static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
                                            MachineBasicBlock *BB,
                                            const RISCVSubtarget &Subtarget) {
   // To "insert" Select_* instructions, we actually have to insert the triangle
   // control-flow pattern.  The incoming instructions know the destination vreg
   // to set, the condition code register to branch on, the true/false values to
   // select between, and the condcode to use to select the appropriate branch.
   //
static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   // instructions meet some requirements we deem safe:
   // - They are debug instructions. Otherwise,
   // - They do not have side-effects, do not access memory and their inputs do
   //   not depend on the results of the select pseudo-instructions.
   // The TrueV/FalseV operands of the selects cannot depend on the result of
   // previous selects in the sequence.
   // These conditions could be further relaxed. See the X86 target for a
   // related approach and more information.
+  //
+  // Select_FPRX_ (rs1, rs2, imm, rs4, (Select_FPRX_ rs1, rs2, imm, rs4, rs5))
+  // is checked here and handled by a separate function -
+  // EmitLoweredCascadedSelect.
   Register LHS = MI.getOperand(1).getReg();
   Register RHS = MI.getOperand(2).getReg();
   auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
 
   SmallVector<MachineInstr *, 4> SelectDebugValues;
   SmallSet<Register, 4> SelectDests;
   SelectDests.insert(MI.getOperand(0).getReg());
 
   MachineInstr *LastSelectPseudo = &MI;
+  auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
+  if (MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR && Next != BB->end() &&
+      Next->getOpcode() == MI.getOpcode() &&
+      Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
+      Next->getOperand(5).isKill()) {
+    return EmitLoweredCascadedSelect(MI, *Next, BB, Subtarget);
+  }
 
   for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
        SequenceMBBI != E; ++SequenceMBBI) {
     if (SequenceMBBI->isDebugInstr())
       continue;
     if (isSelectPseudo(*SequenceMBBI)) {
       if (SequenceMBBI->getOperand(1).getReg() != LHS ||
           SequenceMBBI->getOperand(2).getReg() != RHS ||

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

 ; RV64IBT-NEXT:    addw a0, a0, a1
 ; RV64IBT-NEXT:    ret
 entry:
   %cond1 = select i1 %a, i32 %c, i32 %d
   %cond2 = select i1 %b, i32 %e, i32 %f
   %ret = add i32 %cond1, %cond2
   ret i32 %ret
 }
+
+define float @CascadedSelect(float noundef %a) {
+; RV32I-LABEL: CascadedSelect:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV32I-NEXT:    flw ft0, %lo(.LCPI8_0)(a1)
+; RV32I-NEXT:    fmv.w.x ft1, a0
+; RV32I-NEXT:    flt.s a0, ft0, ft1
+; RV32I-NEXT:    bnez a0, .LBB8_3
+; RV32I-NEXT:  # %bb.1: # %entry
+; RV32I-NEXT:    fmv.w.x ft0, zero
+; RV32I-NEXT:    flt.s a0, ft1, ft0
+; RV32I-NEXT:    bnez a0, .LBB8_3
+; RV32I-NEXT:  # %bb.2: # %entry
+; RV32I-NEXT:    fmv.s ft0, ft1
+; RV32I-NEXT:  .LBB8_3: # %entry
+; RV32I-NEXT:    fmv.x.w a0, ft0
+; RV32I-NEXT:    ret
+;
+; RV32IBT-LABEL: CascadedSelect:
+; RV32IBT:       # %bb.0: # %entry
+; RV32IBT-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV32IBT-NEXT:    flw ft0, %lo(.LCPI8_0)(a1)
+; RV32IBT-NEXT:    fmv.w.x ft1, a0
+; RV32IBT-NEXT:    flt.s a0, ft0, ft1
+; RV32IBT-NEXT:    bnez a0, .LBB8_3
+; RV32IBT-NEXT:  # %bb.1: # %entry
+; RV32IBT-NEXT:    fmv.w.x ft0, zero
+; RV32IBT-NEXT:    flt.s a0, ft1, ft0
+; RV32IBT-NEXT:    bnez a0, .LBB8_3
+; RV32IBT-NEXT:  # %bb.2: # %entry
+; RV32IBT-NEXT:    fmv.s ft0, ft1
+; RV32IBT-NEXT:  .LBB8_3: # %entry
+; RV32IBT-NEXT:    fmv.x.w a0, ft0
+; RV32IBT-NEXT:    ret
+;
+; RV64I-LABEL: CascadedSelect:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV64I-NEXT:    flw ft0, %lo(.LCPI8_0)(a1)
+; RV64I-NEXT:    fmv.w.x ft1, a0
+; RV64I-NEXT:    flt.s a0, ft0, ft1
+; RV64I-NEXT:    bnez a0, .LBB8_3
+; RV64I-NEXT:  # %bb.1: # %entry
+; RV64I-NEXT:    fmv.w.x ft0, zero
+; RV64I-NEXT:    flt.s a0, ft1, ft0
+; RV64I-NEXT:    bnez a0, .LBB8_3
+; RV64I-NEXT:  # %bb.2: # %entry
+; RV64I-NEXT:    fmv.s ft0, ft1
+; RV64I-NEXT:  .LBB8_3: # %entry
+; RV64I-NEXT:    fmv.x.w a0, ft0
+; RV64I-NEXT:    ret
+;
+; RV64IBT-LABEL: CascadedSelect:
+; RV64IBT:       # %bb.0: # %entry
+; RV64IBT-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV64IBT-NEXT:    flw ft0, %lo(.LCPI8_0)(a1)
+; RV64IBT-NEXT:    fmv.w.x ft1, a0
+; RV64IBT-NEXT:    flt.s a0, ft0, ft1
+; RV64IBT-NEXT:    bnez a0, .LBB8_3
+; RV64IBT-NEXT:  # %bb.1: # %entry
+; RV64IBT-NEXT:    fmv.w.x ft0, zero
+; RV64IBT-NEXT:    flt.s a0, ft1, ft0
+; RV64IBT-NEXT:    bnez a0, .LBB8_3
+; RV64IBT-NEXT:  # %bb.2: # %entry
+; RV64IBT-NEXT:    fmv.s ft0, ft1
+; RV64IBT-NEXT:  .LBB8_3: # %entry
+; RV64IBT-NEXT:    fmv.x.w a0, ft0
+; RV64IBT-NEXT:    ret
+entry:
+  %cmp = fcmp ogt float %a, 1.000000e+00
+  %cmp1 = fcmp olt float %a, 0.000000e+00
+  %.a = select i1 %cmp1, float 0.000000e+00, float %a
+  %retval.0 = select i1 %cmp, float 1.000000e+00, float %.a
+  ret float %retval.0
+}