[ARM] [MinGW] Default to WinEH exception handling instead of Dwarf

[mstorsjo]

Summary

Switching this target to SEH also seems to affect the -windows-itanium
target.

I'd still hold off of pushing this patch until all of the headers/runtime
patches have landed.

[smeenai]

Super cool :)

@bd1976llvm was trying to use Windows Itanium some time ago, so CCing him for awareness.

[mstorsjo]

All the prerequisites have been approved now - @efriedma, can you comment on this one and D126871 ?

[efriedma]

LGTM

llvm/lib/MC/MCObjectFileInfo.cpp

void MCObjectFileInfo::initCOFFMCObjectFileInfo(const Triple &T) {
   DataSection = Ctx->getCOFFSection(
       ".data", COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | COFF::IMAGE_SCN_MEM_READ |
                    COFF::IMAGE_SCN_MEM_WRITE,
       SectionKind::getData());
   ReadOnlySection = Ctx->getCOFFSection(
       ".rdata", COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | COFF::IMAGE_SCN_MEM_READ,
       SectionKind::getReadOnly());
 
-  if (T.getArch() == Triple::x86_64 || T.getArch() == Triple::aarch64) {
-    // On Windows 64 with SEH, the LSDA is emitted into the .xdata section
+  if (T.getArch() == Triple::x86_64 || T.getArch() == Triple::aarch64 ||
+      T.getArch() == Triple::arm || T.getArch() == Triple::thumb) {
+    // On Windows with SEH, the LSDA is emitted into the .xdata section
     LSDASection = nullptr;
   } else {
     LSDASection = Ctx->getCOFFSection(".gcc_except_table",
                                       COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
                                           COFF::IMAGE_SCN_MEM_READ,
                                       SectionKind::getReadOnly());
   }
 

llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

ARMCOFFMCAsmInfoGNU::ARMCOFFMCAsmInfoGNU() {
 
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
   PrivateGlobalPrefix = ".L";
   PrivateLabelPrefix = ".L";
 
   SupportsDebugInformation = true;
-  ExceptionsType = ExceptionHandling::DwarfCFI;
+  ExceptionsType = ExceptionHandling::WinEH;
+  WinEHEncodingType = WinEH::EncodingType::Itanium;
   UseParensForSymbolVariant = true;
 
   DwarfRegNumForCFI = false;
 
   // Conditional Thumb 4-byte instructions can have an implicit IT.
   MaxInstLength = 6;
 }

llvm/test/CodeGen/ARM/Windows/dbzchk.ll

 
 ; CHECK-CFG-DAG: %bb.3
 ; CHECK-CFG-DAG: tBX_RET
 
 ; CHECK-CFG-DAG: %bb.5
 ; CHECK-CFG-DAG: t__brkdiv0
 
 ; CHECK-CFG-ASM-LABEL: h:
-; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_4
+; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_5
 ; CHECK-CFG-ASM: bl __rt_udiv
-; CHECK-CFG-ASM-LABEL: .LBB2_4:
+; CHECK-CFG-ASM-LABEL: .LBB2_5:
 ; CHECK-CFG-ASM: __brkdiv0
 
 ; RUN: llc -O1 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
 
 ; long k(void);
 ; int l(void);
 ; int j(int i) {
 ;   if (l() == -1)

llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll

 ; CHECK:    bx   lr
 entry:
   %0 = load i32, i32* @extvar, align 4
   ret i32 %0
 }
 
 define dso_local void @callFunc() {
 ; CHECK-LABEL: callFunc:
-; CHECK:    b otherFunc
+; CHECK:    b.w otherFunc
 entry:
   tail call void @otherFunc()
   ret void
 }
 
 declare dso_local void @otherFunc()
 
 ; CHECK:        .section        .rdata$.refptr.var,"dr",discard,.refptr.var
 ; CHECK:        .globl  .refptr.var
 ; CHECK: .refptr.var:
 ; CHECK:        .long   var

llvm/test/CodeGen/ARM/Windows/powi.ll

 ; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
 
 declare double @llvm.powi.f64.i32(double, i32)
 declare float @llvm.powi.f32.i32(float, i32)
 
 define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
 entry:
   %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK-LABEL: d:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
-; CHECK-NEXT: b pow
+; CHECK-NEXT: b.w pow
 ; CHECK-NOT: __powisf2
 
 define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
 entry:
   %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK-LABEL: f:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
-; CHECK-NEXT: b pow
+; CHECK-NEXT: b.w pow
 ; CHECK-NOT: __powisf2
 
 define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
 entry:
   %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   %conv = fptrunc double %0 to float
   ret float %conv
 }

llvm/test/CodeGen/ARM/ehabi.ll

 ; RUN:     -frame-pointer=all -filetype=asm -o - %s \
 ; RUN:   | FileCheck %s --check-prefix=DWARF-V7-FP
 
 ; RUN: llc -mtriple armv7-unknown-netbsd-eabi \
 ; RUN:     -filetype=asm -o - %s \
 ; RUN:   | FileCheck %s --check-prefix=DWARF-V7-FP-ELIM
 
 ; RUN: llc -mtriple thumbv7-windows-gnu \
-; RUN:     -filetype=asm -o - %s \
+; RUN:     -filetype=asm -exception-model=dwarf -o - %s \
 ; RUN:   | FileCheck %s --check-prefix=DWARF-WIN-FP-ELIM
 
+; RUN: llc -mtriple thumbv7-windows-gnu \
+; RUN:     -filetype=asm -o - %s \
+; RUN:   | FileCheck %s --check-prefix=SEH-WIN-FP-ELIM
+
 ;-------------------------------------------------------------------------------
 ; Test 1
 ;-------------------------------------------------------------------------------
 ; This is the LLVM assembly generated from following C++ code:
 ;
 ;   extern void print(int, int, int, int, int);
 ;   extern void print(double, double, double, double, double);
 ;

 ; DWARF-WIN-FP-ELIM:    .cfi_offset d9, -40
 ; DWARF-WIN-FP-ELIM:    sub sp, #8
 ; DWARF-WIN-FP-ELIM:    .cfi_def_cfa_offset 56
 ; DWARF-WIN-FP-ELIM:    add sp, #8
 ; DWARF-WIN-FP-ELIM:    vpop {d8, d9, d10, d11, d12}
 ; DWARF-WIN-FP-ELIM:    pop {r4, pc}
 ; DWARF-WIN-FP-ELIM:    .cfi_endproc
 
+; SEH-WIN-FP-ELIM-LABEL: _Z4testiiiiiddddd:
+; SEH-WIN-FP-ELIM:    .seh_proc _Z4testiiiiiddddd
+; SEH-WIN-FP-ELIM:    .seh_handler __gxx_personality_v0, %unwind, %except
+; SEH-WIN-FP-ELIM:    push {r4, lr}
+; SEH-WIN-FP-ELIM:    .seh_save_regs {r4, lr}
+; SEH-WIN-FP-ELIM:    vpush {d8, d9, d10, d11, d12}
+; SEH-WIN-FP-ELIM:    .seh_save_fregs {d8-d12}
+; SEH-WIN-FP-ELIM:    sub sp, #8
+; SEH-WIN-FP-ELIM:    .seh_stackalloc 8
+; SEH-WIN-FP-ELIM:    .seh_endprologue
+; SEH-WIN-FP-ELIM:    .seh_startepilogue
+; SEH-WIN-FP-ELIM:    add sp, #8
+; SEH-WIN-FP-ELIM:    .seh_stackalloc 8
+; SEH-WIN-FP-ELIM:    vpop {d8, d9, d10, d11, d12}
+; SEH-WIN-FP-ELIM:    .seh_save_fregs {d8-d12}
+; SEH-WIN-FP-ELIM:    pop {r4, pc}
+; SEH-WIN-FP-ELIM:    .seh_save_regs {r4, lr}
+; SEH-WIN-FP-ELIM:    .seh_endepilogue
+; SEH-WIN-FP-ELIM:    .seh_endproc
+
 ;-------------------------------------------------------------------------------
 ; Test 2
 ;-------------------------------------------------------------------------------
 
 declare void @throw_exception_2()
 
 define void @test2() {
 entry:

 ; DWARF-WIN-FP-ELIM:    .cfi_startproc
 ; DWARF-WIN-FP-ELIM:    push.w {r11, lr}
 ; DWARF-WIN-FP-ELIM:    .cfi_def_cfa_offset 8
 ; DWARF-WIN-FP-ELIM:    .cfi_offset lr, -4
 ; DWARF-WIN-FP-ELIM:    .cfi_offset r11, -8
 ; DWARF-WIN-FP-ELIM:    pop.w  {r11, pc}
 ; DWARF-WIN-FP-ELIM:    .cfi_endproc
 
+; SEH-WIN-FP-ELIM-LABEL: test2:
+; SEH-WIN-FP-ELIM:    .seh_proc test2
+; SEH-WIN-FP-ELIM:    push.w {r11, lr}
+; SEH-WIN-FP-ELIM:    .seh_save_regs_w {r11, lr}
+; SEH-WIN-FP-ELIM:    .seh_endprologue
+; SEH-WIN-FP-ELIM:    .seh_startepilogue
+; SEH-WIN-FP-ELIM:    pop.w  {r11, pc}
+; SEH-WIN-FP-ELIM:    .seh_endepilogue
+; SEH-WIN-FP-ELIM:    .seh_endproc
+
 
 ;-------------------------------------------------------------------------------
 ; Test 3
 ;-------------------------------------------------------------------------------
 
 declare void @throw_exception_3(i32)
 
 define i32 @test3(i32 %a, i32 %b, i32 %c, i32 %d,

 ; DWARF-WIN-FP-ELIM:    .cfi_def_cfa_offset 16
 ; DWARF-WIN-FP-ELIM:    .cfi_offset lr, -4
 ; DWARF-WIN-FP-ELIM:    .cfi_offset r11, -8
 ; DWARF-WIN-FP-ELIM:    .cfi_offset r5, -12
 ; DWARF-WIN-FP-ELIM:    .cfi_offset r4, -16
 ; DWARF-WIN-FP-ELIM:    pop.w  {r4, r5, r11, pc}
 ; DWARF-WIN-FP-ELIM:    .cfi_endproc
 
+; SEH-WIN-FP-ELIM-LABEL: test3:
+; SEH-WIN-FP-ELIM:    .seh_proc test3
+; SEH-WIN-FP-ELIM:    push.w {r4, r5, r11, lr}
+; SEH-WIN-FP-ELIM:    .seh_save_regs_w {r4-r5, r11, lr}
+; SEH-WIN-FP-ELIM:    .seh_endprologue
+; SEH-WIN-FP-ELIM:    .seh_startepilogue
+; SEH-WIN-FP-ELIM:    pop.w  {r4, r5, r11, pc}
+; SEH-WIN-FP-ELIM:    .seh_save_regs_w {r4-r5, r11, lr}
+; SEH-WIN-FP-ELIM:    .seh_endepilogue
+; SEH-WIN-FP-ELIM:    .seh_endproc
+
 
 ;-------------------------------------------------------------------------------
 ; Test 4
 ;-------------------------------------------------------------------------------
 
 define void @test4() nounwind {
 entry:
   ret void

 ; DWARF-V7-FP-ELIM:     bx lr
 ; DWARF-V7-FP-ELIM-NOT: .cfi_endproc
 ; DWARF-V7-FP-ELIM:     .size test4,
 
 ; DWARF-WIN-FP-ELIM-LABEL: test4:
 ; DWARF-WIN-FP-ELIM-NOT: .cfi_startproc
 ; DWARF-WIN-FP-ELIM:     bx lr
 ; DWARF-WIN-FP-ELIM-NOT: .cfi_endproc
+
+; SEH-WIN-FP-ELIM-LABEL: test4:
+; SEH-WIN-FP-ELIM-NOT: .seh_proc test4
+; SEH-WIN-FP-ELIM:     bx lr
+; SEH-WIN-FP-ELIM-NOT: .seh_endproc