[RISCV] Use the new chain when converting a fixed RVV load

[rogfer01]

Summary

When building the final merged node, we were using the original chain rather than the output chain of the new operation. After some collapsing of the chain this could cause the loads be incorrectly scheduled respect to later stores.

This was uncovered by SingleSource/Regression/C/gcc-c-torture/execute/pr36038.c of the llvm testsuite.

[craig.topper]

Well that's embarassing.

LGTM

[rogfer01]

Accidents happen.. Thanks for the prompt review @craig.topper.

[rogfer01]

I added the link but I forgot the Differential Revision: marker. This was fixed in 189ca6958e84

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
   Ops.push_back(Load->getBasePtr());
   Ops.push_back(VL);
   SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
   SDValue NewLoad =
       DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops,
                               Load->getMemoryVT(), Load->getMemOperand());
 
   SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
-  return DAG.getMergeValues({Result, Load->getChain()}, DL);
+  return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
 }
 
 SDValue
 RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDLoc DL(Op);
   auto *Store = cast<StoreSDNode>(Op);
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

 ; LMULMAX1-NEXT:    .cfi_offset s0, -16
 ; LMULMAX1-NEXT:    addi s0, sp, 256
 ; LMULMAX1-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX1-NEXT:    andi sp, sp, -128
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; LMULMAX1-NEXT:    vle32.v v8, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-NEXT:    vle32.v v13, (a1)
-; LMULMAX1-NEXT:    addi a0, a1, 16
-; LMULMAX1-NEXT:    vle32.v v14, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vle32.v v15, (a0)
+; LMULMAX1-NEXT:    addi a0, a1, 16
+; LMULMAX1-NEXT:    vle32.v v14, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 48
 ; LMULMAX1-NEXT:    vle32.v v16, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 64
 ; LMULMAX1-NEXT:    vle32.v v17, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 80
 ; LMULMAX1-NEXT:    vle32.v v18, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 96
 ; LMULMAX1-NEXT:    vle32.v v19, (a0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

; CHECK-NEXT:    ret
   %d = shufflevector <2 x double> %c, <2 x double> poison, <2 x i32> zeroinitializer
   store <2 x double> %d, <2 x double>* %x
   ret void
 }
 
 define void @gather_const_v64f16(<64 x half>* %x) {
 ; LMULMAX8-LABEL: gather_const_v64f16:
 ; LMULMAX8:       # %bb.0:
-; LMULMAX8-NEXT:    addi a1, a0, 94
-; LMULMAX8-NEXT:    li a2, 64
-; LMULMAX8-NEXT:    vsetvli zero, a2, e16, m8, ta, mu
-; LMULMAX8-NEXT:    vlse16.v v8, (a1), zero
+; LMULMAX8-NEXT:    li a1, 64
+; LMULMAX8-NEXT:    addi a2, a0, 94
+; LMULMAX8-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
+; LMULMAX8-NEXT:    vlse16.v v8, (a2), zero
 ; LMULMAX8-NEXT:    vse16.v v8, (a0)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v64f16:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    addi a2, a0, 48
-; LMULMAX1-NEXT:    addi a3, a0, 32
-; LMULMAX1-NEXT:    addi a4, a0, 80
+; LMULMAX1-NEXT:    addi a1, a0, 80
+; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a3, a0, 48
+; LMULMAX1-NEXT:    addi a4, a0, 32
 ; LMULMAX1-NEXT:    addi a5, a0, 94
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; LMULMAX1-NEXT:    vlse16.v v8, (a5), zero
 ; LMULMAX1-NEXT:    addi a5, a0, 64
 ; LMULMAX1-NEXT:    addi a6, a0, 112
 ; LMULMAX1-NEXT:    addi a7, a0, 96
 ; LMULMAX1-NEXT:    vse16.v v8, (a7)
 ; LMULMAX1-NEXT:    vse16.v v8, (a6)
 ; LMULMAX1-NEXT:    vse16.v v8, (a5)
+; LMULMAX1-NEXT:    vse16.v v8, (a1)
 ; LMULMAX1-NEXT:    vse16.v v8, (a4)
 ; LMULMAX1-NEXT:    vse16.v v8, (a3)
-; LMULMAX1-NEXT:    vse16.v v8, (a2)
 ; LMULMAX1-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-NEXT:    vse16.v v8, (a1)
+; LMULMAX1-NEXT:    vse16.v v8, (a2)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = extractelement <64 x half> %a, i32 47
   %c = insertelement <64 x half> poison, half %b, i32 0
   %d = shufflevector <64 x half> %c, <64 x half> poison, <64 x i32> zeroinitializer
   store <64 x half> %d, <64 x half>* %x
   ret void
 }
 
 define void @gather_const_v32f32(<32 x float>* %x) {
 ; LMULMAX8-LABEL: gather_const_v32f32:
 ; LMULMAX8:       # %bb.0:
-; LMULMAX8-NEXT:    addi a1, a0, 68
-; LMULMAX8-NEXT:    li a2, 32
-; LMULMAX8-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
-; LMULMAX8-NEXT:    vlse32.v v8, (a1), zero
+; LMULMAX8-NEXT:    li a1, 32
+; LMULMAX8-NEXT:    addi a2, a0, 68
+; LMULMAX8-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
+; LMULMAX8-NEXT:    vlse32.v v8, (a2), zero
 ; LMULMAX8-NEXT:    vse32.v v8, (a0)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v32f32:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    addi a2, a0, 48
-; LMULMAX1-NEXT:    addi a3, a0, 32
-; LMULMAX1-NEXT:    addi a4, a0, 80
+; LMULMAX1-NEXT:    addi a1, a0, 64
+; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a3, a0, 48
+; LMULMAX1-NEXT:    addi a4, a0, 32
 ; LMULMAX1-NEXT:    addi a5, a0, 68
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-NEXT:    vlse32.v v8, (a5), zero
-; LMULMAX1-NEXT:    addi a5, a0, 64
+; LMULMAX1-NEXT:    addi a5, a0, 80
 ; LMULMAX1-NEXT:    addi a6, a0, 112
 ; LMULMAX1-NEXT:    addi a7, a0, 96
 ; LMULMAX1-NEXT:    vse32.v v8, (a7)
 ; LMULMAX1-NEXT:    vse32.v v8, (a6)
+; LMULMAX1-NEXT:    vse32.v v8, (a1)
 ; LMULMAX1-NEXT:    vse32.v v8, (a5)
 ; LMULMAX1-NEXT:    vse32.v v8, (a4)
 ; LMULMAX1-NEXT:    vse32.v v8, (a3)
-; LMULMAX1-NEXT:    vse32.v v8, (a2)
 ; LMULMAX1-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-NEXT:    vse32.v v8, (a1)
+; LMULMAX1-NEXT:    vse32.v v8, (a2)
 ; LMULMAX1-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = extractelement <32 x float> %a, i32 17
   %c = insertelement <32 x float> poison, float %b, i32 0
   %d = shufflevector <32 x float> %c, <32 x float> poison, <32 x i32> zeroinitializer
   store <32 x float> %d, <32 x float>* %x
   ret void
 }
 
 define void @gather_const_v16f64(<16 x double>* %x) {
 ; LMULMAX8-LABEL: gather_const_v16f64:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    addi a1, a0, 80
 ; LMULMAX8-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; LMULMAX8-NEXT:    vlse64.v v8, (a1), zero
 ; LMULMAX8-NEXT:    vse64.v v8, (a0)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v16f64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    addi a2, a0, 48
-; LMULMAX1-NEXT:    addi a3, a0, 32
-; LMULMAX1-NEXT:    addi a4, a0, 80
+; LMULMAX1-NEXT:    addi a1, a0, 80
+; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a3, a0, 48
+; LMULMAX1-NEXT:    addi a4, a0, 32
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT:    vlse64.v v8, (a4), zero
+; LMULMAX1-NEXT:    vlse64.v v8, (a1), zero
 ; LMULMAX1-NEXT:    addi a5, a0, 64
 ; LMULMAX1-NEXT:    addi a6, a0, 112
 ; LMULMAX1-NEXT:    addi a7, a0, 96
 ; LMULMAX1-NEXT:    vse64.v v8, (a7)
 ; LMULMAX1-NEXT:    vse64.v v8, (a6)
 ; LMULMAX1-NEXT:    vse64.v v8, (a5)
+; LMULMAX1-NEXT:    vse64.v v8, (a1)
 ; LMULMAX1-NEXT:    vse64.v v8, (a4)
 ; LMULMAX1-NEXT:    vse64.v v8, (a3)
-; LMULMAX1-NEXT:    vse64.v v8, (a2)
 ; LMULMAX1-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-NEXT:    vse64.v v8, (a1)
+; LMULMAX1-NEXT:    vse64.v v8, (a2)
 ; LMULMAX1-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = extractelement <16 x double> %a, i32 10
   %c = insertelement <16 x double> poison, double %b, i32 0
   %d = shufflevector <16 x double> %c, <16 x double> poison, <16 x i32> zeroinitializer
   store <16 x double> %d, <16 x double>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

; CHECK-NEXT:    ret
   %d = shufflevector <2 x i64> %c, <2 x i64> poison, <2 x i32> zeroinitializer
   store <2 x i64> %d, <2 x i64>* %x
   ret void
 }
 
 define void @gather_const_v64i8(<64 x i8>* %x) {
 ; LMULMAX4-LABEL: gather_const_v64i8:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    addi a1, a0, 32
-; LMULMAX4-NEXT:    li a2, 64
-; LMULMAX4-NEXT:    vsetvli zero, a2, e8, m4, ta, mu
-; LMULMAX4-NEXT:    vlse8.v v8, (a1), zero
+; LMULMAX4-NEXT:    li a1, 64
+; LMULMAX4-NEXT:    addi a2, a0, 32
+; LMULMAX4-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
+; LMULMAX4-NEXT:    vlse8.v v8, (a2), zero
 ; LMULMAX4-NEXT:    vse8.v v8, (a0)
 ; LMULMAX4-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v64i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a1, a0, 32
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-NEXT:    vlse8.v v8, (a1), zero
; LMULMAX1-NEXT:    ret
   %d = shufflevector <64 x i8> %c, <64 x i8> poison, <64 x i32> zeroinitializer
   store <64 x i8> %d, <64 x i8>* %x
   ret void
 }
 
 define void @gather_const_v16i16(<32 x i16>* %x) {
 ; LMULMAX4-LABEL: gather_const_v16i16:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    addi a1, a0, 50
-; LMULMAX4-NEXT:    li a2, 32
-; LMULMAX4-NEXT:    vsetvli zero, a2, e16, m4, ta, mu
-; LMULMAX4-NEXT:    vlse16.v v8, (a1), zero
+; LMULMAX4-NEXT:    li a1, 32
+; LMULMAX4-NEXT:    addi a2, a0, 50
+; LMULMAX4-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
+; LMULMAX4-NEXT:    vlse16.v v8, (a2), zero
 ; LMULMAX4-NEXT:    vse16.v v8, (a0)
 ; LMULMAX4-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a1, a0, 50
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; LMULMAX1-NEXT:    vlse16.v v8, (a1), zero
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    addi a2, a0, 48
+; LMULMAX1-NEXT:    addi a1, a0, 48
+; LMULMAX1-NEXT:    addi a2, a0, 16
 ; LMULMAX1-NEXT:    addi a3, a0, 32
 ; LMULMAX1-NEXT:    vse16.v v8, (a3)
-; LMULMAX1-NEXT:    vse16.v v8, (a2)
-; LMULMAX1-NEXT:    vse16.v v8, (a0)
 ; LMULMAX1-NEXT:    vse16.v v8, (a1)
+; LMULMAX1-NEXT:    vse16.v v8, (a0)
+; LMULMAX1-NEXT:    vse16.v v8, (a2)
 ; LMULMAX1-NEXT:    ret
   %a = load <32 x i16>, <32 x i16>* %x
   %b = extractelement <32 x i16> %a, i32 25
   %c = insertelement <32 x i16> poison, i16 %b, i32 0
   %d = shufflevector <32 x i16> %c, <32 x i16> poison, <32 x i32> zeroinitializer
   store <32 x i16> %d, <32 x i16>* %x
   ret void
 }
 
 define void @gather_const_v16i32(<16 x i32>* %x) {
 ; LMULMAX4-LABEL: gather_const_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    addi a1, a0, 36
 ; LMULMAX4-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; LMULMAX4-NEXT:    vlse32.v v8, (a1), zero
 ; LMULMAX4-NEXT:    vse32.v v8, (a0)
 ; LMULMAX4-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: gather_const_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a1, a0, 36
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-NEXT:    vlse32.v v8, (a1), zero
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    addi a2, a0, 48
-; LMULMAX1-NEXT:    addi a3, a0, 32
+; LMULMAX1-NEXT:    addi a1, a0, 32
+; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a3, a0, 48
+; LMULMAX1-NEXT:    vse32.v v8, (a1)
 ; LMULMAX1-NEXT:    vse32.v v8, (a3)
-; LMULMAX1-NEXT:    vse32.v v8, (a2)
 ; LMULMAX1-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-NEXT:    vse32.v v8, (a1)
+; LMULMAX1-NEXT:    vse32.v v8, (a2)
 ; LMULMAX1-NEXT:    ret
   %a = load <16 x i32>, <16 x i32>* %x
   %b = extractelement <16 x i32> %a, i32 9
   %c = insertelement <16 x i32> poison, i32 %b, i32 0
   %d = shufflevector <16 x i32> %c, <16 x i32> poison, <16 x i32> zeroinitializer
   store <16 x i32> %d, <16 x i32>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 < %s \
 ; RUN:   | FileCheck %s
 
 @c = global [7 x i64] [i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7], align 8
 
 define void @do.memmove() nounwind {
 ; CHECK-LABEL: do.memmove:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a0, %hi(c)
 ; CHECK-NEXT:    addi a0, a0, %lo(c)
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    addi a1, a0, 16
+; CHECK-NEXT:    vle64.v v9, (a1)
 ; CHECK-NEXT:    addi a1, a0, 8
 ; CHECK-NEXT:    vse64.v v8, (a1)
-; CHECK-NEXT:    addi a1, a0, 16
-; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    addi a0, a0, 24
-; CHECK-NEXT:    vse64.v v8, (a0)
+; CHECK-NEXT:    vse64.v v9, (a0)
 ; CHECK-NEXT:    ret
 entry:
   ; this thing is "__builtin_memmove(&c[1], &c[0], sizeof(c[0]) * 4);"
   tail call void @llvm.memmove.p0.p0.i64(
         ptr noundef nonnull align 8 dereferenceable(32) getelementptr inbounds ([7 x i64], ptr @c, i64 0, i64 1),
         ptr noundef nonnull align 8 dereferenceable(32) @c, i64 32, i1 false)
   ret void
 }
 
 ; Function Attrs: argmemonly mustprogress nofree nounwind willreturn
 declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) #1
 
 attributes #1 = { argmemonly mustprogress nofree nounwind willreturn }