[RISCV][WIP] Update isLegalAddressingMode for RVV.

[craig.topper]

Summary

RVV instructions only support base register addressing.

Probably need more directed LSR tests and maybe CodeGenPrepare.

[reames]

LGTM w/comment addressed.

I applied this locally and checked a couple of hand written vector loops I'm using to get myself started, and the results look entirely reasonable.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1021

Placement wise, this makes more sense at the top so that all of the scalar checks are grouped together.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1021

Top, or just above the 12-bit offset check?

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1021

Ah, you're right.

Or alternately, top, and duplicate the BaseGV check.

Either is fine.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
   // No global is ever allowed as a base.
   if (AM.BaseGV)
     return false;
 
   // Require a 12-bit signed offset.
   if (!isInt<12>(AM.BaseOffs))
     return false;
 
+  // RVV instructions only support register addressing.
+  if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
+    return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs;
+
   switch (AM.Scale) {
   case 0: // "r+i" or just "i", depending on HasBaseReg.
     break;
   case 1:
     if (!AM.HasBaseReg) // allow "r+i".
       break;
     return false; // disallow "r+r" or "r+r+i".
   default:

llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

 ; CHECK-NEXT:    [[VEC_IND_NEXT_SCALAR2]] = add i64 [[VEC_IND_SCALAR1]], 16
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
 ; CHECK-NEXT:    br i1 [[TMP10]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
 ; CHECK:       for.cond.cleanup:
 ; CHECK-NEXT:    ret void
 ;
 ; CHECK-ASM-LABEL: struct_gather:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    addi a0, a0, 32
 ; CHECK-ASM-NEXT:    addi a1, a1, 132
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 16
 ; CHECK-ASM-NEXT:  .LBB8_1: # %vector.body
 ; CHECK-ASM-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-ASM-NEXT:    addi a4, a1, -128
 ; CHECK-ASM-NEXT:    vsetivli zero, 8, e32, m1, ta, mu
 ; CHECK-ASM-NEXT:    vlse32.v v8, (a4), a3
 ; CHECK-ASM-NEXT:    vlse32.v v9, (a1), a3
-; CHECK-ASM-NEXT:    addi a4, a0, -32
-; CHECK-ASM-NEXT:    vle32.v v10, (a4)
-; CHECK-ASM-NEXT:    vle32.v v11, (a0)
+; CHECK-ASM-NEXT:    vle32.v v10, (a0)
+; CHECK-ASM-NEXT:    addi a4, a0, 32
+; CHECK-ASM-NEXT:    vle32.v v11, (a4)
 ; CHECK-ASM-NEXT:    vadd.vv v8, v10, v8
 ; CHECK-ASM-NEXT:    vadd.vv v9, v11, v9
-; CHECK-ASM-NEXT:    vse32.v v8, (a4)
-; CHECK-ASM-NEXT:    vse32.v v9, (a0)
+; CHECK-ASM-NEXT:    vse32.v v8, (a0)
+; CHECK-ASM-NEXT:    vse32.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a2, a2, -16
 ; CHECK-ASM-NEXT:    addi a0, a0, 64
 ; CHECK-ASM-NEXT:    addi a1, a1, 256
 ; CHECK-ASM-NEXT:    bnez a2, .LBB8_1
 ; CHECK-ASM-NEXT:  # %bb.2: # %for.cond.cleanup
 ; CHECK-ASM-NEXT:    ret
 entry:
   br label %vector.body

 ; CHECK-NEXT:    [[DOTSCALAR3]] = add i64 [[DOTSCALAR2]], 20
 ; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1024
 ; CHECK-NEXT:    br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP3]]
 ; CHECK:       15:
 ; CHECK-NEXT:    ret void
 ;
 ; CHECK-ASM-LABEL: gather_of_pointers:
 ; CHECK-ASM:       # %bb.0:
-; CHECK-ASM-NEXT:    addi a0, a0, 16
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 40
 ; CHECK-ASM-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; CHECK-ASM-NEXT:    addi a4, a1, 80
 ; CHECK-ASM-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-ASM-NEXT:    vlse64.v v8, (a1), a3
+; CHECK-ASM-NEXT:    addi a4, a1, 80
 ; CHECK-ASM-NEXT:    vlse64.v v9, (a4), a3
-; CHECK-ASM-NEXT:    addi a4, a0, -16
-; CHECK-ASM-NEXT:    vse64.v v8, (a4)
-; CHECK-ASM-NEXT:    vse64.v v9, (a0)
+; CHECK-ASM-NEXT:    vse64.v v8, (a0)
+; CHECK-ASM-NEXT:    addi a4, a0, 16
+; CHECK-ASM-NEXT:    vse64.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a2, a2, -4
 ; CHECK-ASM-NEXT:    addi a0, a0, 32
 ; CHECK-ASM-NEXT:    addi a1, a1, 160
 ; CHECK-ASM-NEXT:    bnez a2, .LBB10_1
 ; CHECK-ASM-NEXT:  # %bb.2:
 ; CHECK-ASM-NEXT:    ret
   br label %3
 

 ; CHECK-NEXT:    [[DOTSCALAR3]] = add i64 [[DOTSCALAR2]], 20
 ; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1024
 ; CHECK-NEXT:    br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP3]]
 ; CHECK:       15:
 ; CHECK-NEXT:    ret void
 ;
 ; CHECK-ASM-LABEL: scatter_of_pointers:
 ; CHECK-ASM:       # %bb.0:
-; CHECK-ASM-NEXT:    addi a1, a1, 16
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 40
 ; CHECK-ASM-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; CHECK-ASM-NEXT:    addi a4, a1, -16
 ; CHECK-ASM-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-ASM-NEXT:    vle64.v v8, (a4)
-; CHECK-ASM-NEXT:    vle64.v v9, (a1)
+; CHECK-ASM-NEXT:    vle64.v v8, (a1)
+; CHECK-ASM-NEXT:    addi a4, a1, 16
+; CHECK-ASM-NEXT:    vle64.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a4, a0, 80
 ; CHECK-ASM-NEXT:    vsse64.v v8, (a0), a3
 ; CHECK-ASM-NEXT:    vsse64.v v9, (a4), a3
 ; CHECK-ASM-NEXT:    addi a2, a2, -4
 ; CHECK-ASM-NEXT:    addi a1, a1, 32
 ; CHECK-ASM-NEXT:    addi a0, a0, 160
 ; CHECK-ASM-NEXT:    bnez a2, .LBB11_1
 ; CHECK-ASM-NEXT:  # %bb.2: