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Differential D123178

[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
ClosedPublic

Authored by kito-cheng on Apr 5 2022, 9:08 PM.

Details

Reviewers
asb
craig.topper
luismarques
frasercrmck
Commits
rG690085c9b715: [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
Summary

RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and
VarArgsSaveSize are calculated at ISel lowering stage, those info are
not contained in MIR files, that cause test cases rely on those field
can't not reproduce correctly by MIR dump files.

This patch adding the MIR read/write for those fields.

Diff Detail

Event Timeline

kito-cheng created this revision.Apr 5 2022, 9:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 5 2022, 9:08 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
kito-cheng requested review of this revision.Apr 5 2022, 9:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 5 2022, 9:08 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
kito-cheng added reviewers: asb, craig.topper, luismarques.Apr 5 2022, 9:10 PM
Herald added a subscriber: StephenFan. · View Herald TranscriptApr 5 2022, 9:10 PM
kito-cheng added a child revision: D123179: [RISCV] Pre-commit for fixing stack offset for RVV object.Apr 5 2022, 9:24 PM
Harbormaster completed remote builds in B158112: Diff 420698.Apr 5 2022, 9:42 PM
frasercrmck added inline comments.Apr 6 2022, 1:05 AM
llvm/test/CodeGen/RISCV/machine-function-info.mir
97 ↗(On Diff #420698)

I guess we should be checking that machineFunctionInfo is serialized back out again successfully? Seems like update_mir_test_checks.py isn't doing that for us.

craig.topper added inline comments.Apr 6 2022, 9:07 AM
llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
29

Why is MoveF64FrameIndex in here but never referenced anywhere else.

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
241

What makes this need a reinterpret_cast instead of a static_cast? I see that other targets are also using reinterpret_cast but I don't understand them either.

craig.topper mentioned this in D123260: [AArch64][AMDGPU][WebAssembly] Use static_cast instead of a reinterpret_cast to downcast in parseMachineFunctionInfo..Apr 6 2022, 2:54 PM
arsenm added a subscriber: arsenm.Apr 6 2022, 2:57 PM
arsenm added inline comments.
llvm/test/CodeGen/RISCV/machine-function-info.mir
2 ↗(On Diff #420698)

Would be a good idea to have a round trip run line to check printing and parsing

137 ↗(On Diff #420698)

MIR print/parser tests should go under test/CodeGen/MIR/RISCV, not test/CodeGen/RISCV

craig.topper mentioned this in rG1235aaefbd4f: [AArch64][AMDGPU][WebAssembly] Use static_cast instead of a reinterpret_cast to….Apr 6 2022, 3:10 PM
craig.topper added inline comments.Apr 6 2022, 7:49 PM
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
241

I pushed a fix to use static_cast on the other targets.

kito-cheng updated this revision to Diff 421074.Apr 6 2022, 8:37 PM

Changes:

  • Checking machineFunctionInfo.
  • Remove MoveF64FrameIndex.
  • Use static_cast rather than reinterpret_cast.
  • Move test case to test/CodeGen/MIR/RISCV.
kito-cheng marked 5 inline comments as done.Apr 6 2022, 8:41 PM
kito-cheng added inline comments.
llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
29

I was try to serialize that, but I realize that is not necessary soon, however I forgot to remove that...

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
241

Thanks, actually that's copy and paste from AArch64...:P

llvm/test/CodeGen/RISCV/machine-function-info.mir
97 ↗(On Diff #420698)

Thanks, check added!

137 ↗(On Diff #420698)

Moved :)

Harbormaster completed remote builds in B158385: Diff 421074.Apr 6 2022, 9:18 PM
rogfer01 mentioned this in D123179: [RISCV] Pre-commit for fixing stack offset for RVV object.Apr 7 2022, 12:45 AM
frasercrmck accepted this revision.Apr 7 2022, 2:24 AM

LGTM other than a couple of issues to fix up.

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
10

This comment's incorrect, isn't it? Something like this, I'd imagine:

// This file declares RISCV-specific per-machine-function information.
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
242

I don't see much value in creating MF here since we only use it once. I see it's a copy from AArch64. Just PFS.MF.getInfo.... would do?

llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir
2

I think we can merge these two RUN lines: they're less than 80 cols combined.

This revision is now accepted and ready to land.Apr 7 2022, 2:24 AM
This revision was landed with ongoing or failed builds.Apr 7 2022, 8:55 PM
Closed by commit rG690085c9b715: [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file (authored by kito-cheng). · Explain Why
This revision was automatically updated to reflect the committed changes.
kito-cheng marked 3 inline comments as done.
kito-cheng added a commit: rG690085c9b715: [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
1 line
25 lines
30 lines
8 lines
23 lines
test/
CodeGen/
MIR/
RISCV/
138 lines

Diff 421403

llvm/lib/Target/RISCV/CMakeLists.txt

Show All 25 Linesadd_llvm_target(RISCVCodeGen
RISCVFrameLowering.cpp RISCVFrameLowering.cpp
RISCVGatherScatterLowering.cpp RISCVGatherScatterLowering.cpp
RISCVInsertVSETVLI.cpp RISCVInsertVSETVLI.cpp
RISCVInstrInfo.cpp RISCVInstrInfo.cpp
RISCVInstructionSelector.cpp RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp RISCVISelLowering.cpp
RISCVLegalizerInfo.cpp RISCVLegalizerInfo.cpp
RISCVMachineFunctionInfo.cpp
RISCVMCInstLower.cpp RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp RISCVMergeBaseOffset.cpp
RISCVRedundantCopyElimination.cpp RISCVRedundantCopyElimination.cpp
RISCVRegisterBankInfo.cpp RISCVRegisterBankInfo.cpp
RISCVRegisterInfo.cpp RISCVRegisterInfo.cpp
RISCVSExtWRemoval.cpp RISCVSExtWRemoval.cpp
RISCVSubtarget.cpp RISCVSubtarget.cpp
RISCVTargetMachine.cpp RISCVTargetMachine.cpp
Show All 25 Lines

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

//=- RISCVMachineFunctionInfo.h - RISCV machine function info -----*- C++ -*-=// //=- RISCVMachineFunctionInfo.h - RISCV machine function info -----*- C++ -*-=//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file declares RISCV-specific per-machine-function information. // This file declares RISCV-specific per-machine-function information.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H #ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H #define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
#include "RISCVSubtarget.h" #include "RISCVSubtarget.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
namespace llvm { namespace llvm {
class RISCVMachineFunctionInfo;
namespace yaml {
struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo {
int VarArgsFrameIndex;
int VarArgsSaveSize;
craig.topperUnsubmitted
Done
ReplyInline Actions

Why is MoveF64FrameIndex in here but never referenced anywhere else.

craig.topper: Why is `MoveF64FrameIndex` in here but never referenced anywhere else.
kito-chengAuthorUnsubmitted
Done
ReplyInline Actions

I was try to serialize that, but I realize that is not necessary soon, however I forgot to remove that...

kito-cheng: I was try to serialize that, but I realize that is not necessary soon, however I forgot to…
RISCVMachineFunctionInfo() = default;
RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI);
void mappingImpl(yaml::IO &YamlIO) override;
~RISCVMachineFunctionInfo() = default;
};
template <> struct MappingTraits<RISCVMachineFunctionInfo> {
static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex);
YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize);
}
};
} // end namespace yaml
/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo /// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
/// and contains private RISCV-specific information for each MachineFunction. /// and contains private RISCV-specific information for each MachineFunction.
class RISCVMachineFunctionInfo : public MachineFunctionInfo { class RISCVMachineFunctionInfo : public MachineFunctionInfo {
private: private:
/// FrameIndex for start of varargs area /// FrameIndex for start of varargs area
int VarArgsFrameIndex = 0; int VarArgsFrameIndex = 0;
/// Size of the save area used for varargs /// Size of the save area used for varargs
int VarArgsSaveSize = 0; int VarArgsSaveSize = 0;
Show All 39 Linespublic:
uint64_t getRVVStackSize() const { return RVVStackSize; } uint64_t getRVVStackSize() const { return RVVStackSize; }
void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; } void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
uint64_t getRVVPadding() const { return RVVPadding; } uint64_t getRVVPadding() const { return RVVPadding; }
void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; } void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; } unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; } void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
}; };
} // end namespace llvm } // end namespace llvm
#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H #endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp

  • This file was added.
//=- RISCVMachineFunctionInfo.cpp - RISCV machine function info ---*- C++ -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares RISCV-specific per-machine-function information.
//
frasercrmckUnsubmitted
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This comment's incorrect, isn't it? Something like this, I'd imagine:

// This file declares RISCV-specific per-machine-function information.
frasercrmck: This comment's incorrect, isn't it? Something like this, I'd imagine: ``` // This file declares…
//===----------------------------------------------------------------------===//
#include "RISCVMachineFunctionInfo.h"
using namespace llvm;
yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
const llvm::RISCVMachineFunctionInfo &MFI)
: VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
MappingTraits<RISCVMachineFunctionInfo>::mapping(YamlIO, *this);
}
void RISCVMachineFunctionInfo::initializeBaseYamlFields(
const yaml::RISCVMachineFunctionInfo &YamlMFI) {
VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
VarArgsSaveSize = YamlMFI.VarArgsSaveSize;
}

llvm/lib/Target/RISCV/RISCVTargetMachine.h

Show All 40 Linespublic:
TargetLoweringObjectFile *getObjFileLowering() const override { TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get(); return TLOF.get();
} }
TargetTransformInfo getTargetTransformInfo(const Function &F) const override; TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
unsigned DstAS) const override; unsigned DstAS) const override;
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction &MF) const override;
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
PerFunctionMIParsingState &PFS,
SMDiagnostic &Error,
SMRange &SourceRange) const override;
}; };
} // namespace llvm } // namespace llvm
#endif #endif

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Implements the info about RISCV target spec. // Implements the info about RISCV target spec.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVTargetMachine.h" #include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h" #include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetObjectFile.h" #include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h" #include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h" #include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/InitializePasses.h" #include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h" #include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/FormattedStream.h" #include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createRISCVMergeBaseOffsetOptPass()); addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass()); addPass(createRISCVInsertVSETVLIPass());
} }
void RISCVPassConfig::addPostRegAlloc() { void RISCVPassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
addPass(createRISCVRedundantCopyEliminationPass()); addPass(createRISCVRedundantCopyEliminationPass());
} }
yaml::MachineFunctionInfo *
RISCVTargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::RISCVMachineFunctionInfo();
}
yaml::MachineFunctionInfo *
RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
return new yaml::RISCVMachineFunctionInfo(*MFI);
}
bool RISCVTargetMachine::parseMachineFunctionInfo(
const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
SMDiagnostic &Error, SMRange &SourceRange) const {
const auto &YamlMFI =
static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
craig.topperUnsubmitted
Done
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What makes this need a reinterpret_cast instead of a static_cast? I see that other targets are also using reinterpret_cast but I don't understand them either.

craig.topper: What makes this need a reinterpret_cast instead of a static_cast? I see that other targets are…
craig.topperUnsubmitted
Done
ReplyInline Actions

I pushed a fix to use static_cast on the other targets.

craig.topper: I pushed a fix to use static_cast on the other targets.
kito-chengAuthorUnsubmitted
Done
ReplyInline Actions

Thanks, actually that's copy and paste from AArch64...:P

kito-cheng: Thanks, actually that's copy and paste from AArch64...:P
PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
frasercrmckUnsubmitted
Not Done
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I don't see much value in creating MF here since we only use it once. I see it's a copy from AArch64. Just PFS.MF.getInfo.... would do?

frasercrmck: I don't see much value in creating `MF` here since we only use it once. I see it's a copy from…
return false;
}

llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir

  • This file was added.
# RUN: llc -mtriple=riscv64 -run-pass none %s -o - | FileCheck %s
frasercrmckUnsubmitted
Not Done
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I think we can merge these two RUN lines: they're less than 80 cols combined.

frasercrmck: I think we can merge these two RUN lines: they're less than 80 cols combined.
--- |
; ModuleID = 'foo.ll'
source_filename = "foo.ll"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"
define void @foo(i32 %0, ...) {
ret void
}
...
---
name: foo
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
failsVerification: false
tracksDebugUserValues: false
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
- { id: 3, class: gpr, preferred-register: '' }
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
- { id: 7, class: gpr, preferred-register: '' }
liveins:
- { reg: '$x11', virtual-reg: '%1' }
- { reg: '$x12', virtual-reg: '%2' }
- { reg: '$x13', virtual-reg: '%3' }
- { reg: '$x14', virtual-reg: '%4' }
- { reg: '$x15', virtual-reg: '%5' }
- { reg: '$x16', virtual-reg: '%6' }
- { reg: '$x17', virtual-reg: '%7' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
hasTailCall: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
- { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, type: default, offset: -24, size: 8, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, type: default, offset: -32, size: 8, alignment: 16, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, type: default, offset: -40, size: 8, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, type: default, offset: -48, size: 8, alignment: 16, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 6, type: default, offset: -56, size: 8, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, type: default, offset: -64, size: 8, alignment: 16, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 8, type: default, offset: -56, size: 8, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo:
varArgsFrameIndex: -1
varArgsSaveSize: 64
body: |
bb.0 (%ir-block.1):
liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17
; CHECK-LABEL: name: foo
; CHECK: machineFunctionInfo:
; CHECK-NEXT: varArgsFrameIndex: -1
; CHECK-NEXT: varArgsSaveSize: 64
; CHECK: liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x17
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x16
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x14
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x13
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: SD [[COPY]], %fixed-stack.8, 0 :: (store (s64))
; CHECK-NEXT: SD [[COPY1]], %fixed-stack.7, 0 :: (store (s64) into %fixed-stack.7, align 16)
; CHECK-NEXT: SD [[COPY2]], %fixed-stack.6, 0 :: (store (s64))
; CHECK-NEXT: SD [[COPY3]], %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16)
; CHECK-NEXT: SD [[COPY4]], %fixed-stack.4, 0 :: (store (s64))
; CHECK-NEXT: SD [[COPY5]], %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16)
; CHECK-NEXT: SD [[COPY6]], %fixed-stack.2, 0 :: (store (s64))
; CHECK-NEXT: PseudoRET
%7:gpr = COPY $x17
%6:gpr = COPY $x16
%5:gpr = COPY $x15
%4:gpr = COPY $x14
%3:gpr = COPY $x13
%2:gpr = COPY $x12
%1:gpr = COPY $x11
SD %7, %fixed-stack.0, 0 :: (store (s64))
SD %6, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16)
SD %5, %fixed-stack.2, 0 :: (store (s64))
SD %4, %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16)
SD %3, %fixed-stack.4, 0 :: (store (s64))
SD %2, %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16)
SD %1, %fixed-stack.6, 0 :: (store (s64))
PseudoRET
...