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| llvm/test/CodeGen/RISCV/wrong-stack-offset-for-rvv-object.mir | ||
|---|---|---|
| 1 ↗ | (On Diff #420699) | Put in the rvv directory? |
Hi @kito-cheng
I'm ok with this once D123178 lands.
Just to confirm the issue is the vs1r of v8 before the loop. Is my understanding correct?
I made this diagram based on the output of llc -o - -mtriple riscv64 -mattr=+m,+v t.ll -riscv-v-vector-bits-min=512
asm_fprintf: # @asm_fprintf # %bb.0: # %entry addi sp, sp, -64 sd ra, 40(sp) # 8-byte Folded Spill sd s0, 32(sp) # 8-byte Folded Spill sd s1, 24(sp) # 8-byte Folded Spill csrr a0, vlenb sub sp, sp, a0 mv s0, a4 mv s1, a1 csrr a0, vlenb add a0, sp, a0 sd a7, 56(a0) csrr a0, vlenb add a0, sp, a0 sd a6, 48(a0) vsetivli zero, 2, e8, mf8, ta, mu vmv.v.i v8, 0 addi a0, sp, 40 vs1r.v v8, (a0) # Unknown-size Folded Spill .LBB0_1: # %while.cond # =>This Inner Loop Header: Depth=1 bnez zero, .LBB0_1 # %bb.2: # %sw.bb # in Loop: Header=BB0_1 Depth=1 vsetivli zero, 2, e8, mf8, ta, mu addi a0, sp, 40 vl1r.v v8, (a0) # Unknown-size Folded Reload vse8.v v8, (s0) mv a0, s1 call fprintf@plt j .LBB0_1
@rogfer01, almost right, but a6 and a7 is wrong on your table, that has added vlenb, so you only need to care about the offset, so the layout is something like this:
Currently, v8 will corrupt s0 and s1.
The test looks good to me, but I'd like to see some brief description of the problem in this commit, or some comments in the test itself. Something like what you and @rogfer01 have discussed here.
@rogfer01, almost right, but a6 and a7 is wrong on your table, that has added vlenb, so you only need to care about the offset, so the layout is something like this:
Currently, v8 will corrupt s0 and s1.
Thanks a lot Kito I missed the fact that we compensate again with vlenb.