[RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm

[Chenbing.Zheng]

Summary

vcpop and vfirst are still useful when VL=0.
vcpop equivalents to li 0 and vfirst equivalents to li -1,
since no mask elements are active.

[craig.topper]

This should be done as a DAGCombine not isel. You want the constant folding to enable other optimizations.

Even better would be instcombine so we can fold away branches. SelectionDAG can’t remove a branch even if the condition becomes constant.

[Chenbing.Zheng]

move to DAGCombine

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8492

You can use isNullConstant(VL)

8497

Use N->getValueType(0), not the type of the VL.

8503

There's no reason to make an ISD::ADD. You can just return DAG.getConstant

[Chenbing.Zheng]

fix according to review comments

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8500

No need for Imm. You can return DAG.getConstant(-1, DL, VT);

8501

No need for Imm. You can return DAG.getConstant(0, DL, VT);

[Chenbing.Zheng]

modify code

[Chenbing.Zheng]

I pre-commit tests in D120300, could you accept it if this patch is OK ?

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::XOR);
   setTargetDAGCombine(ISD::ROTL);
   setTargetDAGCombine(ISD::ROTR);
   setTargetDAGCombine(ISD::ANY_EXTEND);
+  setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
   if (Subtarget.hasStdExtZfh())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
   if (Subtarget.hasStdExtF()) {
     setTargetDAGCombine(ISD::ZERO_EXTEND);
     setTargetDAGCombine(ISD::FP_TO_SINT);
     setTargetDAGCombine(ISD::FP_TO_UINT);
     setTargetDAGCombine(ISD::FP_TO_SINT_SAT);
     setTargetDAGCombine(ISD::FP_TO_UINT_SAT);
case RISCVISD::VMV_V_X_VL: {
     unsigned ScalarSize = N->getOperand(1).getValueSizeInBits();
     unsigned EltWidth = N->getValueType(0).getScalarSizeInBits();
     if (ScalarSize > EltWidth && N->getOperand(0).isUndef())
       if (SimplifyDemandedLowBitsHelper(1, EltWidth))
         return SDValue(N, 0);
 
     break;
   }
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntNo = N->getConstantOperandVal(0);
+    switch (IntNo) {
+      // By default we do not combine any intrinsic.
+    default:
+      return SDValue();
+    case Intrinsic::riscv_vcpop:
+    case Intrinsic::riscv_vcpop_mask:
+    case Intrinsic::riscv_vfirst:
+    case Intrinsic::riscv_vfirst_mask: {
+      SDValue VL = N->getOperand(2);
+      if (IntNo == Intrinsic::riscv_vcpop_mask ||
+          IntNo == Intrinsic::riscv_vfirst_mask)
+        VL = N->getOperand(3);
+      if (!isNullConstant(VL))
+        return SDValue();
+      // If VL is 0, vcpop -> li 0, vfirst -> li -1.
+      SDLoc DL(N);
+      EVT VT = N->getValueType(0);
+      if (IntNo == Intrinsic::riscv_vfirst ||
+          IntNo == Intrinsic::riscv_vfirst_mask)
+        return DAG.getConstant(-1, DL, VT);
+      return DAG.getConstant(0, DL, VT);
+    }
+    }
+  }
   }
 
   return SDValue();
 }
 
 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
   // The following folds are only desirable if `(OP _, c1 << c2)` can be

llvm/test/CodeGen/RISCV/rvv/vcpop.ll

%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
     iXLen %1)
 
   ret iXLen %a
 }
 
 define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
 ; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
     <vscale x 1 x i1> %0,
     iXLen 0)
 
   ret iXLen %a
 }
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
     iXLen %2)
 
   ret iXLen %a
 }
 
 define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
 ; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a0, v9, v0.t
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
     <vscale x 1 x i1> %0,
     <vscale x 1 x i1> %1,
     iXLen 0)
 
   ret iXLen %a

llvm/test/CodeGen/RISCV/rvv/vfirst.ll

%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
     iXLen %1)
 
   ret iXLen %a
 }
 
 define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
 ; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
     <vscale x 1 x i1> %0,
     iXLen 0)
 
   ret iXLen %a
 }
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
     iXLen %2)
 
   ret iXLen %a
 }
 
 define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
 ; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vfirst.m a0, v9, v0.t
+; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
     <vscale x 1 x i1> %0,
     <vscale x 1 x i1> %1,
     iXLen 0)
 
   ret iXLen %a