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Differential D120300

[RISCV] Pre-commit tests for vcpop and vfirst with VL=0
ClosedPublic

Authored by Chenbing.Zheng on Feb 21 2022, 10:37 PM.

Details

Reviewers
craig.topper
frasercrmck
arcbbb
HsiangKai
benshi001
Commits
rG2aac00e4a685: [RISCV] Add more tests for vcpop and vfirst with VL=0
Summary

Pre-commit tests

Diff Detail

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
31 lines
31 lines

Diff 411006

llvm/test/CodeGen/RISCV/rvv/vcpop.ll

Show All 15 Lines
entry: entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1( %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret iXLen %a ret iXLen %a
} }
define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
iXLen 0)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1( declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind { define iXLen @intrinsic_vcpop_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1: ; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t ; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1( %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret iXLen %a ret iXLen %a
} }
define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen 0)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1( declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define iXLen @intrinsic_vcpop_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define iXLen @intrinsic_vcpop_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv2i1: ; CHECK-LABEL: intrinsic_vcpop_m_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfirst.ll

Show All 15 Lines
entry: entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1( %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret iXLen %a ret iXLen %a
} }
define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
iXLen 0)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1( declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind { define iXLen @intrinsic_vfirst_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1: ; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1( %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret iXLen %a ret iXLen %a
} }
define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen 0)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1( declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define iXLen @intrinsic_vfirst_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define iXLen @intrinsic_vfirst_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv2i1: ; CHECK-LABEL: intrinsic_vfirst_m_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines