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[RISCV] Add fixed-length vector instrinsics for segment load
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Authored by luke957 on Feb 15 2022, 5:12 AM.

Details

Summary

Add fixed-length vector instrinsics for segment load.
Inspired by reviews.llvm.org/D107790.
These fixed-length vector segNload instrinsics would be helpful to https://reviews.llvm.org/D107210.

Diff Detail

Event Timeline

luke957 created this revision.Feb 15 2022, 5:12 AM
luke957 requested review of this revision.Feb 15 2022, 5:12 AM
luke957 edited the summary of this revision. (Show Details)Feb 15 2022, 5:23 AM

Hi, any comments? :)

craig.topper added inline comments.Feb 22 2022, 11:33 PM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
4913

Unexcepted -> Unexpected

4921

You don't need a SmallVector, the number of items is fixed. You can use a plain array.

4925

I think you can do

SmallVector<EVT, 8> ContainerVTs(NF, ContainerVT);

and avoid the loop.

4935

Drop the curly braces around a single line body.

luke957 updated this revision to Diff 411120.Feb 24 2022, 7:16 AM

Address comments

luke957 updated this revision to Diff 411126.Feb 24 2022, 7:28 AM

Gently ping.

Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2022, 8:46 PM
craig.topper accepted this revision.Mar 7 2022, 3:13 PM

LGTM to me other than those 2 comments to change 8 to 9.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
4921

Use 9 instead of 8. Since NF is <= 8 and you push one additional item for MVT::Other.

4928

Use 9 instead of 8.

This revision is now accepted and ready to land.Mar 7 2022, 3:13 PM
This revision was landed with ongoing or failed builds.Mar 10 2022, 12:33 AM
This revision was automatically updated to reflect the committed changes.

Comments addressed before commit. Thanks.