[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.

[craig.topper]

Summary

Part of the shift lowering creates a (sub XLEN-1, ShAmt). When this
value is used we know that ShAmt is [0..XLEN-1]. Since XLEN is a power
of 2 we can replace the sub with an xor. This allows us to use XORI
instead of LI+SUB.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
   SDLoc DL(Op);
   SDValue Lo = Op.getOperand(0);
   SDValue Hi = Op.getOperand(1);
   SDValue Shamt = Op.getOperand(2);
   EVT VT = Lo.getValueType();
 
   // if Shamt-XLEN < 0: // Shamt < XLEN
   //   Lo = Lo << Shamt
-  //   Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt))
+  //   Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 ^ Shamt))
   // else:
   //   Lo = 0
   //   Hi = Lo << (Shamt-XLEN)
 
   SDValue Zero = DAG.getConstant(0, DL, VT);
   SDValue One = DAG.getConstant(1, DL, VT);
   SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
   SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
   SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
-  SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
+  SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1);
 
   SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
   SDValue ShiftRightLo =
       DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt);
   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
   SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
   SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen);
SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
   SDLoc DL(Op);
   SDValue Lo = Op.getOperand(0);
   SDValue Hi = Op.getOperand(1);
   SDValue Shamt = Op.getOperand(2);
   EVT VT = Lo.getValueType();
 
   // SRA expansion:
   //   if Shamt-XLEN < 0: // Shamt < XLEN
-  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
+  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ XLEN-1))
   //     Hi = Hi >>s Shamt
   //   else:
   //     Lo = Hi >>s (Shamt-XLEN);
   //     Hi = Hi >>s (XLEN-1)
   //
   // SRL expansion:
   //   if Shamt-XLEN < 0: // Shamt < XLEN
-  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
+  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ XLEN-1))
   //     Hi = Hi >>u Shamt
   //   else:
   //     Lo = Hi >>u (Shamt-XLEN);
   //     Hi = 0;
 
   unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
 
   SDValue Zero = DAG.getConstant(0, DL, VT);
   SDValue One = DAG.getConstant(1, DL, VT);
   SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
   SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
   SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
-  SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
+  SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1);
 
   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
   SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
   SDValue ShiftLeftHi =
       DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt);
   SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
   SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
   SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);

llvm/test/CodeGen/RISCV/alu64.ll

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB11_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sll a1, a0, a3
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB11_2:
 ; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    srli a4, a0, 1
 ; RV32I-NEXT:    srl a3, a4, a3
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    ret
   %1 = shl i64 %a, %b
   ret i64 %1
 }

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB15_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a3
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB15_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    slli a4, a1, 1
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    ret
   %1 = lshr i64 %a, %b
   ret i64 %1
 }

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB16_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sra a0, a1, a3
 ; RV32I-NEXT:    srai a1, a1, 31
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB16_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    slli a4, a1, 1
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    sra a1, a1, a2
 ; RV32I-NEXT:    ret
   %1 = ashr i64 %a, %b
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rotl-rotr.ll

; RV64ZBB-NEXT:    ret
   %c = shl i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i64 @rotl_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotl_64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    addi a5, a2, -32
-; RV32I-NEXT:    li a6, 31
+; RV32I-NEXT:    mv a4, a1
 ; RV32I-NEXT:    bltz a5, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sll a1, a0, a5
 ; RV32I-NEXT:    j .LBB2_3
 ; RV32I-NEXT:  .LBB2_2:
-; RV32I-NEXT:    sll a1, a3, a2
-; RV32I-NEXT:    sub a4, a6, a2
-; RV32I-NEXT:    srli a7, a0, 1
-; RV32I-NEXT:    srl a4, a7, a4
-; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    sll a1, a4, a2
+; RV32I-NEXT:    xori a3, a2, 31
+; RV32I-NEXT:    srli a6, a0, 1
+; RV32I-NEXT:    srl a3, a6, a3
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:  .LBB2_3:
-; RV32I-NEXT:    neg a7, a2
-; RV32I-NEXT:    li a4, 32
-; RV32I-NEXT:    sub t0, a4, a2
-; RV32I-NEXT:    srl a4, a3, a7
-; RV32I-NEXT:    bltz t0, .LBB2_6
+; RV32I-NEXT:    neg a6, a2
+; RV32I-NEXT:    li a3, 32
+; RV32I-NEXT:    sub a7, a3, a2
+; RV32I-NEXT:    srl a3, a4, a6
+; RV32I-NEXT:    bltz a7, .LBB2_6
 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    bltz a5, .LBB2_7
 ; RV32I-NEXT:  .LBB2_5:
-; RV32I-NEXT:    mv a0, a4
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB2_6:
-; RV32I-NEXT:    srl a7, a0, a7
-; RV32I-NEXT:    li t0, 64
-; RV32I-NEXT:    sub t0, t0, a2
-; RV32I-NEXT:    sub a6, a6, t0
-; RV32I-NEXT:    slli a3, a3, 1
-; RV32I-NEXT:    sll a3, a3, a6
-; RV32I-NEXT:    or a3, a7, a3
-; RV32I-NEXT:    or a1, a1, a4
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    srl a6, a0, a6
+; RV32I-NEXT:    li a7, 64
+; RV32I-NEXT:    sub a7, a7, a2
+; RV32I-NEXT:    xori a7, a7, 31
+; RV32I-NEXT:    slli a4, a4, 1
+; RV32I-NEXT:    sll a4, a4, a7
+; RV32I-NEXT:    or a4, a6, a4
+; RV32I-NEXT:    or a1, a1, a3
+; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    bgez a5, .LBB2_5
 ; RV32I-NEXT:  .LBB2_7:
 ; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    or a4, a4, a0
-; RV32I-NEXT:    mv a0, a4
+; RV32I-NEXT:    or a3, a3, a0
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    sll a1, a0, a1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_64:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    mv a3, a1
 ; RV32ZBB-NEXT:    addi a5, a2, -32
-; RV32ZBB-NEXT:    li a6, 31
+; RV32ZBB-NEXT:    mv a4, a1
 ; RV32ZBB-NEXT:    bltz a5, .LBB2_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    sll a1, a0, a5
 ; RV32ZBB-NEXT:    j .LBB2_3
 ; RV32ZBB-NEXT:  .LBB2_2:
-; RV32ZBB-NEXT:    sll a1, a3, a2
-; RV32ZBB-NEXT:    sub a4, a6, a2
-; RV32ZBB-NEXT:    srli a7, a0, 1
-; RV32ZBB-NEXT:    srl a4, a7, a4
-; RV32ZBB-NEXT:    or a1, a1, a4
+; RV32ZBB-NEXT:    sll a1, a4, a2
+; RV32ZBB-NEXT:    xori a3, a2, 31
+; RV32ZBB-NEXT:    srli a6, a0, 1
+; RV32ZBB-NEXT:    srl a3, a6, a3
+; RV32ZBB-NEXT:    or a1, a1, a3
 ; RV32ZBB-NEXT:  .LBB2_3:
-; RV32ZBB-NEXT:    neg a7, a2
-; RV32ZBB-NEXT:    li a4, 32
-; RV32ZBB-NEXT:    sub t0, a4, a2
-; RV32ZBB-NEXT:    srl a4, a3, a7
-; RV32ZBB-NEXT:    bltz t0, .LBB2_6
+; RV32ZBB-NEXT:    neg a6, a2
+; RV32ZBB-NEXT:    li a3, 32
+; RV32ZBB-NEXT:    sub a7, a3, a2
+; RV32ZBB-NEXT:    srl a3, a4, a6
+; RV32ZBB-NEXT:    bltz a7, .LBB2_6
 ; RV32ZBB-NEXT:  # %bb.4:
 ; RV32ZBB-NEXT:    bltz a5, .LBB2_7
 ; RV32ZBB-NEXT:  .LBB2_5:
-; RV32ZBB-NEXT:    mv a0, a4
+; RV32ZBB-NEXT:    mv a0, a3
 ; RV32ZBB-NEXT:    ret
 ; RV32ZBB-NEXT:  .LBB2_6:
-; RV32ZBB-NEXT:    srl a7, a0, a7
-; RV32ZBB-NEXT:    li t0, 64
-; RV32ZBB-NEXT:    sub t0, t0, a2
-; RV32ZBB-NEXT:    sub a6, a6, t0
-; RV32ZBB-NEXT:    slli a3, a3, 1
-; RV32ZBB-NEXT:    sll a3, a3, a6
-; RV32ZBB-NEXT:    or a3, a7, a3
-; RV32ZBB-NEXT:    or a1, a1, a4
-; RV32ZBB-NEXT:    mv a4, a3
+; RV32ZBB-NEXT:    srl a6, a0, a6
+; RV32ZBB-NEXT:    li a7, 64
+; RV32ZBB-NEXT:    sub a7, a7, a2
+; RV32ZBB-NEXT:    xori a7, a7, 31
+; RV32ZBB-NEXT:    slli a4, a4, 1
+; RV32ZBB-NEXT:    sll a4, a4, a7
+; RV32ZBB-NEXT:    or a4, a6, a4
+; RV32ZBB-NEXT:    or a1, a1, a3
+; RV32ZBB-NEXT:    mv a3, a4
 ; RV32ZBB-NEXT:    bgez a5, .LBB2_5
 ; RV32ZBB-NEXT:  .LBB2_7:
 ; RV32ZBB-NEXT:    sll a0, a0, a2
-; RV32ZBB-NEXT:    or a4, a4, a0
-; RV32ZBB-NEXT:    mv a0, a4
+; RV32ZBB-NEXT:    or a3, a3, a0
+; RV32ZBB-NEXT:    mv a0, a3
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %z = sub i64 64, %y
   %b = shl i64 %x, %y
   %c = lshr i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    addi a5, a2, -32
-; RV32I-NEXT:    li a6, 31
+; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    bltz a5, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a5
 ; RV32I-NEXT:    j .LBB3_3
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    srl a0, a4, a2
-; RV32I-NEXT:    sub a3, a6, a2
-; RV32I-NEXT:    slli a7, a1, 1
-; RV32I-NEXT:    sll a3, a7, a3
+; RV32I-NEXT:    xori a3, a2, 31
+; RV32I-NEXT:    slli a6, a1, 1
+; RV32I-NEXT:    sll a3, a6, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB3_3:
-; RV32I-NEXT:    neg a7, a2
+; RV32I-NEXT:    neg a6, a2
 ; RV32I-NEXT:    li a3, 32
-; RV32I-NEXT:    sub t0, a3, a2
-; RV32I-NEXT:    sll a3, a4, a7
-; RV32I-NEXT:    bltz t0, .LBB3_6
+; RV32I-NEXT:    sub a7, a3, a2
+; RV32I-NEXT:    sll a3, a4, a6
+; RV32I-NEXT:    bltz a7, .LBB3_6
 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    bltz a5, .LBB3_7
 ; RV32I-NEXT:  .LBB3_5:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB3_6:
-; RV32I-NEXT:    sll a7, a1, a7
-; RV32I-NEXT:    li t0, 64
-; RV32I-NEXT:    sub t0, t0, a2
-; RV32I-NEXT:    sub a6, a6, t0
+; RV32I-NEXT:    sll a6, a1, a6
+; RV32I-NEXT:    li a7, 64
+; RV32I-NEXT:    sub a7, a7, a2
+; RV32I-NEXT:    xori a7, a7, 31
 ; RV32I-NEXT:    srli a4, a4, 1
-; RV32I-NEXT:    srl a4, a4, a6
-; RV32I-NEXT:    or a4, a7, a4
+; RV32I-NEXT:    srl a4, a4, a7
+; RV32I-NEXT:    or a4, a6, a4
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    bgez a5, .LBB3_5
 ; RV32I-NEXT:  .LBB3_7:
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    or a3, a3, a1
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    srl a1, a0, a1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    mv a4, a0
 ; RV32ZBB-NEXT:    addi a5, a2, -32
-; RV32ZBB-NEXT:    li a6, 31
+; RV32ZBB-NEXT:    mv a4, a0
 ; RV32ZBB-NEXT:    bltz a5, .LBB3_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    srl a0, a1, a5
 ; RV32ZBB-NEXT:    j .LBB3_3
 ; RV32ZBB-NEXT:  .LBB3_2:
 ; RV32ZBB-NEXT:    srl a0, a4, a2
-; RV32ZBB-NEXT:    sub a3, a6, a2
-; RV32ZBB-NEXT:    slli a7, a1, 1
-; RV32ZBB-NEXT:    sll a3, a7, a3
+; RV32ZBB-NEXT:    xori a3, a2, 31
+; RV32ZBB-NEXT:    slli a6, a1, 1
+; RV32ZBB-NEXT:    sll a3, a6, a3
 ; RV32ZBB-NEXT:    or a0, a0, a3
 ; RV32ZBB-NEXT:  .LBB3_3:
-; RV32ZBB-NEXT:    neg a7, a2
+; RV32ZBB-NEXT:    neg a6, a2
 ; RV32ZBB-NEXT:    li a3, 32
-; RV32ZBB-NEXT:    sub t0, a3, a2
-; RV32ZBB-NEXT:    sll a3, a4, a7
-; RV32ZBB-NEXT:    bltz t0, .LBB3_6
+; RV32ZBB-NEXT:    sub a7, a3, a2
+; RV32ZBB-NEXT:    sll a3, a4, a6
+; RV32ZBB-NEXT:    bltz a7, .LBB3_6
 ; RV32ZBB-NEXT:  # %bb.4:
 ; RV32ZBB-NEXT:    bltz a5, .LBB3_7
 ; RV32ZBB-NEXT:  .LBB3_5:
 ; RV32ZBB-NEXT:    mv a1, a3
 ; RV32ZBB-NEXT:    ret
 ; RV32ZBB-NEXT:  .LBB3_6:
-; RV32ZBB-NEXT:    sll a7, a1, a7
-; RV32ZBB-NEXT:    li t0, 64
-; RV32ZBB-NEXT:    sub t0, t0, a2
-; RV32ZBB-NEXT:    sub a6, a6, t0
+; RV32ZBB-NEXT:    sll a6, a1, a6
+; RV32ZBB-NEXT:    li a7, 64
+; RV32ZBB-NEXT:    sub a7, a7, a2
+; RV32ZBB-NEXT:    xori a7, a7, 31
 ; RV32ZBB-NEXT:    srli a4, a4, 1
-; RV32ZBB-NEXT:    srl a4, a4, a6
-; RV32ZBB-NEXT:    or a4, a7, a4
+; RV32ZBB-NEXT:    srl a4, a4, a7
+; RV32ZBB-NEXT:    or a4, a6, a4
 ; RV32ZBB-NEXT:    or a0, a0, a3
 ; RV32ZBB-NEXT:    mv a3, a4
 ; RV32ZBB-NEXT:    bgez a5, .LBB3_5
 ; RV32ZBB-NEXT:  .LBB3_7:
 ; RV32ZBB-NEXT:    srl a1, a1, a2
 ; RV32ZBB-NEXT:    or a3, a3, a1
 ; RV32ZBB-NEXT:    mv a1, a3
 ; RV32ZBB-NEXT:    ret
; RV64ZBB-NEXT:    ret
   %c = shl i32 %x, %and
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotl_64_mask:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    addi a5, a2, -32
-; RV32I-NEXT:    li a4, 31
+; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    bltz a5, .LBB6_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sll a1, a0, a5
 ; RV32I-NEXT:    j .LBB6_3
 ; RV32I-NEXT:  .LBB6_2:
 ; RV32I-NEXT:    sll a1, a3, a2
-; RV32I-NEXT:    sub a6, a4, a2
-; RV32I-NEXT:    srli a7, a0, 1
-; RV32I-NEXT:    srl a6, a7, a6
-; RV32I-NEXT:    or a1, a1, a6
+; RV32I-NEXT:    xori a4, a2, 31
+; RV32I-NEXT:    srli a6, a0, 1
+; RV32I-NEXT:    srl a4, a6, a4
+; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:  .LBB6_3:
 ; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    andi a7, a6, 63
-; RV32I-NEXT:    addi t0, a7, -32
-; RV32I-NEXT:    bltz t0, .LBB6_5
+; RV32I-NEXT:    andi a4, a6, 63
+; RV32I-NEXT:    addi a7, a4, -32
+; RV32I-NEXT:    bltz a7, .LBB6_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    srl a4, a3, t0
+; RV32I-NEXT:    srl a4, a3, a7
 ; RV32I-NEXT:    bltz a5, .LBB6_6
 ; RV32I-NEXT:    j .LBB6_7
 ; RV32I-NEXT:  .LBB6_5:
-; RV32I-NEXT:    srl t0, a0, a6
-; RV32I-NEXT:    sub a4, a4, a7
-; RV32I-NEXT:    slli a7, a3, 1
-; RV32I-NEXT:    sll a4, a7, a4
-; RV32I-NEXT:    or a4, t0, a4
+; RV32I-NEXT:    srl a7, a0, a6
+; RV32I-NEXT:    xori a4, a4, 31
+; RV32I-NEXT:    slli t0, a3, 1
+; RV32I-NEXT:    sll a4, t0, a4
+; RV32I-NEXT:    or a4, a7, a4
 ; RV32I-NEXT:    srl a3, a3, a6
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    bgez a5, .LBB6_7
 ; RV32I-NEXT:  .LBB6_6:
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    or a4, a4, a0
 ; RV32I-NEXT:  .LBB6_7:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a2, a1
 ; RV64I-NEXT:    sll a1, a0, a1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_64_mask:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    mv a3, a1
 ; RV32ZBB-NEXT:    addi a5, a2, -32
-; RV32ZBB-NEXT:    li a4, 31
+; RV32ZBB-NEXT:    mv a3, a1
 ; RV32ZBB-NEXT:    bltz a5, .LBB6_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    sll a1, a0, a5
 ; RV32ZBB-NEXT:    j .LBB6_3
 ; RV32ZBB-NEXT:  .LBB6_2:
 ; RV32ZBB-NEXT:    sll a1, a3, a2
-; RV32ZBB-NEXT:    sub a6, a4, a2
-; RV32ZBB-NEXT:    srli a7, a0, 1
-; RV32ZBB-NEXT:    srl a6, a7, a6
-; RV32ZBB-NEXT:    or a1, a1, a6
+; RV32ZBB-NEXT:    xori a4, a2, 31
+; RV32ZBB-NEXT:    srli a6, a0, 1
+; RV32ZBB-NEXT:    srl a4, a6, a4
+; RV32ZBB-NEXT:    or a1, a1, a4
 ; RV32ZBB-NEXT:  .LBB6_3:
 ; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    andi a7, a6, 63
-; RV32ZBB-NEXT:    addi t0, a7, -32
-; RV32ZBB-NEXT:    bltz t0, .LBB6_5
+; RV32ZBB-NEXT:    andi a4, a6, 63
+; RV32ZBB-NEXT:    addi a7, a4, -32
+; RV32ZBB-NEXT:    bltz a7, .LBB6_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    srl a4, a3, t0
+; RV32ZBB-NEXT:    srl a4, a3, a7
 ; RV32ZBB-NEXT:    bltz a5, .LBB6_6
 ; RV32ZBB-NEXT:    j .LBB6_7
 ; RV32ZBB-NEXT:  .LBB6_5:
-; RV32ZBB-NEXT:    srl t0, a0, a6
-; RV32ZBB-NEXT:    sub a4, a4, a7
-; RV32ZBB-NEXT:    slli a7, a3, 1
-; RV32ZBB-NEXT:    sll a4, a7, a4
-; RV32ZBB-NEXT:    or a4, t0, a4
+; RV32ZBB-NEXT:    srl a7, a0, a6
+; RV32ZBB-NEXT:    xori a4, a4, 31
+; RV32ZBB-NEXT:    slli t0, a3, 1
+; RV32ZBB-NEXT:    sll a4, t0, a4
+; RV32ZBB-NEXT:    or a4, a7, a4
 ; RV32ZBB-NEXT:    srl a3, a3, a6
 ; RV32ZBB-NEXT:    or a1, a1, a3
 ; RV32ZBB-NEXT:    bgez a5, .LBB6_7
 ; RV32ZBB-NEXT:  .LBB6_6:
 ; RV32ZBB-NEXT:    sll a0, a0, a2
 ; RV32ZBB-NEXT:    or a4, a4, a0
 ; RV32ZBB-NEXT:  .LBB6_7:
 ; RV32ZBB-NEXT:    mv a0, a4
; RV64ZBB-NEXT:    ret
   %c = lshr i64 %x, %and
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64_mask:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    addi a5, a2, -32
-; RV32I-NEXT:    li a4, 31
+; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    bltz a5, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a5
 ; RV32I-NEXT:    j .LBB7_3
 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    srl a0, a3, a2
-; RV32I-NEXT:    sub a6, a4, a2
-; RV32I-NEXT:    slli a7, a1, 1
-; RV32I-NEXT:    sll a6, a7, a6
-; RV32I-NEXT:    or a0, a0, a6
+; RV32I-NEXT:    xori a4, a2, 31
+; RV32I-NEXT:    slli a6, a1, 1
+; RV32I-NEXT:    sll a4, a6, a4
+; RV32I-NEXT:    or a0, a0, a4
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    andi a7, a6, 63
-; RV32I-NEXT:    addi t0, a7, -32
-; RV32I-NEXT:    bltz t0, .LBB7_5
+; RV32I-NEXT:    andi a4, a6, 63
+; RV32I-NEXT:    addi a7, a4, -32
+; RV32I-NEXT:    bltz a7, .LBB7_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    sll a4, a3, t0
+; RV32I-NEXT:    sll a4, a3, a7
 ; RV32I-NEXT:    bltz a5, .LBB7_6
 ; RV32I-NEXT:    j .LBB7_7
 ; RV32I-NEXT:  .LBB7_5:
-; RV32I-NEXT:    sll t0, a1, a6
-; RV32I-NEXT:    sub a4, a4, a7
-; RV32I-NEXT:    srli a7, a3, 1
-; RV32I-NEXT:    srl a4, a7, a4
-; RV32I-NEXT:    or a4, t0, a4
+; RV32I-NEXT:    sll a7, a1, a6
+; RV32I-NEXT:    xori a4, a4, 31
+; RV32I-NEXT:    srli t0, a3, 1
+; RV32I-NEXT:    srl a4, t0, a4
+; RV32I-NEXT:    or a4, a7, a4
 ; RV32I-NEXT:    sll a3, a3, a6
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    bgez a5, .LBB7_7
 ; RV32I-NEXT:  .LBB7_6:
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    or a4, a4, a1
 ; RV32I-NEXT:  .LBB7_7:
 ; RV32I-NEXT:    mv a1, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a2, a1
 ; RV64I-NEXT:    srl a1, a0, a1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64_mask:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    mv a3, a0
 ; RV32ZBB-NEXT:    addi a5, a2, -32
-; RV32ZBB-NEXT:    li a4, 31
+; RV32ZBB-NEXT:    mv a3, a0
 ; RV32ZBB-NEXT:    bltz a5, .LBB7_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    srl a0, a1, a5
 ; RV32ZBB-NEXT:    j .LBB7_3
 ; RV32ZBB-NEXT:  .LBB7_2:
 ; RV32ZBB-NEXT:    srl a0, a3, a2
-; RV32ZBB-NEXT:    sub a6, a4, a2
-; RV32ZBB-NEXT:    slli a7, a1, 1
-; RV32ZBB-NEXT:    sll a6, a7, a6
-; RV32ZBB-NEXT:    or a0, a0, a6
+; RV32ZBB-NEXT:    xori a4, a2, 31
+; RV32ZBB-NEXT:    slli a6, a1, 1
+; RV32ZBB-NEXT:    sll a4, a6, a4
+; RV32ZBB-NEXT:    or a0, a0, a4
 ; RV32ZBB-NEXT:  .LBB7_3:
 ; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    andi a7, a6, 63
-; RV32ZBB-NEXT:    addi t0, a7, -32
-; RV32ZBB-NEXT:    bltz t0, .LBB7_5
+; RV32ZBB-NEXT:    andi a4, a6, 63
+; RV32ZBB-NEXT:    addi a7, a4, -32
+; RV32ZBB-NEXT:    bltz a7, .LBB7_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    sll a4, a3, t0
+; RV32ZBB-NEXT:    sll a4, a3, a7
 ; RV32ZBB-NEXT:    bltz a5, .LBB7_6
 ; RV32ZBB-NEXT:    j .LBB7_7
 ; RV32ZBB-NEXT:  .LBB7_5:
-; RV32ZBB-NEXT:    sll t0, a1, a6
-; RV32ZBB-NEXT:    sub a4, a4, a7
-; RV32ZBB-NEXT:    srli a7, a3, 1
-; RV32ZBB-NEXT:    srl a4, a7, a4
-; RV32ZBB-NEXT:    or a4, t0, a4
+; RV32ZBB-NEXT:    sll a7, a1, a6
+; RV32ZBB-NEXT:    xori a4, a4, 31
+; RV32ZBB-NEXT:    srli t0, a3, 1
+; RV32ZBB-NEXT:    srl a4, t0, a4
+; RV32ZBB-NEXT:    or a4, a7, a4
 ; RV32ZBB-NEXT:    sll a3, a3, a6
 ; RV32ZBB-NEXT:    or a0, a0, a3
 ; RV32ZBB-NEXT:    bgez a5, .LBB7_7
 ; RV32ZBB-NEXT:  .LBB7_6:
 ; RV32ZBB-NEXT:    srl a1, a1, a2
 ; RV32ZBB-NEXT:    or a4, a4, a1
 ; RV32ZBB-NEXT:  .LBB7_7:
 ; RV32ZBB-NEXT:    mv a1, a4

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32I-NEXT:    andi a3, a2, 63
 ; RV32I-NEXT:    addi a4, a3, -32
 ; RV32I-NEXT:    bltz a4, .LBB12_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a4
 ; RV32I-NEXT:    j .LBB12_3
 ; RV32I-NEXT:  .LBB12_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a2, 31
-; RV32I-NEXT:    sub a2, a2, a3
 ; RV32I-NEXT:    slli a1, a1, 1
+; RV32I-NEXT:    xori a2, a3, 31
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB12_3:
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bext_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a3, a2, 63
 ; RV32ZBS-NEXT:    addi a4, a3, -32
 ; RV32ZBS-NEXT:    bltz a4, .LBB12_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    srl a0, a1, a4
 ; RV32ZBS-NEXT:    j .LBB12_3
 ; RV32ZBS-NEXT:  .LBB12_2:
 ; RV32ZBS-NEXT:    srl a0, a0, a2
-; RV32ZBS-NEXT:    li a2, 31
-; RV32ZBS-NEXT:    sub a2, a2, a3
 ; RV32ZBS-NEXT:    slli a1, a1, 1
+; RV32ZBS-NEXT:    xori a2, a3, 31
 ; RV32ZBS-NEXT:    sll a1, a1, a2
 ; RV32ZBS-NEXT:    or a0, a0, a1
 ; RV32ZBS-NEXT:  .LBB12_3:
 ; RV32ZBS-NEXT:    andi a0, a0, 1
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
   %conv = and i64 %b, 63
   %shr = lshr i64 %a, %conv

llvm/test/CodeGen/RISCV/shift-masked-shamt.ll

 ; RV32I-NEXT:    addi a4, a3, -32
 ; RV32I-NEXT:    bltz a4, .LBB9_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sll a1, a0, a4
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB9_2:
 ; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    li a4, 31
-; RV32I-NEXT:    sub a3, a4, a3
 ; RV32I-NEXT:    srli a4, a0, 1
+; RV32I-NEXT:    xori a3, a3, 31
 ; RV32I-NEXT:    srl a3, a4, a3
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sll_redundant_mask_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 2

 ; RV32I-NEXT:    addi a4, a3, -32
 ; RV32I-NEXT:    bltz a4, .LBB10_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a4
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB10_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a4, 31
-; RV32I-NEXT:    sub a3, a4, a3
 ; RV32I-NEXT:    slli a4, a1, 1
+; RV32I-NEXT:    xori a3, a3, 31
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: srl_redundant_mask_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 3

 ; RV32I-NEXT:    addi a4, a3, -32
 ; RV32I-NEXT:    bltz a4, .LBB11_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sra a0, a1, a4
 ; RV32I-NEXT:    srai a1, a1, 31
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB11_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a4, 31
-; RV32I-NEXT:    sub a3, a4, a3
 ; RV32I-NEXT:    slli a4, a1, 1
+; RV32I-NEXT:    xori a3, a3, 31
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    sra a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sra_redundant_mask_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 4
 ; RV64I-NEXT:    sra a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = shl i64 %b, 4
   %2 = and i64 %1, 48
   %3 = ashr i64 %a, %2
   ret i64 %3
 }

llvm/test/CodeGen/RISCV/shifts.ll

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a0, a1, a3
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    slli a4, a1, 1
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: lshr64:
 ; RV64I:       # %bb.0:

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sra a0, a1, a3
 ; RV32I-NEXT:    srai a1, a1, 31
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    srl a0, a0, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    slli a4, a1, 1
 ; RV32I-NEXT:    sll a3, a4, a3
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    sra a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: ashr64:
 ; RV64I:       # %bb.0:

 ; RV32I-NEXT:    addi a3, a2, -32
 ; RV32I-NEXT:    bltz a3, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sll a1, a0, a3
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    sll a1, a1, a2
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a2
+; RV32I-NEXT:    xori a3, a2, 31
 ; RV32I-NEXT:    srli a4, a0, 1
 ; RV32I-NEXT:    srl a3, a4, a3
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: shl64:
 ; RV64I:       # %bb.0:

 define i128 @lshr128(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: lshr128:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a2, 0(a2)
 ; RV32I-NEXT:    lw a5, 8(a1)
 ; RV32I-NEXT:    lw a4, 12(a1)
 ; RV32I-NEXT:    neg a6, a2
 ; RV32I-NEXT:    li a3, 64
-; RV32I-NEXT:    li t2, 31
 ; RV32I-NEXT:    li a7, 32
 ; RV32I-NEXT:    sub t1, a7, a2
 ; RV32I-NEXT:    sll t0, a5, a6
 ; RV32I-NEXT:    bltz t1, .LBB6_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv t6, t0
+; RV32I-NEXT:    mv t2, t0
 ; RV32I-NEXT:    j .LBB6_3
 ; RV32I-NEXT:  .LBB6_2:
 ; RV32I-NEXT:    sll a6, a4, a6
 ; RV32I-NEXT:    sub a7, a3, a2
-; RV32I-NEXT:    sub a7, t2, a7
-; RV32I-NEXT:    srli t3, a5, 1
-; RV32I-NEXT:    srl a7, t3, a7
-; RV32I-NEXT:    or t6, a6, a7
+; RV32I-NEXT:    xori a7, a7, 31
+; RV32I-NEXT:    srli t2, a5, 1
+; RV32I-NEXT:    srl a7, t2, a7
+; RV32I-NEXT:    or t2, a6, a7
 ; RV32I-NEXT:  .LBB6_3:
 ; RV32I-NEXT:    lw t5, 4(a1)
 ; RV32I-NEXT:    addi a6, a2, -32
 ; RV32I-NEXT:    bgez a6, .LBB6_5
 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    srl a7, t5, a2
-; RV32I-NEXT:    or t6, t6, a7
+; RV32I-NEXT:    or t2, t2, a7
 ; RV32I-NEXT:  .LBB6_5:
 ; RV32I-NEXT:    addi t4, a2, -96
 ; RV32I-NEXT:    addi t3, a2, -64
 ; RV32I-NEXT:    bltz t4, .LBB6_7
 ; RV32I-NEXT:  # %bb.6:
 ; RV32I-NEXT:    li a7, 0
 ; RV32I-NEXT:    bgeu a2, a3, .LBB6_8
 ; RV32I-NEXT:    j .LBB6_9
 ; RV32I-NEXT:  .LBB6_7:
 ; RV32I-NEXT:    srl a7, a4, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB6_9
 ; RV32I-NEXT:  .LBB6_8:
-; RV32I-NEXT:    mv t6, a7
+; RV32I-NEXT:    mv t2, a7
 ; RV32I-NEXT:  .LBB6_9:
 ; RV32I-NEXT:    mv a7, t5
 ; RV32I-NEXT:    beqz a2, .LBB6_11
 ; RV32I-NEXT:  # %bb.10:
-; RV32I-NEXT:    mv a7, t6
+; RV32I-NEXT:    mv a7, t2
 ; RV32I-NEXT:  .LBB6_11:
 ; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    sub t2, t2, a2
+; RV32I-NEXT:    xori t2, a2, 31
 ; RV32I-NEXT:    bltz a6, .LBB6_13
 ; RV32I-NEXT:  # %bb.12:
 ; RV32I-NEXT:    srl t5, t5, a6
 ; RV32I-NEXT:    bltz t1, .LBB6_14
 ; RV32I-NEXT:    j .LBB6_15
 ; RV32I-NEXT:  .LBB6_13:
 ; RV32I-NEXT:    srl t6, a1, a2
 ; RV32I-NEXT:    slli t5, t5, 1
 ; RV32I-NEXT:    sll t5, t5, t2
 ; RV32I-NEXT:    or t5, t6, t5
 ; RV32I-NEXT:    bgez t1, .LBB6_15
 ; RV32I-NEXT:  .LBB6_14:
 ; RV32I-NEXT:    or t5, t5, t0
 ; RV32I-NEXT:  .LBB6_15:
 ; RV32I-NEXT:    slli t0, a4, 1
 ; RV32I-NEXT:    bltz t4, .LBB6_17
 ; RV32I-NEXT:  # %bb.16:
 ; RV32I-NEXT:    srl t1, a4, t4
 ; RV32I-NEXT:    bgeu a2, a3, .LBB6_18
 ; RV32I-NEXT:    j .LBB6_19
 ; RV32I-NEXT:  .LBB6_17:
-; RV32I-NEXT:    li t1, 95
-; RV32I-NEXT:    sub t1, t1, a2
-; RV32I-NEXT:    sll t1, t0, t1
-; RV32I-NEXT:    srl t3, a5, t3
-; RV32I-NEXT:    or t1, t3, t1
+; RV32I-NEXT:    srl t1, a5, t3
+; RV32I-NEXT:    xori t3, t3, 31
+; RV32I-NEXT:    sll t3, t0, t3
+; RV32I-NEXT:    or t1, t1, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB6_19
 ; RV32I-NEXT:  .LBB6_18:
 ; RV32I-NEXT:    mv t5, t1
 ; RV32I-NEXT:  .LBB6_19:
 ; RV32I-NEXT:    bnez a2, .LBB6_22
 ; RV32I-NEXT:  # %bb.20:
 ; RV32I-NEXT:    bltz a6, .LBB6_23
 ; RV32I-NEXT:  .LBB6_21:

 ; RV64I-NEXT:    addi a3, a2, -64
 ; RV64I-NEXT:    bltz a3, .LBB6_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srl a0, a1, a3
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB6_2:
 ; RV64I-NEXT:    srl a0, a0, a2
-; RV64I-NEXT:    li a3, 63
-; RV64I-NEXT:    sub a3, a3, a2
+; RV64I-NEXT:    xori a3, a2, 63
 ; RV64I-NEXT:    slli a4, a1, 1
 ; RV64I-NEXT:    sll a3, a4, a3
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    srl a1, a1, a2
 ; RV64I-NEXT:    ret
   %1 = lshr i128 %a, %b
   ret i128 %1
 }
 
 define i128 @ashr128(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: ashr128:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a2, 0(a2)
 ; RV32I-NEXT:    lw a5, 8(a1)
 ; RV32I-NEXT:    lw a4, 12(a1)
 ; RV32I-NEXT:    neg a6, a2
 ; RV32I-NEXT:    li a3, 64
-; RV32I-NEXT:    li t3, 31
 ; RV32I-NEXT:    li a7, 32
 ; RV32I-NEXT:    sub t2, a7, a2
 ; RV32I-NEXT:    sll t1, a5, a6
 ; RV32I-NEXT:    bltz t2, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv s0, t1
+; RV32I-NEXT:    mv t4, t1
 ; RV32I-NEXT:    j .LBB7_3
 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    sll a6, a4, a6
 ; RV32I-NEXT:    sub a7, a3, a2
-; RV32I-NEXT:    sub a7, t3, a7
+; RV32I-NEXT:    xori a7, a7, 31
 ; RV32I-NEXT:    srli t0, a5, 1
 ; RV32I-NEXT:    srl a7, t0, a7
-; RV32I-NEXT:    or s0, a6, a7
+; RV32I-NEXT:    or t4, a6, a7
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    lw t6, 4(a1)
 ; RV32I-NEXT:    addi a6, a2, -32
 ; RV32I-NEXT:    bgez a6, .LBB7_5
 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    srl a7, t6, a2
-; RV32I-NEXT:    or s0, s0, a7
+; RV32I-NEXT:    or t4, t4, a7
 ; RV32I-NEXT:  .LBB7_5:
-; RV32I-NEXT:    addi t4, a2, -64
+; RV32I-NEXT:    addi t3, a2, -64
 ; RV32I-NEXT:    addi t5, a2, -96
 ; RV32I-NEXT:    srai a7, a4, 31
 ; RV32I-NEXT:    bltz t5, .LBB7_7
 ; RV32I-NEXT:  # %bb.6:
 ; RV32I-NEXT:    mv t0, a7
 ; RV32I-NEXT:    bgeu a2, a3, .LBB7_8
 ; RV32I-NEXT:    j .LBB7_9
 ; RV32I-NEXT:  .LBB7_7:
-; RV32I-NEXT:    sra t0, a4, t4
+; RV32I-NEXT:    sra t0, a4, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB7_9
 ; RV32I-NEXT:  .LBB7_8:
-; RV32I-NEXT:    mv s0, t0
+; RV32I-NEXT:    mv t4, t0
 ; RV32I-NEXT:  .LBB7_9:
 ; RV32I-NEXT:    mv t0, t6
 ; RV32I-NEXT:    beqz a2, .LBB7_11
 ; RV32I-NEXT:  # %bb.10:
-; RV32I-NEXT:    mv t0, s0
+; RV32I-NEXT:    mv t0, t4
 ; RV32I-NEXT:  .LBB7_11:
 ; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    sub t3, t3, a2
+; RV32I-NEXT:    xori t4, a2, 31
 ; RV32I-NEXT:    bltz a6, .LBB7_13
 ; RV32I-NEXT:  # %bb.12:
 ; RV32I-NEXT:    srl t6, t6, a6
 ; RV32I-NEXT:    bltz t2, .LBB7_14
 ; RV32I-NEXT:    j .LBB7_15
 ; RV32I-NEXT:  .LBB7_13:
 ; RV32I-NEXT:    srl s0, a1, a2
 ; RV32I-NEXT:    slli t6, t6, 1
-; RV32I-NEXT:    sll t6, t6, t3
+; RV32I-NEXT:    sll t6, t6, t4
 ; RV32I-NEXT:    or t6, s0, t6
 ; RV32I-NEXT:    bgez t2, .LBB7_15
 ; RV32I-NEXT:  .LBB7_14:
 ; RV32I-NEXT:    or t6, t6, t1
 ; RV32I-NEXT:  .LBB7_15:
 ; RV32I-NEXT:    slli t1, a4, 1
 ; RV32I-NEXT:    bltz t5, .LBB7_17
 ; RV32I-NEXT:  # %bb.16:
 ; RV32I-NEXT:    sra t2, a4, t5
 ; RV32I-NEXT:    bgeu a2, a3, .LBB7_18
 ; RV32I-NEXT:    j .LBB7_19
 ; RV32I-NEXT:  .LBB7_17:
-; RV32I-NEXT:    li t2, 95
-; RV32I-NEXT:    sub t2, t2, a2
-; RV32I-NEXT:    sll t2, t1, t2
-; RV32I-NEXT:    srl t4, a5, t4
-; RV32I-NEXT:    or t2, t4, t2
+; RV32I-NEXT:    srl t2, a5, t3
+; RV32I-NEXT:    xori t3, t3, 31
+; RV32I-NEXT:    sll t3, t1, t3
+; RV32I-NEXT:    or t2, t2, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB7_19
 ; RV32I-NEXT:  .LBB7_18:
 ; RV32I-NEXT:    mv t6, t2
 ; RV32I-NEXT:  .LBB7_19:
 ; RV32I-NEXT:    bnez a2, .LBB7_22
 ; RV32I-NEXT:  # %bb.20:
 ; RV32I-NEXT:    bltz a6, .LBB7_23
 ; RV32I-NEXT:  .LBB7_21:
 ; RV32I-NEXT:    sra a5, a4, a6
 ; RV32I-NEXT:    bgeu a2, a3, .LBB7_24
 ; RV32I-NEXT:    j .LBB7_25
 ; RV32I-NEXT:  .LBB7_22:
 ; RV32I-NEXT:    mv a1, t6
 ; RV32I-NEXT:    bgez a6, .LBB7_21
 ; RV32I-NEXT:  .LBB7_23:
 ; RV32I-NEXT:    srl a5, a5, a2
-; RV32I-NEXT:    sll t1, t1, t3
+; RV32I-NEXT:    sll t1, t1, t4
 ; RV32I-NEXT:    or a5, a5, t1
 ; RV32I-NEXT:    bltu a2, a3, .LBB7_25
 ; RV32I-NEXT:  .LBB7_24:
 ; RV32I-NEXT:    mv a5, a7
 ; RV32I-NEXT:  .LBB7_25:
 ; RV32I-NEXT:    bltz a6, .LBB7_27
 ; RV32I-NEXT:  # %bb.26:
 ; RV32I-NEXT:    mv a4, a7

 ; RV64I-NEXT:    addi a3, a2, -64
 ; RV64I-NEXT:    bltz a3, .LBB7_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    sra a0, a1, a3
 ; RV64I-NEXT:    srai a1, a1, 63
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB7_2:
 ; RV64I-NEXT:    srl a0, a0, a2
-; RV64I-NEXT:    li a3, 63
-; RV64I-NEXT:    sub a3, a3, a2
+; RV64I-NEXT:    xori a3, a2, 63
 ; RV64I-NEXT:    slli a4, a1, 1
 ; RV64I-NEXT:    sll a3, a4, a3
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    sra a1, a1, a2
 ; RV64I-NEXT:    ret
   %1 = ashr i128 %a, %b
   ret i128 %1
 }
 
 define i128 @shl128(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: shl128:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a2, 0(a2)
 ; RV32I-NEXT:    lw a5, 4(a1)
 ; RV32I-NEXT:    lw a4, 0(a1)
 ; RV32I-NEXT:    neg a6, a2
 ; RV32I-NEXT:    li a3, 64
-; RV32I-NEXT:    li t2, 31
 ; RV32I-NEXT:    li a7, 32
 ; RV32I-NEXT:    sub t1, a7, a2
 ; RV32I-NEXT:    srl t0, a5, a6
 ; RV32I-NEXT:    bltz t1, .LBB8_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv t6, t0
+; RV32I-NEXT:    mv t2, t0
 ; RV32I-NEXT:    j .LBB8_3
 ; RV32I-NEXT:  .LBB8_2:
 ; RV32I-NEXT:    srl a6, a4, a6
 ; RV32I-NEXT:    sub a7, a3, a2
-; RV32I-NEXT:    sub a7, t2, a7
-; RV32I-NEXT:    slli t3, a5, 1
-; RV32I-NEXT:    sll a7, t3, a7
-; RV32I-NEXT:    or t6, a6, a7
+; RV32I-NEXT:    xori a7, a7, 31
+; RV32I-NEXT:    slli t2, a5, 1
+; RV32I-NEXT:    sll a7, t2, a7
+; RV32I-NEXT:    or t2, a6, a7
 ; RV32I-NEXT:  .LBB8_3:
 ; RV32I-NEXT:    lw t5, 8(a1)
 ; RV32I-NEXT:    addi a6, a2, -32
 ; RV32I-NEXT:    bgez a6, .LBB8_5
 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    sll a7, t5, a2
-; RV32I-NEXT:    or t6, t6, a7
+; RV32I-NEXT:    or t2, t2, a7
 ; RV32I-NEXT:  .LBB8_5:
 ; RV32I-NEXT:    addi t4, a2, -96
 ; RV32I-NEXT:    addi t3, a2, -64
 ; RV32I-NEXT:    bltz t4, .LBB8_7
 ; RV32I-NEXT:  # %bb.6:
 ; RV32I-NEXT:    li a7, 0
 ; RV32I-NEXT:    bgeu a2, a3, .LBB8_8
 ; RV32I-NEXT:    j .LBB8_9
 ; RV32I-NEXT:  .LBB8_7:
 ; RV32I-NEXT:    sll a7, a4, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB8_9
 ; RV32I-NEXT:  .LBB8_8:
-; RV32I-NEXT:    mv t6, a7
+; RV32I-NEXT:    mv t2, a7
 ; RV32I-NEXT:  .LBB8_9:
 ; RV32I-NEXT:    mv a7, t5
 ; RV32I-NEXT:    beqz a2, .LBB8_11
 ; RV32I-NEXT:  # %bb.10:
-; RV32I-NEXT:    mv a7, t6
+; RV32I-NEXT:    mv a7, t2
 ; RV32I-NEXT:  .LBB8_11:
 ; RV32I-NEXT:    lw a1, 12(a1)
-; RV32I-NEXT:    sub t2, t2, a2
+; RV32I-NEXT:    xori t2, a2, 31
 ; RV32I-NEXT:    bltz a6, .LBB8_13
 ; RV32I-NEXT:  # %bb.12:
 ; RV32I-NEXT:    sll t5, t5, a6
 ; RV32I-NEXT:    bltz t1, .LBB8_14
 ; RV32I-NEXT:    j .LBB8_15
 ; RV32I-NEXT:  .LBB8_13:
 ; RV32I-NEXT:    sll t6, a1, a2
 ; RV32I-NEXT:    srli t5, t5, 1
 ; RV32I-NEXT:    srl t5, t5, t2
 ; RV32I-NEXT:    or t5, t6, t5
 ; RV32I-NEXT:    bgez t1, .LBB8_15
 ; RV32I-NEXT:  .LBB8_14:
 ; RV32I-NEXT:    or t5, t5, t0
 ; RV32I-NEXT:  .LBB8_15:
 ; RV32I-NEXT:    srli t0, a4, 1
 ; RV32I-NEXT:    bltz t4, .LBB8_17
 ; RV32I-NEXT:  # %bb.16:
 ; RV32I-NEXT:    sll t1, a4, t4
 ; RV32I-NEXT:    bgeu a2, a3, .LBB8_18
 ; RV32I-NEXT:    j .LBB8_19
 ; RV32I-NEXT:  .LBB8_17:
-; RV32I-NEXT:    li t1, 95
-; RV32I-NEXT:    sub t1, t1, a2
-; RV32I-NEXT:    srl t1, t0, t1
-; RV32I-NEXT:    sll t3, a5, t3
-; RV32I-NEXT:    or t1, t3, t1
+; RV32I-NEXT:    sll t1, a5, t3
+; RV32I-NEXT:    xori t3, t3, 31
+; RV32I-NEXT:    srl t3, t0, t3
+; RV32I-NEXT:    or t1, t1, t3
 ; RV32I-NEXT:    bltu a2, a3, .LBB8_19
 ; RV32I-NEXT:  .LBB8_18:
 ; RV32I-NEXT:    mv t5, t1
 ; RV32I-NEXT:  .LBB8_19:
 ; RV32I-NEXT:    bnez a2, .LBB8_22
 ; RV32I-NEXT:  # %bb.20:
 ; RV32I-NEXT:    bltz a6, .LBB8_23
 ; RV32I-NEXT:  .LBB8_21:

 ; RV64I-NEXT:    addi a3, a2, -64
 ; RV64I-NEXT:    bltz a3, .LBB8_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    sll a1, a0, a3
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB8_2:
 ; RV64I-NEXT:    sll a1, a1, a2
-; RV64I-NEXT:    li a3, 63
-; RV64I-NEXT:    sub a3, a3, a2
+; RV64I-NEXT:    xori a3, a2, 63
 ; RV64I-NEXT:    srli a4, a0, 1
 ; RV64I-NEXT:    srl a3, a4, a3
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    ret
   %1 = shl i128 %a, %b
   ret i128 %1
 }