m68k: Support bit shifts on 64-bit integers

[0x59616e]

Summary

As per https://bugs.llvm.org/show_bug.cgi?id=52119.

[jrtc27]

llvm/test/CodeGen/M68k/Arith/bitwise.ll

235

Regenerate the CHECK lines

[AnnikaCodes]

Regenerate CHECKs

[AnnikaCodes]

llvm/test/CodeGen/M68k/Arith/bitwise.ll

235

OK.

[jrtc27]

llvm/test/CodeGen/M68k/Arith/bitwise.ll

241

Hm now why is this being turned into a libcall, I'd expect Expand to inline it. RISC-V has custom lowering you could copy, but that lowering looks pretty generic (just turn XLEN into the width of the first operand).

[AnnikaCodes]

Use RISC-V's custom lowering

[AnnikaCodes]

Use RISC-V's custom lowering

(oops I used arc wrong, sorry)

[AnnikaCodes]

llvm/test/CodeGen/M68k/Arith/bitwise.ll

241

Yeah, the custom lowering does away with the call.

[AnnikaCodes]

Fix formatting

3 Updating D111497: m68k: Support bit shifts on 64-bit integers

[AnnikaCodes]

Fix Polly checks

(just needed to rebase; I guess the issue wasn't in my changes)

[AnnikaCodes]

llvm/lib/Target/M68k/M68kISelLowering.cpp

3368

These other changes are because I ran clang-format on the file; it's syntactically the same.

[myhsu]

llvm/lib/Target/M68k/M68kISelLowering.cpp

104

Please remove curly brace if there is only one statement in for-loop.

385

I feel like this is modified by clang-format. Can you format only the part you changed using clang/tools/clang-format/clang-format-diff.py

3368

ditto, please use clang-format-diff.py instead

[AnnikaCodes]

Properly format code

[AnnikaCodes]

Fix for loop

[AnnikaCodes]

ok, I reformatted it; hopefully I did it correctly this time.

[jrtc27]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1321

Keep order in this file consistent with the header

1329

XLEN is a RISC-V-specific term, referring to the size of its X registers

llvm/lib/Target/M68k/M68kISelLowering.h

138

Don't group with LowerOperation, and put these with all the other LowerX in the private section below (maybe in the same order as the LowerOperation switch?)

[AnnikaCodes]

• Remove references to XLen and reorder code

[AnnikaCodes]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1329

Oh, sorry; I didn't know that.

[myhsu]

LGTM
Thank you!

llvm/lib/Target/M68k/M68kISelLowering.cpp

3314

Appreciate the explanations here :-)

[glaubitz]

Could someone land this?

[ricky26]

I'm happy to. Are you ready for this to land @AnnikaCodes?

[AnnikaCodes]

In D111497#3077640, @ricky26 wrote:

I'm happy to. Are you ready for this to land @AnnikaCodes?

Yeah, I think it's ready.

[ricky26]

@AnnikaCodes, I'm seeing test failures from this patch. It looks like it's generating SETCC nodes which don't return i8 (which the M68k requires).

FAIL: LLVM :: CodeGen/M68k/Arith/bitwise.ll (315 of 45926)
******************** TEST 'LLVM :: CodeGen/M68k/Arith/bitwise.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc < /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll -mtriple=m68k-linux -verify-machineinstrs | /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/FileCheck /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll
--
Exit Code: 1

Command Output (stderr):
--
llc: /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:1914: llvm::SDValue llvm::M68kTargetLowering::LowerSETCC(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `VT == MVT::i8 && "SetCC type must be 8-bit integer"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc -mtriple=m68k-linux -verify-machineinstrs
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'M68k DAG->DAG Pattern Instruction Selection' on function '@lshr64'
-snip-
 #8 0x0000557b6ce29aee llvm::M68kTargetLowering::LowerSETCC(llvm::SDValue, llvm::SelectionDAG&) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:1976:1
 #9 0x0000557b6ce2a251 llvm::M68kTargetLowering::LowerSELECT(llvm::SDValue, llvm::SelectionDAG&) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:2039:5
#10 0x0000557b6dde95a0 (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*) /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1281:43

I checked the debug output:

Legalizing: t24: i32,i32 = srl_parts t5, t3, t9
Trying custom legalization
Creating constant: t25: i32 = Constant<0>
Creating constant: t26: i32 = Constant<1>
Creating constant: t27: i32 = Constant<-32>
Creating constant: t28: i32 = Constant<31>
Creating new node: t29: i32 = add t9, Constant:i32<-32>
Creating new node: t30: i32 = sub Constant:i32<31>, t9
Creating new node: t31: i32 = srl t5, t9
Creating new node: t32: i32 = shl t3, Constant:i32<1>
Creating new node: t33: i32 = shl t32, t30
Creating new node: t34: i32 = or t31, t33
Creating new node: t35: i32 = srl t3, t9
Creating new node: t36: i32 = srl t3, t29
Creating new node: t38: i32 = setcc t29, Constant:i32<0>, setlt:ch
Creating new node: t39: i32 = select t38, t34, t36
Creating new node: t40: i32 = select t38, t35, Constant:i32<0>
Creating new node: t41: i32,i32 = merge_values t39, t40
Successfully custom legalized node
 ... replacing: t24: i32,i32 = srl_parts t5, t3, t9
     with:      t41: i32,i32 = merge_values t39, t40
      and:      t41: i32,i32 = merge_values t39, t40

If I understand correctly, I think the only issue is that t38 returns i32 instead of i8.

It might be as simple as making it so that the getSetCC calls use MVT::i8 instead of the input VT.

[jrtc27]

In D111497#3079635, @ricky26 wrote:

@AnnikaCodes, I'm seeing test failures from this patch. It looks like it's generating SETCC nodes which don't return i8 (which the M68k requires).

FAIL: LLVM :: CodeGen/M68k/Arith/bitwise.ll (315 of 45926)
******************** TEST 'LLVM :: CodeGen/M68k/Arith/bitwise.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc < /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll -mtriple=m68k-linux -verify-machineinstrs | /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/FileCheck /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll
--
Exit Code: 1

Command Output (stderr):
--
llc: /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:1914: llvm::SDValue llvm::M68kTargetLowering::LowerSETCC(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `VT == MVT::i8 && "SetCC type must be 8-bit integer"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc -mtriple=m68k-linux -verify-machineinstrs
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'M68k DAG->DAG Pattern Instruction Selection' on function '@lshr64'
-snip-
 #8 0x0000557b6ce29aee llvm::M68kTargetLowering::LowerSETCC(llvm::SDValue, llvm::SelectionDAG&) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:1976:1
 #9 0x0000557b6ce2a251 llvm::M68kTargetLowering::LowerSELECT(llvm::SDValue, llvm::SelectionDAG&) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kISelLowering.cpp:2039:5
#10 0x0000557b6dde95a0 (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*) /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1281:43

I checked the debug output:

Legalizing: t24: i32,i32 = srl_parts t5, t3, t9
Trying custom legalization
Creating constant: t25: i32 = Constant<0>
Creating constant: t26: i32 = Constant<1>
Creating constant: t27: i32 = Constant<-32>
Creating constant: t28: i32 = Constant<31>
Creating new node: t29: i32 = add t9, Constant:i32<-32>
Creating new node: t30: i32 = sub Constant:i32<31>, t9
Creating new node: t31: i32 = srl t5, t9
Creating new node: t32: i32 = shl t3, Constant:i32<1>
Creating new node: t33: i32 = shl t32, t30
Creating new node: t34: i32 = or t31, t33
Creating new node: t35: i32 = srl t3, t9
Creating new node: t36: i32 = srl t3, t29
Creating new node: t38: i32 = setcc t29, Constant:i32<0>, setlt:ch
Creating new node: t39: i32 = select t38, t34, t36
Creating new node: t40: i32 = select t38, t35, Constant:i32<0>
Creating new node: t41: i32,i32 = merge_values t39, t40
Successfully custom legalized node
 ... replacing: t24: i32,i32 = srl_parts t5, t3, t9
     with:      t41: i32,i32 = merge_values t39, t40
      and:      t41: i32,i32 = merge_values t39, t40

If I understand correctly, I think the only issue is that t38 returns i32 instead of i8.

It might be as simple as making it so that the getSetCC calls use MVT::i8 instead of the input VT.

That sounds right. On RISC-V, XLenVT is the only legal integer type, and thus what is used by getSetCCResultType (ignoring vectorisation), whereas M68k's returns i8, something I missed when outlining how to generalise the RISC-V implementation.

[AnnikaCodes]

Use i8

[AnnikaCodes]

Run clang-format

[AnnikaCodes]

To be honest here, I have no idea what this build error Harbormaster is giving me means.

FAIL: libarcher :: races/task-dependency.c (117 of 305)
******************** TEST 'libarcher :: races/task-dependency.c' FAILED ********************
Script:
--
: 'RUN: at line 13';   /var/lib/buildkite-agent/builds/llvm-project/build/./bin/clang -fopenmp -pthread -fno-experimental-isel -g -O1 -fsanitize=thread  -I /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests -I /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/runtime/src -L /var/lib/buildkite-agent/builds/llvm-project/build/lib -Wl,-rpath,/var/lib/buildkite-agent/builds/llvm-project/build/lib   /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/races/task-dependency.c -o /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp -latomic && env TSAN_OPTIONS='ignore_noninstrumented_modules=0:ignore_noninstrumented_modules=1' /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/deflake.bash /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp 2>&1 | tee /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp.log | /var/lib/buildkite-agent/builds/llvm-project/build/./bin/FileCheck /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/races/task-dependency.c
: 'RUN: at line 14';   /var/lib/buildkite-agent/builds/llvm-project/build/./bin/clang -fopenmp -pthread -fno-experimental-isel -g -O1 -fsanitize=thread  -I /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests -I /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/runtime/src -L /var/lib/buildkite-agent/builds/llvm-project/build/lib -Wl,-rpath,/var/lib/buildkite-agent/builds/llvm-project/build/lib   /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/races/task-dependency.c -o /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp -latomic && env ARCHER_OPTIONS="ignore_serial=1 report_data_leak=1" env TSAN_OPTIONS='ignore_noninstrumented_modules=0:ignore_noninstrumented_modules=1' /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/deflake.bash /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp 2>&1 | tee /var/lib/buildkite-agent/builds/llvm-project/build/projects/openmp/tools/archer/tests/races/Output/task-dependency.c.tmp.log | /var/lib/buildkite-agent/builds/llvm-project/build/./bin/FileCheck /var/lib/buildkite-agent/builds/llvm-project/openmp/tools/archer/tests/races/task-dependency.c
--
Exit Code: 1

[jrtc27]

That's probably https://github.com/llvm/llvm-project/commit/26b675d65eb2d1f117a39eee965652f590373232. It's in unrelated code so you can ignore it, and the buildbot probably isn't even enabling the experimental M68k backend?

[glaubitz]

In D111497#3082590, @jrtc27 wrote:

That's probably https://github.com/llvm/llvm-project/commit/26b675d65eb2d1f117a39eee965652f590373232. It's in unrelated code so you can ignore it, and the buildbot probably isn't even enabling the experimental M68k backend?

FWIW, the M68k backend is actually tested on a different buildbot: http://lab.llvm.org:8014/#/builders/180

[jrtc27]

In D111497#3082763, @glaubitz wrote:

In D111497#3082590, @jrtc27 wrote:

That's probably https://github.com/llvm/llvm-project/commit/26b675d65eb2d1f117a39eee965652f590373232. It's in unrelated code so you can ignore it, and the buildbot probably isn't even enabling the experimental M68k backend?

FWIW, the M68k backend is actually tested on a different buildbot: http://lab.llvm.org:8014/#/builders/180

Sure, but that's all for post-commit checks, not pre-commit like the failure here.

[glaubitz]

In D111497#3082769, @jrtc27 wrote:

In D111497#3082763, @glaubitz wrote:

In D111497#3082590, @jrtc27 wrote:

That's probably https://github.com/llvm/llvm-project/commit/26b675d65eb2d1f117a39eee965652f590373232. It's in unrelated code so you can ignore it, and the buildbot probably isn't even enabling the experimental M68k backend?

FWIW, the M68k backend is actually tested on a different buildbot: http://lab.llvm.org:8014/#/builders/180

Sure, but that's all for post-commit checks, not pre-commit like the failure here.

OK, I guess it's safe to commit then.

Could anyone with commit access go ahead and push the changes, please?

[ricky26]

I'm still getting test failures with this updated patch.

******************** TEST 'LLVM :: CodeGen/M68k/Arith/bitwise.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc < /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll -mtriple=m68k-linux -verify-machineinstrs | /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/FileCheck /home/ricky26/Projects/OSS/m68k/llvm/llvm/test/CodeGen/M68k/Arith/bitwise.ll
--
Exit Code: 1

Command Output (stderr):
--
llc: /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kInstrInfo.cpp:762: virtual void llvm::M68kInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineBasicBlock::iterator, llvm::Register, bool, int, const llvm::TargetRegisterClass*, const llvm::TargetRegisterInfo*) const: Assertion `MF.getFrameInfo().getObjectSize(FrameIndex) == 4 && "Stack slot too small for store"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/ricky26/Projects/OSS/m68k/llvm/build-relwithdebinfo/bin/llc -mtriple=m68k-linux -verify-machineinstrs
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'Greedy Register Allocator' on function '@lshr64'
-snip-
 #8 0x0000556e49e37621 llvm::MachineFrameInfo::getObjectSize(int) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kInstrInfo.cpp:762:3
 #9 0x0000556e49e37621 llvm::M68kInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/Target/M68k/M68kInstrInfo.cpp:762:3
#10 0x0000556e4a5c6de4 llvm::TargetInstrInfo::foldMemoryOperand(llvm::MachineInstr&, llvm::ArrayRef<unsigned int>, int, llvm::LiveIntervals*, llvm::VirtRegMap*) const /home/ricky26/Projects/OSS/m68k/llvm/llvm/lib/CodeGen/TargetInstrInfo.cpp:646:24

Debug logging:

selectOrSplit CCRC:%12 [80r,288r:0)  0@80r weight:3.322368e-03 w=3.322368e-03
hints: $ccr
RS_Split Cascade 0
Analyze counted 2 instrs in 2 blocks, through 2 blocks.
Compact region bundles, v=2, none.
Cost of isolating all blocks = 2.0
$ccr    static = 1.0, v=2 no bundles.
Inline spilling CCRC:%12 [80r,288r:0)  0@80r weight:3.322368e-03
From original %12
Merged spilled regs: SS#0 [80r,288r:0)  0@x weight:0.000000e+00
spillAroundUses %12

It looks like it's trying to spill the CCR, perhaps we can't handle smaller than 32-bit stack slots either? Ideally we shouldn't spill the CCR at all since it's not supported on the 68000, but that's a problem for later.

[glaubitz]

In D111497#3086076, @ricky26 wrote:

I'm still getting test failures with this updated patch.

Yeah, I'm getting the same failure, so it's reproducible.

[glaubitz]

Hi! Any news on this?

[ricky26]

I've been meaning to take a look since it shouldn't need much, but I've not gotten around to it yet.

[glaubitz]

Any news on this?

[0x59616e]

llvm/lib/Target/M68k/M68kISelLowering.cpp

3283–3284

That error seems result from here.

3339–3340

...and here.

[0x59616e]

the machine ir after dag-isel (-print-after=amdgpu-isel) has a weird COPY:

...
%12:ccrc = COPY $ccr
...

I believe this is the root cause.

But that COPY isn't there before dag-combine2 (-view-dag-combine2-dags).

I don't know where it comes from.

[craig.topper]

llvm/lib/Target/M68k/M68kISelLowering.cpp

3261

"register size - ShAmt" -> "register size - 1 - ShAmt" right?

3272

This sub can be an xor. See D119411

I don't m68k, does it have an xor with immediate instruction?

3289

This temporary array is unnecessary. You can write

return DAG.getMergeValues({Lo, Hi}, DL);

[craig.topper]

To fix the ccrc copy I believe you need to add this to M68kRegisterInfo.cpp

const TargetRegisterClass *
M68kRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
  if (RC == &M68k::CCRCRegClass)
    return &M68k::DR32RegClass;
  return RC;
}

I'm not sure if DR32 is the right class. But ultimately you need to tell it that a regular register should be used for copying flags, not the CCRC class. This will convince the scheduler that converts SelectionDAG to MachineIR that it should duplicate the ADD32di that provides that flag for the two CMOV32r instead of trying to copy the flags to the second CMOV32r. This need is needed because the flags are clobbered by other instructions between the first and second CMOV32r.

[0x59616e]

In D111497#3313565, @craig.topper wrote:

To fix the ccrc copy I believe you need to add this to M68kRegisterInfo.cpp

const TargetRegisterClass *
M68kRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
  if (RC == &M68k::CCRCRegClass)
    return &M68k::DR32RegClass;
  return RC;
}

I'm not sure if DR32 is the right class. But ultimately you need to tell it that a regular register should be used for copying flags, not the CCRC class. This will convince the scheduler that converts SelectionDAG to MachineIR that it should duplicate the ADD32di that provides that flag for the two CMOV32r instead of trying to copy the flags to the second CMOV32r. This need is needed because the flags are clobbered by other instructions between the first and second CMOV32r.

It works !

My solution seems to be wrong because of the reason Craig just mentioned: flags are clobbered between the two CMOV32r.

[0x59616e]

@AnnikaCodes if you agree, I can update the diff so that we can land this ASAP.

[glaubitz]

In D111497#3313643, @0x59616e wrote:

@AnnikaCodes if you agree, I can update the diff so that we can land this ASAP.

That would be great!, Thanks!

[0x59616e]

Address feedback.

[0x59616e]

I think it's ok to land this. Any suggestion ?

[AnnikaCodes]

I think this is fine (although to be honest, I don't really know what I'm doing).

llvm/lib/Target/M68k/M68kISelLowering.h

public:
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
 
   /// EVT is not used in-tree, but is used by out-of-tree target.
   virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
 
   /// Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
   /// Return the entry encoding for a jump table in the current function.
   /// The returned value is a member of the  MachineJumpTableInfo::JTEntryKind
   /// enum.
   unsigned getJumpTableEncoding() const override;
 
   const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
                                           const MachineBasicBlock *MBB,
                                           unsigned uid,
private:
   SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
                              int64_t Offset, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 
   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                           CallingConv::ID CallConv, bool IsVarArg,
                           const SmallVectorImpl<ISD::InputArg> &Ins,
                           const SDLoc &DL, SelectionDAG &DAG,
                           SmallVectorImpl<SDValue> &InVals) const;
 
   /// LowerFormalArguments - transform physical registers into virtual

llvm/lib/Target/M68k/M68kISelLowering.cpp

M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
 
   // FIXME It would be better to use a custom lowering
   for (auto OP : {ISD::SMULO, ISD::UMULO}) {
     setOperationAction(OP, MVT::i8, Expand);
     setOperationAction(OP, MVT::i16, Expand);
     setOperationAction(OP, MVT::i32, Expand);
   }
 
+  for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS})
+    setOperationAction(OP, MVT::i32, Custom);
+
   // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
   for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
     setOperationAction(ISD::ADDC, VT, Custom);
     setOperationAction(ISD::ADDE, VT, Custom);
     setOperationAction(ISD::SUBC, VT, Custom);
     setOperationAction(ISD::SUBE, VT, Custom);
   }
 

 }
 
 SDValue
 M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
                                      const SmallVectorImpl<ISD::InputArg> &Ins,
                                      const SDLoc &DL, SelectionDAG &DAG,
                                      const CCValAssign &VA,
                                      MachineFrameInfo &MFI,
                                      unsigned ArgIdx) const {
   // Create the nodes corresponding to a load from this parameter slot.
   ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
   EVT ValVT;
 
   // If value is passed by pointer we have address passed instead of the value
   // itself.
   if (VA.getLocInfo() == CCValAssign::Indirect)
     ValVT = VA.getLocVT();
bool M68kTargetLowering::IsEligibleForTailCallOptimization(
 
   return true;
 }
 
 //===----------------------------------------------------------------------===//
 // Custom Lower
 //===----------------------------------------------------------------------===//
 
 SDValue M68kTargetLowering::LowerOperation(SDValue Op,
                                            SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default:
     llvm_unreachable("Should not custom lower this!");
   case ISD::SADDO:
   case ISD::UADDO:
   case ISD::SSUBO:
   case ISD::USUBO:
   case ISD::SMULO:
   case ISD::UMULO:
     return LowerXALUO(Op, DAG);
   case ISD::SETCC:
     return LowerSETCC(Op, DAG);
   case ISD::SETCCCARRY:
     return LowerSETCCCARRY(Op, DAG);
   case ISD::SELECT:
SDValue M68kTargetLowering::LowerOperation(SDValue Op,
   case ISD::BlockAddress:
     return LowerBlockAddress(Op, DAG);
   case ISD::JumpTable:
     return LowerJumpTable(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
+  case ISD::SHL_PARTS:
+    return LowerShiftLeftParts(Op, DAG);
+  case ISD::SRA_PARTS:
+    return LowerShiftRightParts(Op, DAG, true);
+  case ISD::SRL_PARTS:
+    return LowerShiftRightParts(Op, DAG, false);
   }
 }
 
 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
                                                 SDValue C) const {
   // Shifts and add instructions in M68000 and M68010 support
   // up to 32 bits, but mul only has 16-bit variant. So it's almost
   // certainly beneficial to lower 8/16/32-bit mul to their
SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
 
   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
                              DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
 
   SDValue Ops[2] = {Result, Chain};
   return DAG.getMergeValues(Ops, DL);
 }
 
+SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Lo = Op.getOperand(0);
+  SDValue Hi = Op.getOperand(1);
+  SDValue Shamt = Op.getOperand(2);
+  EVT VT = Lo.getValueType();
+
+  // if Shamt - register size < 0: // Shamt < register size
+  //   Lo = Lo << Shamt
+  //   Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
+  // else:
+  //   Lo = 0
+  //   Hi = Lo << (Shamt - register size)
+
+  SDValue Zero = DAG.getConstant(0, DL, VT);
+  SDValue One = DAG.getConstant(1, DL, VT);
+  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
+  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
+  SDValue ShamtMinusRegisterSize =
+      DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
+  SDValue RegisterSizeMinus1Shamt =
+      DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
+
+  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
+  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
+  SDValue ShiftRightLo =
+      DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
+  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
+  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
+  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
+
+  SDValue CC =
+      DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
+
+  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
+  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
+
+  return DAG.getMergeValues({Lo, Hi}, DL);
+}
+
+SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
+                                                 bool IsSRA) const {
+  SDLoc DL(Op);
+  SDValue Lo = Op.getOperand(0);
+  SDValue Hi = Op.getOperand(1);
+  SDValue Shamt = Op.getOperand(2);
+  EVT VT = Lo.getValueType();
+
+  // SRA expansion:
+  //   if Shamt - register size < 0: // Shamt < register size
+  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
+  //     Hi = Hi >>s Shamt
+  //   else:
+  //     Lo = Hi >>s (Shamt - register size);
+  //     Hi = Hi >>s (register size - 1)
+  //
+  // SRL expansion:
+  //   if Shamt - register size < 0: // Shamt < register size
+  //     Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
+  //     Hi = Hi >>u Shamt
+  //   else:
+  //     Lo = Hi >>u (Shamt - register size);
+  //     Hi = 0;
+
+  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
+
+  SDValue Zero = DAG.getConstant(0, DL, VT);
+  SDValue One = DAG.getConstant(1, DL, VT);
+  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
+  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
+  SDValue ShamtMinusRegisterSize =
+      DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
+  SDValue RegisterSizeMinus1Shamt =
+      DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
+
+  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
+  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
+  SDValue ShiftLeftHi =
+      DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
+  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
+  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
+  SDValue LoFalse =
+      DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
+  SDValue HiFalse =
+      IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
+
+  SDValue CC =
+      DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
+
+  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
+  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
+
+  return DAG.getMergeValues({Lo, Hi}, DL);
+}
+
 //===----------------------------------------------------------------------===//
 // DAG Combine
 //===----------------------------------------------------------------------===//
 
 static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl,
                         SelectionDAG &DAG) {
   return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
                      DAG.getConstant(Cond, dl, MVT::i8), CCR);
 }
 // When legalizing carry, we create carries via add X, -1
 // If that comes from an actual carry, via setcc, we use the
 // carry directly.
 static SDValue combineCarryThroughADD(SDValue CCR) {
   if (CCR.getOpcode() == M68kISD::ADD) {
     if (isAllOnesConstant(CCR.getOperand(1))) {
       SDValue Carry = CCR.getOperand(0);
       while (Carry.getOpcode() == ISD::TRUNCATE ||
              Carry.getOpcode() == ISD::ZERO_EXTEND ||
              Carry.getOpcode() == ISD::SIGN_EXTEND ||
              Carry.getOpcode() == ISD::ANY_EXTEND ||
              (Carry.getOpcode() == ISD::AND &&
               isOneConstant(Carry.getOperand(1))))
         Carry = Carry.getOperand(0);
       if (Carry.getOpcode() == M68kISD::SETCC ||
           Carry.getOpcode() == M68kISD::SETCC_CARRY) {
         if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
           return Carry.getOperand(1);
       }
     }
   }

llvm/lib/Target/M68k/M68kRegisterInfo.h

void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            RegScavenger *RS = nullptr) const override;
 
   bool hasBasePointer(const MachineFunction &MF) const;
 
   /// True if the stack can be realigned for the target.
   bool canRealignStack(const MachineFunction &MF) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
+
+  const TargetRegisterClass *
+  getCrossCopyRegClass(const TargetRegisterClass *RC) const override {
+    if (RC == &M68k::CCRCRegClass)
+      return &M68k::DR32RegClass;
+    return RC;
+  }
+
   unsigned getStackRegister() const { return StackPtr; }
   unsigned getBaseRegister() const { return BasePtr; }
   unsigned getGlobalBaseRegister() const { return GlobalBasePtr; }
 
   const TargetRegisterClass *intRegClass(unsigned Size) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_M68K_M68KREGISTERINFO_H

llvm/test/CodeGen/M68k/Arith/bitwise.ll

 ; CHECK-LABEL: eoril:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    move.l (4,%sp), %d0
 ; CHECK-NEXT:    eori.l #305419896, %d0
 ; CHECK-NEXT:    rts
   %1 = xor i32 %a, 305419896
   ret i32 %1
 }
+
+define i64 @lshr64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: lshr64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill
+; CHECK-NEXT:    move.l (28,%sp), %d3
+; CHECK-NEXT:    move.l (16,%sp), %d2
+; CHECK-NEXT:    move.l %d3, %d1
+; CHECK-NEXT:    add.l #-32, %d1
+; CHECK-NEXT:    bmi .LBB18_1
+; CHECK-NEXT:  ; %bb.2:
+; CHECK-NEXT:    move.l #0, %d0
+; CHECK-NEXT:    bra .LBB18_3
+; CHECK-NEXT:  .LBB18_1:
+; CHECK-NEXT:    move.l %d2, %d0
+; CHECK-NEXT:    lsr.l %d3, %d0
+; CHECK-NEXT:  .LBB18_3:
+; CHECK-NEXT:    move.l %d3, %d4
+; CHECK-NEXT:    add.l #-32, %d4
+; CHECK-NEXT:    bmi .LBB18_4
+; CHECK-NEXT:  ; %bb.5:
+; CHECK-NEXT:    lsr.l %d1, %d2
+; CHECK-NEXT:    move.l %d2, %d1
+; CHECK-NEXT:    bra .LBB18_6
+; CHECK-NEXT:  .LBB18_4:
+; CHECK-NEXT:    move.l %d3, %d4
+; CHECK-NEXT:    eori.l #31, %d4
+; CHECK-NEXT:    lsl.l #1, %d2
+; CHECK-NEXT:    move.l (20,%sp), %d1
+; CHECK-NEXT:    lsl.l %d4, %d2
+; CHECK-NEXT:    lsr.l %d3, %d1
+; CHECK-NEXT:    or.l %d2, %d1
+; CHECK-NEXT:  .LBB18_6:
+; CHECK-NEXT:    movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+  %1 = lshr i64 %a, %b
+  ret i64 %1
+}
+
+define i64 @ashr64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: ashr64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #8, %sp
+; CHECK-NEXT:    movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
+; CHECK-NEXT:    move.l (24,%sp), %d2
+; CHECK-NEXT:    move.l (12,%sp), %d0
+; CHECK-NEXT:    move.l %d2, %d3
+; CHECK-NEXT:    add.l #-32, %d3
+; CHECK-NEXT:    move.l %d2, %d1
+; CHECK-NEXT:    add.l #-32, %d1
+; CHECK-NEXT:    bmi .LBB19_1
+; CHECK-NEXT:  ; %bb.2:
+; CHECK-NEXT:    move.l %d0, %d1
+; CHECK-NEXT:    asr.l %d3, %d1
+; CHECK-NEXT:    bra .LBB19_3
+; CHECK-NEXT:  .LBB19_1:
+; CHECK-NEXT:    move.l %d2, %d1
+; CHECK-NEXT:    eori.l #31, %d1
+; CHECK-NEXT:    move.l %d0, %d3
+; CHECK-NEXT:    lsl.l #1, %d3
+; CHECK-NEXT:    lsl.l %d1, %d3
+; CHECK-NEXT:    move.l (16,%sp), %d1
+; CHECK-NEXT:    lsr.l %d2, %d1
+; CHECK-NEXT:    or.l %d3, %d1
+; CHECK-NEXT:  .LBB19_3:
+; CHECK-NEXT:    move.l %d2, %d3
+; CHECK-NEXT:    add.l #-32, %d3
+; CHECK-NEXT:    bmi .LBB19_5
+; CHECK-NEXT:  ; %bb.4:
+; CHECK-NEXT:    move.l #31, %d2
+; CHECK-NEXT:  .LBB19_5:
+; CHECK-NEXT:    asr.l %d2, %d0
+; CHECK-NEXT:    movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
+; CHECK-NEXT:    adda.l #8, %sp
+; CHECK-NEXT:    rts
+  %1 = ashr i64 %a, %b
+  ret i64 %1
+}
+
+define i64 @shl64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: shl64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill
+; CHECK-NEXT:    move.l (28,%sp), %d3
+; CHECK-NEXT:    move.l (20,%sp), %d2
+; CHECK-NEXT:    move.l %d3, %d0
+; CHECK-NEXT:    add.l #-32, %d0
+; CHECK-NEXT:    bmi .LBB20_1
+; CHECK-NEXT:  ; %bb.2:
+; CHECK-NEXT:    move.l #0, %d1
+; CHECK-NEXT:    bra .LBB20_3
+; CHECK-NEXT:  .LBB20_1:
+; CHECK-NEXT:    move.l %d2, %d1
+; CHECK-NEXT:    lsl.l %d3, %d1
+; CHECK-NEXT:  .LBB20_3:
+; CHECK-NEXT:    move.l %d3, %d4
+; CHECK-NEXT:    add.l #-32, %d4
+; CHECK-NEXT:    bmi .LBB20_4
+; CHECK-NEXT:  ; %bb.5:
+; CHECK-NEXT:    lsl.l %d0, %d2
+; CHECK-NEXT:    move.l %d2, %d0
+; CHECK-NEXT:    bra .LBB20_6
+; CHECK-NEXT:  .LBB20_4:
+; CHECK-NEXT:    move.l %d3, %d4
+; CHECK-NEXT:    eori.l #31, %d4
+; CHECK-NEXT:    lsr.l #1, %d2
+; CHECK-NEXT:    move.l (16,%sp), %d0
+; CHECK-NEXT:    lsr.l %d4, %d2
+; CHECK-NEXT:    lsl.l %d3, %d0
+; CHECK-NEXT:    or.l %d2, %d0
+; CHECK-NEXT:  .LBB20_6:
+; CHECK-NEXT:    movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+  %1 = shl i64 %a, %b
+  ret i64 %1
+}