[RISCV] Add a fatal error if ISD::VSCALE is used with Zvl32b.

[craig.topper]

Summary

We convert VLEN to vscale by dividing by RVVBitsPerBlock which is
currently 64. This is only correct if VLEN is evenly divisible by

64. With only Zvl32b we can't assume that.

This patch adds a fatal_error to prevent generating code that may
be broken.

We probably need to look at how we size stack frame objects too.

[frasercrmck]

LGTM, though this issue is really in any scalable-vector code with Zvl32b, so we're still letting a lot slip through the cracks, aren't we?

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
     // vscale as VLENB / 8.
     static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
+    if (Subtarget.getMinVLen() < RISCV::RVVBitsPerBlock)
+      report_fatal_error("Support for VLEN==32 is incomplete.");
     if (isa<ConstantSDNode>(Op.getOperand(0))) {
       // We assume VLENB is a multiple of 8. We manually choose the best shift
       // here because SimplifyDemandedBits isn't always able to simplify it.
       uint64_t Val = Op.getConstantOperandVal(0);
       if (isPowerOf2_64(Val)) {
         uint64_t Log2 = Log2_64(Val);
         if (Log2 < 3)
           return DAG.getNode(ISD::SRL, DL, VT, VLENB,