[RISCV] Add bfp and bfpw intrinsic in zbf extension

[Jimerlife]

Summary

RV32, RV64
bfp
RV64 only
bfpw

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

36

Capital Z

37

I think we should have __builtin_riscv_bfp_32 and __builtin_riscv_bfp_64. It's more convenient and portable for software to be written in terms of number of bits being operated on rather than changing behavior based on xlen.

llvm/include/llvm/IR/IntrinsicsRISCV.td

98

We only need one intrinsic. BitManipGPRGPRIntrinsics is type overloaded. We can check the type in isel patterns.

[Jimerlife]

According to machine target, write two intrinsic builtin_riscv_bfp_rv32 and builtin_riscv_bfp_rv64.
Support __builtin_riscv_bfp_rv32 used in RV64 target.

[Jimerlife]

clang/include/clang/Basic/BuiltinsRISCV.def

36

done

37

I have rewrite two intrinsics according to target machine

llvm/include/llvm/IR/IntrinsicsRISCV.td

98

Only save one intrinsic pattern.

[Jimerlife]

format code

[craig.topper]

LGTM

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
 TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
                "experimental-zbe,64bit")
 TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc",
                "experimental-zbe")
 TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc",
                "experimental-zbe,64bit")
 
+// Zbf extension
+TARGET_BUILTIN(__builtin_riscv_bfp_32, "ZiZiZi", "nc", "experimental-zbf")
+TARGET_BUILTIN(__builtin_riscv_bfp_64, "WiWiWi", "nc", "experimental-zbf,64bit")
+
 // Zbp extension
 TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
   case RISCV::BI__builtin_riscv_bcompress_32:
   case RISCV::BI__builtin_riscv_bcompress_64:
   case RISCV::BI__builtin_riscv_bdecompress_32:
   case RISCV::BI__builtin_riscv_bdecompress_64:
+  case RISCV::BI__builtin_riscv_bfp_32:
+  case RISCV::BI__builtin_riscv_bfp_64:
   case RISCV::BI__builtin_riscv_grev_32:
   case RISCV::BI__builtin_riscv_grev_64:
   case RISCV::BI__builtin_riscv_gorc_32:
   case RISCV::BI__builtin_riscv_gorc_64:
   case RISCV::BI__builtin_riscv_shfl_32:
   case RISCV::BI__builtin_riscv_shfl_64:
   case RISCV::BI__builtin_riscv_unshfl_32:
   case RISCV::BI__builtin_riscv_unshfl_64:
case RISCV::BI__builtin_riscv_crc32c_d: {
     case RISCV::BI__builtin_riscv_bcompress_64:
       ID = Intrinsic::riscv_bcompress;
       break;
     case RISCV::BI__builtin_riscv_bdecompress_32:
     case RISCV::BI__builtin_riscv_bdecompress_64:
       ID = Intrinsic::riscv_bdecompress;
       break;
 
+    // Zbf
+    case RISCV::BI__builtin_riscv_bfp_32:
+    case RISCV::BI__builtin_riscv_bfp_64:
+      ID = Intrinsic::riscv_bfp;
+      break;
+
     // Zbp
     case RISCV::BI__builtin_riscv_grev_32:
     case RISCV::BI__builtin_riscv_grev_64:
       ID = Intrinsic::riscv_grev;
       break;
     case RISCV::BI__builtin_riscv_gorc_32:
     case RISCV::BI__builtin_riscv_gorc_64:
       ID = Intrinsic::riscv_gorc;

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbf.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbf -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBF
+
+// RV32ZBF-LABEL: @bfp32(
+// RV32ZBF-NEXT:  entry:
+// RV32ZBF-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBF-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBF-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBF-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBF-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBF-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBF-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bfp.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBF-NEXT:    ret i32 [[TMP2]]
+//
+int bfp32(int a, int b) {
+  return __builtin_riscv_bfp_32(a, b);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbf.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbf -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBF
+
+// RV64ZBF-LABEL: @bfp32(
+// RV64ZBF-NEXT:  entry:
+// RV64ZBF-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBF-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBF-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBF-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV64ZBF-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBF-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV64ZBF-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bfp.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBF-NEXT:    ret i32 [[TMP2]]
+//
+int bfp32(int a, int b) {
+  return __builtin_riscv_bfp_32(a, b);
+}
+
+// RV64ZBF-LABEL: @bfp64(
+// RV64ZBF-NEXT:  entry:
+// RV64ZBF-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBF-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBF-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBF-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.bfp.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBF-NEXT:    ret i64 [[TMP2]]
+//
+long bfp64(long a, long b) {
+  return __builtin_riscv_bfp_64(a, b);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
   // Zbe
   def int_riscv_bcompress   : BitManipGPRGPRIntrinsics;
   def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
 
+  // Zbf
+  def int_riscv_bfp  : BitManipGPRGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
   def int_riscv_shfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_unshfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_n  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_b  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_h  : BitManipGPRGPRIntrinsics;

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Bit Compress/Decompress implement the generic bit extract and bit deposit
   // functions. This operation is also referred to as bit gather/scatter, bit
   // pack/unpack, parallel extract/deposit, compress/expand, or right
   // compress/right expand.
   BCOMPRESS,
   BCOMPRESSW,
   BDECOMPRESS,
   BDECOMPRESSW,
+  // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2
+  // into the value in rs1. The upper bits of rs2 control the length of the bit
+  // field and target position. The layout of rs2 is chosen in a way that makes
+  // it possible to construct rs2 easily using pack[h] instructions and/or
+  // andi/lui.
+  BFP,
+  BFPW,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
   VMV_V_X_VL,
   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
   // for the VL value to be used for the operation.
   VFMV_V_F_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case Intrinsic::riscv_unshfl: {
     return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
   }
   case Intrinsic::riscv_bcompress:
   case Intrinsic::riscv_bdecompress: {
     unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS
                                                        : RISCVISD::BDECOMPRESS;
     return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
   }
+  case Intrinsic::riscv_bfp:
+    return DAG.getNode(RISCVISD::BFP, DL, XLenVT, Op.getOperand(1),
+                       Op.getOperand(2));
   case Intrinsic::riscv_vmv_x_s:
     assert(Op.getValueType() == XLenVT && "Unexpected VT!");
     return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
                        Op.getOperand(1));
   case Intrinsic::riscv_vmv_v_x:
     return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),
                             Op.getSimpleValueType(), DL, DAG, Subtarget);
   case Intrinsic::riscv_vfmv_v_f:
case Intrinsic::riscv_bdecompress: {
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
       unsigned Opc = IntNo == Intrinsic::riscv_bcompress
                          ? RISCVISD::BCOMPRESSW
                          : RISCVISD::BDECOMPRESSW;
       SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       break;
     }
+    case Intrinsic::riscv_bfp: {
+      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+             "Unexpected custom legalisation");
+      SDValue NewOp1 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue NewOp2 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
+      SDValue Res = DAG.getNode(RISCVISD::BFPW, DL, MVT::i64, NewOp1, NewOp2);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      break;
+    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
       if (VT.bitsLT(XLenVT)) {
         // Simple case just extract using vmv.x.s and truncate.
         SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                       Subtarget.getXLenVT(), N->getOperand(1));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(GREV)
   NODE_NAME_CASE(GREVW)
   NODE_NAME_CASE(GORC)
   NODE_NAME_CASE(GORCW)
   NODE_NAME_CASE(SHFL)
   NODE_NAME_CASE(SHFLW)
   NODE_NAME_CASE(UNSHFL)
   NODE_NAME_CASE(UNSHFLW)
+  NODE_NAME_CASE(BFP)
+  NODE_NAME_CASE(BFPW)
   NODE_NAME_CASE(BCOMPRESS)
   NODE_NAME_CASE(BCOMPRESSW)
   NODE_NAME_CASE(BDECOMPRESS)
   NODE_NAME_CASE(BDECOMPRESSW)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def riscv_grev   : SDNode<"RISCVISD::GREV",   SDTIntBinOp>;
 def riscv_grevw  : SDNode<"RISCVISD::GREVW",  SDT_RISCVIntBinOpW>;
 def riscv_gorc   : SDNode<"RISCVISD::GORC",   SDTIntBinOp>;
 def riscv_gorcw  : SDNode<"RISCVISD::GORCW",  SDT_RISCVIntBinOpW>;
 def riscv_shfl   : SDNode<"RISCVISD::SHFL",   SDTIntBinOp>;
 def riscv_shflw  : SDNode<"RISCVISD::SHFLW",  SDT_RISCVIntBinOpW>;
 def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bfp    : SDNode<"RISCVISD::BFP",    SDTIntBinOp>;
+def riscv_bfpw   : SDNode<"RISCVISD::BFPW",   SDT_RISCVIntBinOpW>;
 def riscv_bcompress    : SDNode<"RISCVISD::BCOMPRESS",   SDTIntBinOp>;
 def riscv_bcompressw   : SDNode<"RISCVISD::BCOMPRESSW",  SDT_RISCVIntBinOpW>;
 def riscv_bdecompress  : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
 def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>;
 
 def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenHalf";
   let RenderMethod = "addImmOperands";

 def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
 def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def : PatGpr<int_riscv_crc32_d, CRC32D>;
 def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
 } // Predicates = [HasStdExtZbr, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def : PatGprGpr<riscv_bfp, BFP>;
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def : PatGprGpr<riscv_bfpw, BFPW>;

llvm/test/CodeGen/RISCV/rv32zbf-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV32ZBF-LABEL: bfp32:
+; RV32ZBF:       # %bb.0:
+; RV32ZBF-NEXT:    bfp a0, a0, a1
+; RV32ZBF-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBF
+
+declare i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+
+define i32 @bfp32(i32 %a, i32 %b) nounwind {
+; RV64ZBF-LABEL: bfp32:
+; RV64ZBF:       # %bb.0:
+; RV64ZBF-NEXT:    bfpw a0, a0, a1
+; RV64ZBF-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+
+define i64 @bfp64(i64 %a, i64 %b) nounwind {
+; RV64ZBF-LABEL: bfp64:
+; RV64ZBF:       # %bb.0:
+; RV64ZBF-NEXT:    bfp a0, a0, a1
+; RV64ZBF-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}