[RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.

[jacquesguan]

Summary

Enable transform (X & Y) == Y ---> (~X & Y) == 0 and (X & Y) != Y ---> (~X & Y) != 0 when have Zbb extension to use more andn instruction.

[craig.topper]

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

562

Can you pre-commit the new test cases so we can see the change here?

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1180

This is the default implementation

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

561

Don't put double blank lines in

[jacquesguan]

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

562

Done, I added a precommit test in https://reviews.llvm.org/D116013.

[jacquesguan]

remove hasAndNot and format test.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1180

Done

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

561

Done

[luismarques]

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

562

This diff doesn't yet reflect the separate test patch. You don't need to wait for the other patch to be accepted to update the diff here. You can use the other patch as the diff baseline and add it as a parent revision to this one.

[jacquesguan]

rebase to pre-commit test.

[jacquesguan]

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

562

Done, I rebase to the pre-commit test, now the diff is OK.

[jacquesguan]

Update test.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;
   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
   bool isCheapToSpeculateCttz() const override;
   bool isCheapToSpeculateCtlz() const override;
-  bool hasAndNot(SDValue Y) const override;
+  bool hasAndNotCompare(SDValue Y) const override;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 
   bool softPromoteHalfType() const override { return true; }
 
   /// Return the register type for a given MVT, ensuring vectors are treated

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 bool RISCVTargetLowering::isCheapToSpeculateCttz() const {
   return Subtarget.hasStdExtZbb();
 }
 
 bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {
   return Subtarget.hasStdExtZbb();
 }
 
-bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
+bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   EVT VT = Y.getValueType();
 
   // FIXME: Support vectors once we have tests.
   if (VT.isVector())
     return false;
 
   return Subtarget.hasStdExtZbb() && !isa<ConstantSDNode>(Y);
 }
 
 /// Check if sinking \p I's operands to I's basic block is profitable, because
 /// the operands can be folded into a target instruction, e.g.
 /// splats of scalars can fold into vector instructions.
 bool RISCVTargetLowering::shouldSinkOperands(
     Instruction *I, SmallVectorImpl<Use *> &Ops) const {
   using namespace llvm::PatternMatch;
 
   if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())
     return false;
 

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    slli a0, a0, 16
 ; RV32ZBP-NEXT:    srai a0, a0, 25
 ; RV32ZBP-NEXT:    ret
   %1 = ashr i16 %a, 9
   ret i16 %1
 }
 
 define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: andn_seqz_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: andn_seqz_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    seqz a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: andn_seqz_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    and a0, a0, a1
 ; RV32ZBP-NEXT:    xor a0, a0, a1
 ; RV32ZBP-NEXT:    seqz a0, a0

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: andn_snez_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    snez a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: andn_snez_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    and a0, a0, a1
 ; RV32ZBP-NEXT:    xor a0, a0, a1
 ; RV32ZBP-NEXT:    snez a0, a0

llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: andn_seqz_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: andn_seqz_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    and a0, a0, a1
 ; RV64ZBP-NEXT:    xor a0, a0, a1
 ; RV64ZBP-NEXT:    seqz a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i32 %a, %b
   %cmpeq = icmp eq i32 %and, %b
   ret i1 %cmpeq
 }
 
 define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: andn_seqz_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: andn_seqz_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: andn_seqz_i64:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    and a0, a0, a1
 ; RV64ZBP-NEXT:    xor a0, a0, a1
 ; RV64ZBP-NEXT:    seqz a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i64 %a, %b
   %cmpeq = icmp eq i64 %and, %b
   ret i1 %cmpeq
 }
 
 define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: andn_snez_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: andn_snez_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: andn_snez_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    and a0, a0, a1
 ; RV64ZBP-NEXT:    xor a0, a0, a1
 ; RV64ZBP-NEXT:    snez a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i32 %a, %b
   %cmpeq = icmp ne i32 %and, %b
   ret i1 %cmpeq
 }
 
 define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: andn_snez_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: andn_snez_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: andn_snez_i64:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    and a0, a0, a1
 ; RV64ZBP-NEXT:    xor a0, a0, a1
 ; RV64ZBP-NEXT:    snez a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i64 %a, %b
   %cmpeq = icmp ne i64 %and, %b
   ret i1 %cmpeq
 }