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Differential D116013

[RISCV] Precommit tests for override hasAndNotCompare.
ClosedPublic

Authored by jacquesguan on Dec 19 2021, 7:46 PM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
HsiangKai
khchen
Commits
rGcb3eb7a70b56: [RISCV] Precommit tests for override hasAndNotCompare.
Summary

Precommit tests for D115922.

Diff Detail

Event Timeline

jacquesguan created this revision.Dec 19 2021, 7:46 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 23 others. · View Herald TranscriptDec 19 2021, 7:46 PM
jacquesguan requested review of this revision.Dec 19 2021, 7:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 19 2021, 7:46 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
jacquesguan mentioned this in D115922: [RISCV] Override hasAndNotCompare to use more andn when have Zbb extension..Dec 19 2021, 7:47 PM
Harbormaster completed remote builds in B140030: Diff 395364.Dec 19 2021, 8:35 PM
jacquesguan added a child revision: D115922: [RISCV] Override hasAndNotCompare to use more andn when have Zbb extension..Dec 20 2021, 3:30 AM
jacquesguan updated this revision to Diff 395406.Dec 20 2021, 3:53 AM

rebase to pre-commit tests.

luismarques added a comment.Dec 20 2021, 4:03 AM

Nit: this seems to have an inconsistent naming logic:

  • andn_seqz_i32
  • andn_ne_i32

Other than that, LGTM.

jacquesguan updated this revision to Diff 395409.Dec 20 2021, 4:25 AM

rename.

jacquesguan added a comment.Dec 20 2021, 4:55 AM
In D116013#3202480, @luismarques wrote:

Nit: this seems to have an inconsistent naming logic:

  • andn_seqz_i32
  • andn_ne_i32

Other than that, LGTM.

Done, thanks.

Harbormaster completed remote builds in B140061: Diff 395409.Dec 20 2021, 5:05 AM
luismarques accepted this revision.Dec 20 2021, 5:19 AM
This revision is now accepted and ready to land.Dec 20 2021, 5:19 AM
luismarques added a comment.Dec 20 2021, 5:29 AM

BTW, maybe add signext to the function i32 params if that removes sext.ws that are irrelevant for the tests.

jacquesguan updated this revision to Diff 395560.Dec 20 2021, 5:48 PM

Add signext to i32 params in RV64 case.

Harbormaster completed remote builds in B140166: Diff 395560.Dec 20 2021, 6:30 PM
This revision was landed with ongoing or failed builds.Dec 20 2021, 10:55 PM
Closed by commit rGcb3eb7a70b56: [RISCV] Precommit tests for override hasAndNotCompare. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rGcb3eb7a70b56: [RISCV] Precommit tests for override hasAndNotCompare..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
114 lines
104 lines

Diff 395602

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

Show First 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
; RV32ZBP-LABEL: srai_i16: ; RV32ZBP-LABEL: srai_i16:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: slli a0, a0, 16 ; RV32ZBP-NEXT: slli a0, a0, 16
; RV32ZBP-NEXT: srai a0, a0, 25 ; RV32ZBP-NEXT: srai a0, a0, 25
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = ashr i16 %a, 9 %1 = ashr i16 %a, 9
ret i16 %1 ret i16 %1
} }
define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: andn_seqz_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: andn_seqz_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: xor a0, a0, a1
; RV32ZBB-NEXT: seqz a0, a0
; RV32ZBB-NEXT: ret
;
; RV32ZBP-LABEL: andn_seqz_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: and a0, a0, a1
; RV32ZBP-NEXT: xor a0, a0, a1
; RV32ZBP-NEXT: seqz a0, a0
; RV32ZBP-NEXT: ret
%and = and i32 %a, %b
%cmpeq = icmp eq i32 %and, %b
ret i1 %cmpeq
}
define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: andn_seqz_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: andn_seqz_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a1, a3, a1
; RV32ZBB-NEXT: andn a0, a2, a0
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: seqz a0, a0
; RV32ZBB-NEXT: ret
;
; RV32ZBP-LABEL: andn_seqz_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: andn a1, a3, a1
; RV32ZBP-NEXT: andn a0, a2, a0
; RV32ZBP-NEXT: or a0, a0, a1
; RV32ZBP-NEXT: seqz a0, a0
; RV32ZBP-NEXT: ret
%and = and i64 %a, %b
%cmpeq = icmp eq i64 %and, %b
ret i1 %cmpeq
}
define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: andn_snez_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: andn_snez_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: xor a0, a0, a1
; RV32ZBB-NEXT: snez a0, a0
; RV32ZBB-NEXT: ret
;
; RV32ZBP-LABEL: andn_snez_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: and a0, a0, a1
; RV32ZBP-NEXT: xor a0, a0, a1
; RV32ZBP-NEXT: snez a0, a0
; RV32ZBP-NEXT: ret
%and = and i32 %a, %b
%cmpeq = icmp ne i32 %and, %b
ret i1 %cmpeq
}
define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: andn_snez_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: andn_snez_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a1, a3, a1
; RV32ZBB-NEXT: andn a0, a2, a0
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: snez a0, a0
; RV32ZBB-NEXT: ret
;
; RV32ZBP-LABEL: andn_snez_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: andn a1, a3, a1
; RV32ZBP-NEXT: andn a0, a2, a0
; RV32ZBP-NEXT: or a0, a0, a1
; RV32ZBP-NEXT: snez a0, a0
; RV32ZBP-NEXT: ret
%and = and i64 %a, %b
%cmpeq = icmp ne i64 %and, %b
ret i1 %cmpeq
}

llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Show First 20 Lines • Show All 622 Lines • ▼ Show 20 Lines
; RV64ZBP-LABEL: srai_i16: ; RV64ZBP-LABEL: srai_i16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: slli a0, a0, 48 ; RV64ZBP-NEXT: slli a0, a0, 48
; RV64ZBP-NEXT: srai a0, a0, 57 ; RV64ZBP-NEXT: srai a0, a0, 57
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = ashr i16 %a, 9 %1 = ashr i16 %a, 9
ret i16 %1 ret i16 %1
} }
define i1 @andn_seqz_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: andn_seqz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: andn_seqz_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: seqz a0, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: andn_seqz_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: and a0, a0, a1
; RV64ZBP-NEXT: xor a0, a0, a1
; RV64ZBP-NEXT: seqz a0, a0
; RV64ZBP-NEXT: ret
%and = and i32 %a, %b
%cmpeq = icmp eq i32 %and, %b
ret i1 %cmpeq
}
define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: andn_seqz_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: andn_seqz_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: seqz a0, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: andn_seqz_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: and a0, a0, a1
; RV64ZBP-NEXT: xor a0, a0, a1
; RV64ZBP-NEXT: seqz a0, a0
; RV64ZBP-NEXT: ret
%and = and i64 %a, %b
%cmpeq = icmp eq i64 %and, %b
ret i1 %cmpeq
}
define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: andn_snez_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: andn_snez_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: snez a0, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: andn_snez_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: and a0, a0, a1
; RV64ZBP-NEXT: xor a0, a0, a1
; RV64ZBP-NEXT: snez a0, a0
; RV64ZBP-NEXT: ret
%and = and i32 %a, %b
%cmpeq = icmp ne i32 %and, %b
ret i1 %cmpeq
}
define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: andn_snez_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: andn_snez_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: snez a0, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: andn_snez_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: and a0, a0, a1
; RV64ZBP-NEXT: xor a0, a0, a1
; RV64ZBP-NEXT: snez a0, a0
; RV64ZBP-NEXT: ret
%and = and i64 %a, %b
%cmpeq = icmp ne i64 %and, %b
ret i1 %cmpeq
}