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Luhaocong (Haocong Lu)
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User Since
Oct 21 2021, 5:33 AM (42 w, 2 d)

Recent Activity

May 23 2022

Luhaocong requested review of D126185: [RISCV]Remove solved TODO for combining constant shifts.
May 23 2022, 12:19 AM · Restricted Project, Restricted Project

Mar 15 2022

Luhaocong updated the diff for D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask.

rebase

Mar 15 2022, 6:46 PM · Restricted Project, Restricted Project
Luhaocong added a comment to D121650: [DAGCombiner][RISCV] Adjust (aext (and (trunc x), cst)) -> (and x, cst) to sext cst based on target preference.

LGTM

Mar 15 2022, 1:32 AM · Restricted Project, Restricted Project
Luhaocong added inline comments to D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask.
Mar 15 2022, 1:22 AM · Restricted Project, Restricted Project
Luhaocong updated the diff for D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask.
  1. Only do this selection for and i64 %x, imm when the imm exceeds simm32 (cannot be generated by LUI)
  2. Add some test cases
Mar 15 2022, 12:56 AM · Restricted Project, Restricted Project

Mar 14 2022

Luhaocong updated the diff for D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask.
Mar 14 2022, 6:03 AM · Restricted Project, Restricted Project
Luhaocong requested review of D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask.
Mar 14 2022, 5:55 AM · Restricted Project, Restricted Project

Feb 24 2022

Luhaocong added a comment to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

ping...

Feb 24 2022, 6:21 PM · Restricted Project

Feb 16 2022

Luhaocong updated the diff for D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

update test case

Feb 16 2022, 6:49 PM · Restricted Project
Luhaocong added a comment to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

Do you have test case?

Feb 16 2022, 5:51 PM · Restricted Project
Luhaocong updated the diff for D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

upload a test case

Feb 16 2022, 5:46 PM · Restricted Project
Luhaocong requested review of D119934: [RISCV] Fix a mistake in PostprocessISelDAG.
Feb 16 2022, 4:52 AM · Restricted Project

Feb 14 2022

Luhaocong added a comment to D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

I objected and still believe this patch is fundamentally wrong. The problem needs solving elsewhere, not like this. Please revert.

Although this solution is far from perfect, it does improve code quality. Could you please show a test case that gets wrong or worse assembly by this patch?
I suggest we can keep it and go on searching better solutions.

I don't know, but I don't really care, it is blatantly wrong to say LUI rd, <imm> is not as cheap as a move, especially so to say LUI rd, %hi(x) isn't but LUI rd, x is, it's complete nonsense. There are lots of things you can commit that would improve codegen quality but are totally wrong and would get backed out immediately.

Feb 14 2022, 11:56 PM · Restricted Project

Feb 9 2022

Luhaocong added a comment to D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

This seems conceptually wrong to me. isAsCheapAsAMove is meant to model how expensive an instruction is to execute, but how you compute the immediate it uses has zero bearing on that. lui rd, 0x123 and lui rd, %hi(sym) if %hi(sym) happens to be 0x123 are completely indistinguishable from the perspective of the processor. To me this screams of something elsewhere getting cost modelling wrong.

Maybe the heuristic #1 should ignore the isCheapAsMove if the instruction isTriviallyRematerializable?

So the problem is that LUI _is_ current marked as cheap as a move, since we set isAsCheapAsAMove to 1 on the TableGen record, and the default case falls back on that value. What this patch does is override that and make LUIs that are part of address computations _not_ as cheap as a move.

Feb 9 2022, 3:45 AM · Restricted Project
Luhaocong added a comment to D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

The only issue I have is that the description is specifically talking about arrays' base addresses but the change has wider-reaching consequences than just LICM: CSE, register allocation, sinking, etc. It's not even a loop-unroll specific change, right? This would apply to non-unrolled loops too, presumably.

So for me it'd be best for:
a) the commit title to reflect the code change itself
b) the description to describe why "MO_HI" is not as cheap as a move in principle
c) use array base address rematerialization as one motivating example.

Feb 9 2022, 2:48 AM · Restricted Project
Luhaocong updated the diff for D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

modify description

Feb 9 2022, 2:41 AM · Restricted Project
Luhaocong updated the diff for D118218: [RISCV] Pre-commit test for D118216.

delete unnecessary CHECK

Feb 9 2022, 2:36 AM · Restricted Project

Feb 8 2022

Luhaocong abandoned D116398: [SelectionDAG][RISCV] Add preferred extend of value used for PHI node.
Feb 8 2022, 12:28 AM · Restricted Project

Feb 7 2022

Luhaocong added reviewers for D118218: [RISCV] Pre-commit test for D118216: craig.topper, jrtc27.
Feb 7 2022, 6:13 PM · Restricted Project

Feb 6 2022

Luhaocong updated the diff for D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

update test case.

Feb 6 2022, 5:56 PM · Restricted Project
Luhaocong updated the diff for D118218: [RISCV] Pre-commit test for D118216.
  1. Add test for rv64.
  2. Add description of test case.
Feb 6 2022, 5:54 PM · Restricted Project

Jan 26 2022

Luhaocong retitled D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove from [RISCV][NFC] eliminate rematerialization of array's base address to [RISCV] eliminate rematerialization of array's base address.
Jan 26 2022, 5:21 PM · Restricted Project
Luhaocong requested review of D118218: [RISCV] Pre-commit test for D118216.
Jan 26 2022, 12:03 AM · Restricted Project
Luhaocong retitled D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove from [RISCV][NFC] eliminate rematerialization ofarray's base address to [RISCV][NFC] eliminate rematerialization of array's base address.
Jan 26 2022, 12:00 AM · Restricted Project

Jan 25 2022

Luhaocong requested review of D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.
Jan 25 2022, 11:46 PM · Restricted Project

Jan 10 2022

Luhaocong updated the diff for D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled.

rebase and update test cases

Jan 10 2022, 5:01 AM · Restricted Project

Jan 6 2022

Luhaocong updated the diff for D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled.

update pattern

Jan 6 2022, 6:48 PM · Restricted Project
Luhaocong updated the diff for D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled.

Generalise this optimization

Jan 6 2022, 4:49 AM · Restricted Project
Luhaocong added a comment to D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled.

The AND could be better for loops if LICM can move the constant materialization out of the loop.

I’ve wondered about doing this as a machine IR peephole after LICM has its chance. But I haven’t spent any time on it.

Jan 6 2022, 12:48 AM · Restricted Project

Jan 5 2022

Luhaocong requested review of D116720: [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled.
Jan 5 2022, 7:42 PM · Restricted Project

Jan 3 2022

Luhaocong added a comment to D116398: [SelectionDAG][RISCV] Add preferred extend of value used for PHI node.

With this optimization, we could perform bit extend in necessary BB,instead of all predecessors of
return BB. At the same time, increase more machine CSE opportunities.

Why would the extend be in all predecessors? Wouldn't it just be in the block with the return?

Wouldn't this patch increase code size if none of the phi inputs were known to be sign extended? Your test just moves an extend to the block that produced %conv2 because %left and %right are already extended. But if they weren't wouldn't it increase the number of extends?

Jan 3 2022, 10:58 PM · Restricted Project
Luhaocong added a comment to D116398: [SelectionDAG][RISCV] Add preferred extend of value used for PHI node.

The test case is quite complicated for what should be a simple thing to test. and is rather redundant in its IR; ignoring the nsw aspect, sext+sub+trunc is just sub of the smaller type, and the sext+icmp can just be icmp of the smaller type. Changing the latter seems to have no effect on the generated code, but for whatever reason changing the former to just sub on i16 already sign-extends at the computation site. Also, your ; preds comments don't belong in IR tests, and the naming looks like you just took Clang output and hacked it into a test.

define signext i16 @foo(i16 signext %a, i1 zeroext %b) {
entry:
  br i1 %b, label %add, label %ret

add:
  %0 = add i16 %a, 1
  br label %ret

ret:
  %1 = phi i16 [ %a, %entry ], [ %0, %add ]
  ret i16 %1
}

is a much simpler from-scratch test that should show the behaviour you want.

Jan 3 2022, 10:45 PM · Restricted Project
Luhaocong updated the diff for D116398: [SelectionDAG][RISCV] Add preferred extend of value used for PHI node.
  1. fix failed test case.
  2. To avoid increasing the loop body, we exclude values within the loop,
Jan 3 2022, 10:42 PM · Restricted Project

Dec 30 2021

Luhaocong requested review of D116398: [SelectionDAG][RISCV] Add preferred extend of value used for PHI node.
Dec 30 2021, 1:01 AM · Restricted Project

Dec 19 2021

Luhaocong added a comment to D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info.

ping. Hi everyone, can you please help me review?

Dec 19 2021, 7:34 PM · Restricted Project

Dec 12 2021

Luhaocong added a reviewer for D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info: kito-cheng.
Dec 12 2021, 6:24 PM · Restricted Project
Luhaocong updated the diff for D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info.

re-upload with full context

Dec 12 2021, 6:19 PM · Restricted Project
Luhaocong retitled D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info from [RISCV] Fix upper bound of RISC-V V type in debug info to [Clang][RISCV] Fix upper bound of RISC-V V type in debug info.
Dec 12 2021, 5:18 PM · Restricted Project

Dec 9 2021

Luhaocong requested review of D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info.
Dec 9 2021, 12:30 AM · Restricted Project

Dec 8 2021

Luhaocong updated Luhaocong.
Dec 8 2021, 6:49 PM