[SPIRV 1/6] Add stub for SPIRV backend

[iliya-diyachkov]

Summary

This patch contains enough for lib/Target/SPIRV to compile: a basic SPIRVTargetMachine and SPIRVTargetInfo.

Triples for SPIRV were recently added (see D109144).

[efriedma]

I don't see any recent discussion of this project on llvm-dev. Please make sure you send an email to llvm-dev stating your plan to land an experimental SPIRV target, and explains how it meets the requirements outlined at https://llvm.org/docs/DeveloperPolicy.html#adding-a-new-target . (I don't see any issue meeting those requirements, but let's make sure everyone is on the same page.)

[konrad.trifunovic]

Just to clarify, the high level design for the proposal has been sent to llvm-dev in March this year.

https://lists.llvm.org/pipermail/llvm-dev/2021-March/148905.html

But I agree, we should send some heads up announcement that we are starting to land patches and they are going to be an experimental backend.

[konrad.trifunovic]

Ilya has posted an official RFC announcing the upstream of SPIR-V backend as an experimental target:
https://lists.llvm.org/pipermail/llvm-dev/2021-December/154270.html

[iliya-diyachkov]

Gentle ping.

[tschuett]

You could mark the other revisions as child revisions with Edit Related Revisions... at the top right.

[rengolin]

Hi, I only saw that now.

In addition to adding the rest of the reviews as a child to this one, can you also please number them accordingly?

Please use 1/10, 2/10, etc. instead of 1/n, 2/n. It makes no sense to have a '/n'.

Also, make sure that the last patch allows the target to do something substantial (with tests), for example, parse/lower assembly instructions, lower a simple function with return, etc.

Once the first series is complete, you don't need to number the patches any more. That's the whole point of the '/n', to separate the before, where nothing works, with the after, where things progressively work better.

Finally, just a reminder that you should not merge any patch in the initial series until *all* patches in the series have been approved. This is crucial to avoid reverting patches on a half-implemented back-end.

Thanks!
Renato

[iliya-diyachkov]

Hi Renato. Great thanks for your clear explanation! We'll rename the patches and provide the complete series for review.

[iliya-diyachkov]

It's a small update with capitalized names of variables.

[rengolin]

Hi, this looks good as the first patch. Will keep looking for the others.

[iliya-diyachkov]

Confusing comment in SPIRVTargetMachine.cpp was removed.

[MaskRay]

Other than the regular -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=on builds, it's good to ensure a few others work:

• -DBUILD_SHARED_LIBS=on ensure CMake build dependency is correct. The mode uses -Wl,-z,defs to link shared objects. It has some dependency checking effects: https://maskray.me/blog/2021-06-13-dependency-related-linker-options#z-defs)
• -DLLVM_LINK_LLVM_DYLIB=on -DCLANG_LINK_CLANG_DYLIB=on: somewhat covered by -DBUILD_SHARED_LIBS=on, but not bad to ensure it works as many Linux distros have shifted to this mode
• -DLLVM_ENABLE_EXPENSIVE_CHECKS=on -DLLVM_ENABLE_ABI_BREAKING_CHECKS=on
• omitting -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=SPIRV works

[arsenm]

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

40

Don’t need .hasValue()

[iliya-diyachkov]

Ok, after fixing the issues in all patches I'll check these builds.

[iliya-diyachkov]

SPIRVTargetMachine.cpp was fixed.

[mpaszkowski]

Thank you to everyone for all the suggestions and feedback. In the recent weeks we have resolved all the comments and submitted all the necessary fixes to the initial six submitted patches:

1. SPIRV 1/6 Add stub for SPIRV backend
2. SPIRV 2/6 Add SPIRV {InstrFormats,InstrInfo,RegisterInfo,RegisterBanks...}.td
3. SPIRV 3/6 Add MC layer, object file support and InstPrinter
4. SPIRV 4/6 Add target lowerling, TargetMachine and AsmPrinter
5. SPIRV 5/6 Add LegalizerInfo, InstructionSelector and utilities
6. SPIRV 6/6 Add 2 essential passes and the simplest tests

Right now all the patches are passing buildbot builds and checks (with the exception of a single clang-format comment on the common across all targets Triple.cpp file in the third patch). We would love to ask you for the final review and LGTM of the backend stub and the six patches above as a whole, so we will be able to push the changes to the trunk soon.

[iliya-diyachkov]

I also want to express my gratitude to the reviewers.

In addition to the regular builds, I also checked the special ones that Fengrui Song listed earlier (all with and without -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=SPIRV). I fixed a few issues in the 3th-6th patches, so now all additional builds (as well as the regular ones) are build-able, and built llcs successfully pass LIT testing (including added SPIRV's LIT tests).

We look forward to the final feedback or further comments on the code.

[rengolin]

In D115009#3288320, @iliya-diyachkov wrote:

In addition to the regular builds, I also checked the special ones that Fengrui Song listed earlier (all with and without -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=SPIRV). I fixed a few issues in the 3th-6th patches, so now all additional builds (as well as the regular ones) are build-able, and built llcs successfully pass LIT testing (including added SPIRV's LIT tests).

Great! That's a good shape to have the initial series. Thanks for the hard work!

[rengolin]

This looks good to me as the first patch.

If others still have comments, please don't shy on posting them. If not, feel free to approve, too.

[rengolin]

@MaskRay last round?

[MaskRay]

In D115009#3289851, @rengolin wrote:

@MaskRay last round?

Thanks for tagging me. Will look:)

llvm/CODE_OWNERS.TXT

 
 N: Martin Storsjö
 E: [e-mail]
 D: MinGW
 
 N: Zi Xuan Wu (Zeson)
 E: [e-mail]
 D: C-SKY backend (lib/Target/CSKY/*)
+
+N: Ilia Diachkov
+E: [e-mail]
+D: SPIR-V backend (lib/Target/SPIRV/*)

llvm/docs/CompilerWriterInfo.rst

 * `Overview of ARM32 ABI Conventions <https://docs.microsoft.com/en-us/cpp/build/overview-of-arm-abi-conventions>`_
 
 NVPTX
 =====
 
 * `CUDA Documentation <http://docs.nvidia.com/cuda/index.html>`_ includes the PTX
   ISA and Driver API documentation
 
+SPIR-V
+======
+
+* `SPIR-V documentation <https://www.khronos.org/registry/SPIR-V/>`_
+
 Miscellaneous Resources
 =======================
 
 * `Executable File Format library <http://www.nondot.org/sabre/os/articles/ExecutableFileFormats/>`_
 
 * `GCC prefetch project <http://gcc.gnu.org/projects/prefetch.html>`_ page has a
   good survey of the prefetching capabilities of a variety of modern
   processors.

llvm/lib/Target/SPIRV/CMakeLists.txt

+add_llvm_component_group(SPIRV)
+
+add_llvm_target(SPIRVCodeGen
+  SPIRVTargetMachine.cpp
+
+  LINK_COMPONENTS
+  CodeGen
+  Core
+  SPIRVInfo
+  Support
+  Target
+
+  ADD_TO_COMPONENT
+  SPIRV
+  )
+
+add_subdirectory(TargetInfo)

llvm/lib/Target/SPIRV/SPIRVTargetMachine.h

+//===-- SPIRVTargetMachine.h - Define TargetMachine for SPIR-V -*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the SPIR-V specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVTARGETMACHINE_H
+#define LLVM_LIB_TARGET_SPIRV_SPIRVTARGETMACHINE_H
+
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
+
+namespace llvm {
+class SPIRVTargetMachine : public LLVMTargetMachine {
+  std::unique_ptr<TargetLoweringObjectFile> TLOF;
+
+public:
+  SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                     StringRef FS, const TargetOptions &Options,
+                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+                     CodeGenOpt::Level OL, bool JIT);
+
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+  TargetLoweringObjectFile *getObjFileLowering() const override {
+    return TLOF.get();
+  }
+};
+} // namespace llvm
+
+#endif

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

+//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Implements the info about SPIR-V target spec.
+//
+//===----------------------------------------------------------------------===//
+
+#include "SPIRVTargetMachine.h"
+#include "TargetInfo/SPIRVTargetInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/MC/TargetRegistry.h"
+
+using namespace llvm;
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget() {
+  // Register the target.
+  RegisterTargetMachine<SPIRVTargetMachine> X(getTheSPIRV32Target());
+  RegisterTargetMachine<SPIRVTargetMachine> Y(getTheSPIRV64Target());
+}
+
+static std::string computeDataLayout(const Triple &TT) {
+  std::string DataLayout = "e-m:e";
+
+  const auto Arch = TT.getArch();
+  if (Arch == Triple::spirv32)
+    DataLayout += "-p:32:32";
+  else if (Arch == Triple::spirv64)
+    DataLayout += "-p:64:64";
+  return DataLayout;
+}
+
+static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
+  if (!RM)
+    return Reloc::PIC_;
+  return *RM;
+}
+
+SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
+                                       StringRef CPU, StringRef FS,
+                                       const TargetOptions &Options,
+                                       Optional<Reloc::Model> RM,
+                                       Optional<CodeModel::Model> CM,
+                                       CodeGenOpt::Level OL, bool JIT)
+    : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
+                        getEffectiveRelocModel(RM),
+                        getEffectiveCodeModel(CM, CodeModel::Small), OL),
+      TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
+  initAsmInfo();
+}
+
+namespace {
+// SPIR-V Code Generator Pass Configuration Options.
+class SPIRVPassConfig : public TargetPassConfig {
+public:
+  SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
+      : TargetPassConfig(TM, PM) {}
+
+  SPIRVTargetMachine &getSPIRVTargetMachine() const {
+    return getTM<SPIRVTargetMachine>();
+  }
+};
+} // namespace
+
+TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) {
+  return new SPIRVPassConfig(*this, PM);
+}

llvm/lib/Target/SPIRV/TargetInfo/CMakeLists.txt

+add_llvm_component_library(LLVMSPIRVInfo
+  SPIRVTargetInfo.cpp
+
+  LINK_COMPONENTS
+  MC
+  Support
+
+  ADD_TO_COMPONENT
+  SPIRV
+  )

llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.h

+//===-- SPIRVTargetInfo.h - SPIRV Target Implementation ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPIRV_TARGETINFO_SPIRVTARGETINFO_H
+#define LLVM_LIB_TARGET_SPIRV_TARGETINFO_SPIRVTARGETINFO_H
+
+namespace llvm {
+
+class Target;
+
+Target &getTheSPIRV32Target();
+Target &getTheSPIRV64Target();
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_SPIRV_TARGETINFO_SPIRVTARGETINFO_H

llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp

+//===-- SPIRVTargetInfo.cpp - SPIR-V Target Implementation ----*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "TargetInfo/SPIRVTargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+
+using namespace llvm;
+
+Target &llvm::getTheSPIRV32Target() {
+  static Target TheSPIRV32Target;
+  return TheSPIRV32Target;
+}
+Target &llvm::getTheSPIRV64Target() {
+  static Target TheSPIRV64Target;
+  return TheSPIRV64Target;
+}
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTargetInfo() {
+  RegisterTarget<Triple::spirv32> X(getTheSPIRV32Target(), "spirv32",
+                                    "SPIR-V 32-bit", "SPIRV");
+  RegisterTarget<Triple::spirv64> Y(getTheSPIRV64Target(), "spirv64",
+                                    "SPIR-V 64-bit", "SPIRV");
+}
+
+// FIXME: Temporary stub - this function must be defined for linking
+// to succeed and will be called unconditionally by llc, so must be a no-op.
+// Remove once this function is properly implemented.
+extern "C" void LLVMInitializeSPIRVTargetMC() {}