This is an archive of the discontinued LLVM Phabricator instance.

Differential D113527

[RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/rint/trunc intrinsics to f32 libcalls.
ClosedPublic

Authored by craig.topper on Nov 9 2021, 4:59 PM.

Details

Reviewers
HsiangKai
evandro
khchen
frasercrmck
rogfer01
jrtc27
arcbbb
asb
luismarques
Commits
rGee7a006ce461: [RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/rint/trunc intrinsics…
Summary

Previously these would crash. I don't think these can be generated
directly from C. Not sure if any optimizations can introduce them.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 9 2021, 4:59 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptNov 9 2021, 4:59 PM
craig.topper requested review of this revision.Nov 9 2021, 4:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 9 2021, 4:59 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added reviewers: asb, luismarques.Nov 9 2021, 5:06 PM
Harbormaster completed remote builds in B133384: Diff 386016.Nov 9 2021, 6:02 PM
asb accepted this revision.Nov 11 2021, 2:13 AM
This revision is now accepted and ready to land.Nov 11 2021, 2:13 AM
This revision was landed with ongoing or failed builds.Nov 11 2021, 8:32 AM
Closed by commit rGee7a006ce461: [RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/rint/trunc intrinsics… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGee7a006ce461: [RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/rint/trunc intrinsics….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines
test/
CodeGen/
RISCV/
350 lines

Diff 386016

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 323 Lines • ▼ Show 20 Lines if (Subtarget.hasStdExtZfh()) {
setOperationAction(ISD::LLROUND, MVT::f16, Legal); setOperationAction(ISD::LLROUND, MVT::f16, Legal);
for (auto CC : FPCCToExpand) for (auto CC : FPCCToExpand)
setCondCodeAction(CC, MVT::f16, Expand); setCondCodeAction(CC, MVT::f16, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f16, Expand); setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
setOperationAction(ISD::SELECT, MVT::f16, Custom); setOperationAction(ISD::SELECT, MVT::f16, Custom);
setOperationAction(ISD::BR_CC, MVT::f16, Expand); setOperationAction(ISD::BR_CC, MVT::f16, Expand);
for (auto Op : FPOpToExpand) for (auto Op : FPOpToExpand)
setOperationAction(Op, MVT::f16, Expand); setOperationAction(Op, MVT::f16, Expand);
setOperationAction(ISD::FCEIL, MVT::f16, Promote);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    setOperationAction(ISD::FCEIL,       MVT::f16,  Promote);
-    setOperationAction(ISD::FFLOOR,      MVT::f16,  Promote);
-    setOperationAction(ISD::FNEARBYINT,  MVT::f16,  Promote);
-    setOperationAction(ISD::FRINT,       MVT::f16,  Promote);
-    setOperationAction(ISD::FROUND,      MVT::f16,  Promote);
-    setOperationAction(ISD::FROUNDEVEN,  MVT::f16,  Promote);
-    setOperationAction(ISD::FTRUNC,      MVT::f16,  Promote);
+    setOperationAction(ISD::FCEIL, MVT::f16, Promote);
+    setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
+    setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);

4 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - setOperationAction(ISD::FCEIL, MVT::f16…
setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
setOperationAction(ISD::FRINT, MVT::f16, Promote);
setOperationAction(ISD::FROUND, MVT::f16, Promote);
setOperationAction(ISD::FROUNDEVEN, MVT::f16, Promote);
setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
} }
if (Subtarget.hasStdExtF()) { if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal); setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
setOperationAction(ISD::LRINT, MVT::f32, Legal); setOperationAction(ISD::LRINT, MVT::f32, Legal);
setOperationAction(ISD::LLRINT, MVT::f32, Legal); setOperationAction(ISD::LLRINT, MVT::f32, Legal);
setOperationAction(ISD::LROUND, MVT::f32, Legal); setOperationAction(ISD::LROUND, MVT::f32, Legal);
▲ Show 20 Lines • Show All 9,623 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-intrinsics.ll

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
; RV64IDZFH-LABEL: copysign_f16: ; RV64IDZFH-LABEL: copysign_f16:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1 ; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%1 = call half @llvm.copysign.f16(half %a, half %b) %1 = call half @llvm.copysign.f16(half %a, half %b)
ret half %1 ret half %1
} }
declare half @llvm.floor.f16(half)
define half @floor_f16(half %a) nounwind {
; RV32IZFH-LABEL: floor_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: floor_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call floorf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: floor_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call floorf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: floor_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call floorf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.floor.f16(half %a)
ret half %1
}
declare half @llvm.ceil.f16(half)
define half @ceil_f16(half %a) nounwind {
; RV32IZFH-LABEL: ceil_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: ceil_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call ceilf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: ceil_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call ceilf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: ceil_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call ceilf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.ceil.f16(half %a)
ret half %1
}
declare half @llvm.trunc.f16(half)
define half @trunc_f16(half %a) nounwind {
; RV32IZFH-LABEL: trunc_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: trunc_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call truncf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: trunc_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call truncf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: trunc_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call truncf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.trunc.f16(half %a)
ret half %1
}
declare half @llvm.rint.f16(half)
define half @rint_f16(half %a) nounwind {
; RV32IZFH-LABEL: rint_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call rintf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: rint_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call rintf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: rint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call rintf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: rint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call rintf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.rint.f16(half %a)
ret half %1
}
declare half @llvm.nearbyint.f16(half)
define half @nearbyint_f16(half %a) nounwind {
; RV32IZFH-LABEL: nearbyint_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call nearbyintf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: nearbyint_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call nearbyintf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: nearbyint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call nearbyintf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: nearbyint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call nearbyintf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.nearbyint.f16(half %a)
ret half %1
}
declare half @llvm.round.f16(half)
define half @round_f16(half %a) nounwind {
; RV32IZFH-LABEL: round_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: round_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call roundf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: round_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call roundf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: round_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call roundf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.round.f16(half %a)
ret half %1
}
declare half @llvm.roundeven.f16(half)
define half @roundeven_f16(half %a) nounwind {
; RV32IZFH-LABEL: roundeven_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: roundeven_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: call roundevenf@plt
; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: roundeven_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call roundevenf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: roundeven_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -16
; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: call roundevenf@plt
; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 16
; RV64IDZFH-NEXT: ret
%1 = call half @llvm.roundeven.f16(half %a)
ret half %1
}
declare iXLen @llvm.lrint.iXLen.f16(float) declare iXLen @llvm.lrint.iXLen.f16(float)
define iXLen @lrint_f16(float %a) nounwind { define iXLen @lrint_f16(float %a) nounwind {
; RV32IZFH-LABEL: lrint_f16: ; RV32IZFH-LABEL: lrint_f16:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.w.s a0, fa0 ; RV32IZFH-NEXT: fcvt.w.s a0, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines