[RISCV] Split RISCV vector builtins into their own file and namespace.

[craig.topper]

Summary

Similar to SVE, this separates the RVV builtlins into their own
region of builtin IDs. Only those IDs are allowed to be used by
the builtin_alias attribute now.

[HsiangKai]

LGTM.

clang/include/clang/Basic/BuiltinsRISCV.def

 // this file must define the BUILTIN macro to make use of this information.
 //
 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
-#include "clang/Basic/riscv_vector_builtins.inc"
-
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
 
 // Zbc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")

clang/include/clang/Basic/BuiltinsRISCVVector.def

+//==- BuiltinsRISCVVector.def - RISC-V Vector Builtin Database ---*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the RISC-V-specific builtin function database.  Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
+#   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
+#endif
+
+#include "clang/Basic/riscv_vector_builtins.inc"
+
+#undef BUILTIN
+#undef TARGET_BUILTIN

clang/include/clang/Basic/TargetBuiltins.h

 //===--- TargetBuiltins.h - Target specific builtin IDs ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
#include "clang/Basic/BuiltinsX86_64.def"
   };
   }
 
   /// VE builtins
   namespace VE {
   enum { LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, LastTSBuiltin };
   }
 
+  namespace RISCVVector {
+  enum {
+    LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsRISCVVector.def"
+    FirstTSBuiltin,
+  };
+  }
+
   /// RISCV builtins
   namespace RISCV {
   enum {
     LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+    FirstRVVBuiltin = clang::Builtin::FirstTSBuiltin,
+    LastRVVBuiltin = RISCVVector::FirstTSBuiltin - 1,
 #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
 #include "clang/Basic/BuiltinsRISCV.def"
     LastTSBuiltin
   };
   } // namespace RISCV
 
   /// Flags to identify the types for overloaded Neon builtins.
   ///

clang/include/clang/module.modulemap

module Clang_Basic {
   textual header "Basic/BuiltinsHexagon.def"
   textual header "Basic/BuiltinsHexagonDep.def"
   textual header "Basic/BuiltinsHexagonMapCustomDep.def"
   textual header "Basic/BuiltinsMips.def"
   textual header "Basic/BuiltinsNEON.def"
   textual header "Basic/BuiltinsNVPTX.def"
   textual header "Basic/BuiltinsPPC.def"
   textual header "Basic/BuiltinsRISCV.def"
+  textual header "Basic/BuiltinsRISCVVector.def"
   textual header "Basic/BuiltinsSVE.def"
   textual header "Basic/BuiltinsSystemZ.def"
   textual header "Basic/BuiltinsWebAssembly.def"
   textual header "Basic/BuiltinsX86.def"
   textual header "Basic/BuiltinsX86_64.def"
   textual header "Basic/BuiltinsXCore.def"
   textual header "Basic/CodeGenOptions.def"
   textual header "Basic/DiagnosticOptions.def"

clang/lib/Basic/Targets/RISCV.cpp

 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasZvlsseg)
     Builder.defineMacro("__riscv_zvlsseg", "10000");
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
     {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
+#include "clang/Basic/BuiltinsRISCVVector.def"
+#define BUILTIN(ID, TYPE, ATTRS)                                               \
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
+    {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
 #include "clang/Basic/BuiltinsRISCV.def"
 };
 
 ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
   return llvm::makeArrayRef(BuiltinInfo, clang::RISCV::LastTSBuiltin -
                                              Builtin::FirstTSBuiltin);
 }
 

clang/lib/Sema/SemaChecking.cpp

 //===- SemaChecking.cpp - Extra Semantic Checking -------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (StringRef F : ReqFeatures) {
     Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
         << TheCall->getSourceRange() << StringRef(FeatureStr);
   }
 
   if (FeatureMissing)
     return true;
 
   switch (BuiltinID) {
-  case RISCV::BI__builtin_rvv_vsetvli:
+  case RISCVVector::BI__builtin_rvv_vsetvli:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) ||
            CheckRISCVLMUL(TheCall, 2);
-  case RISCV::BI__builtin_rvv_vsetvlimax:
+  case RISCVVector::BI__builtin_rvv_vsetvlimax:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
            CheckRISCVLMUL(TheCall, 1);
-  case RISCV::BI__builtin_rvv_vget_v_i8m2_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m2_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m2_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m2_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m2_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m2_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m2_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m2_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m2_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m2_u64m1:
-  case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m2:
-  case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m2:
-  case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m2:
-  case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m2:
-  case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m2:
-  case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m2:
-  case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m2:
-  case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m2:
-  case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m2:
-  case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m2:
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m4:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m4:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m4:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m4:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m4:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m4:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m4:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m4:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m4:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m2_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m2_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m2_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m2_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m2_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m2_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m2_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m2_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m2_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m2_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m4_i8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m4_i16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m4_i32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m4_i64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m4_f32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m4_f64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m4_u8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m4_u16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m4_u32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m4_u64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m4:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m4:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
-  case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m1:
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m2:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m2:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m2:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m2:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m2:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m2:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m2:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m2:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m2:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m4_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m4_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m4_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m4_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m4_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m4_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m4_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m4_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m4_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m4_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m2:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m2:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
-  case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m1:
-  case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m1:
-  case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m1:
-  case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m1:
-  case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m1:
-  case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m1:
-  case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m1:
-  case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m1:
-  case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m1:
-  case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i8m8_i8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i16m8_i16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i32m8_i32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_i64m8_i64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f32m8_f32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_f64m8_f64m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u8m8_u8m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u16m8_u16m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u32m8_u32m1:
+  case RISCVVector::BI__builtin_rvv_vget_v_u64m8_u64m1:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m2:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m2:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m2:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m2:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m2:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m2:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m2:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m2:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m2:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m2:
-  case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m4:
-  case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m4:
-  case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m4:
-  case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m4:
-  case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m4:
-  case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m4:
-  case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m4:
-  case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m4:
-  case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m4:
-  case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m4:
-  case RISCV::BI__builtin_rvv_vset_v_i8m4_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m4_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m4_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m4_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m4_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m4_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m4_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m4_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m4_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m4_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m2:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m2_i8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m2_i16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m2_i32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m2_i64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m2_f32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m2_f64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m2_u8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m2_u16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m2_u32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m2_u64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m4_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m4_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m4_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m4_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m4_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m4_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m4_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m4_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m4_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m4_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m4:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m4:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m4:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m4:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m4:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m4:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m4:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m4:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m4:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m4:
-  case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m4:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m2_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m2_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m2_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m2_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m2_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m2_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m2_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m2_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m2_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m2_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
-  case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m8:
-  case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m8:
-  case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m8:
-  case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m8:
-  case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m8:
-  case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m8:
-  case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m8:
-  case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m8:
-  case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m8:
-  case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i8m1_i8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i16m1_i16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i32m1_i32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_i64m1_i64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f32m1_f32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_f64m1_f64m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u8m1_u8m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u16m1_u16m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u32m1_u32m8:
+  case RISCVVector::BI__builtin_rvv_vset_v_u64m1_u64m8:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
   }
 
   return false;
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
                                            CallExpr *TheCall) {

clang/lib/Sema/SemaDeclAttr.cpp

 //===--- SemaDeclAttr.cpp - Declaration Attribute Handling ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if ((IsAArch64 && !ArmSveAliasValid(S.Context, BuiltinID, AliasName)) ||
     S.Diag(AL.getLoc(), diag::err_attribute_arm_builtin_alias);
     return;
   }
 
   D->addAttr(::new (S.Context) ArmBuiltinAliasAttr(S.Context, AL, Ident));
 }
 
 static bool RISCVAliasValid(unsigned BuiltinID, StringRef AliasName) {
-  return BuiltinID >= Builtin::FirstTSBuiltin &&
-         BuiltinID < RISCV::LastTSBuiltin;
+  return BuiltinID >= RISCV::FirstRVVBuiltin &&
+         BuiltinID <= RISCV::LastRVVBuiltin;
 }
 
 static void handleBuiltinAliasAttr(Sema &S, Decl *D,
                                         const ParsedAttr &AL) {
   if (!AL.isArgIdent(0)) {
     S.Diag(AL.getLoc(), diag::err_attribute_argument_n_type)
         << AL << 1 << AANT_ArgumentIdentifier;
     return;

clang/utils/TableGen/RISCVVEmitter.cpp

 //===- RISCVVEmitter.cpp - Generate riscv_vector.h for use with clang -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RVVEmitter::createCodeGen(raw_ostream &OS) {
   RVVIntrinsic *PrevDef = Defs.begin()->get();
   for (auto &Def : Defs) {
     StringRef CurIRName = Def->getIRName();
     if (CurIRName != PrevDef->getIRName() ||
         (Def->getManualCodegen() != PrevDef->getManualCodegen())) {
       PrevDef->emitCodeGenSwitchBody(OS);
     }
     PrevDef = Def.get();
-    OS << "case RISCV::BI__builtin_rvv_" << Def->getName() << ":\n";
+    OS << "case RISCVVector::BI__builtin_rvv_" << Def->getName() << ":\n";
   }
   Defs.back()->emitCodeGenSwitchBody(OS);
   OS << "\n";
 }
 
 void RVVEmitter::parsePrototypes(StringRef Prototypes,
                                  std::function<void(StringRef)> Handler) {
   const StringRef Primaries("evwqom0ztul");