[RISCV] Fold store of vmv.x.s to a vse with VL=1.

[craig.topper]

Summary

This can avoid a loss of decoupling with the scalar unit on cores
with decoupled scalar and vector units.

We should support FP too, but those use extract_element and not a
custom ISD node so it is a little different. I also left a FIXME
in the test for i64 extract and store on RV32.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7132

I was wondering what'd happen if you replaced it with a ISD::VP_STORE. Just thinking that a standard node would potentially provide more optimization opportunities compared to a RISCVISD node.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7132

If I'm reading the code right, we don't recognize VP_STORE with an all ones mask as special and I think we'll end up lowering it to the vse_mask intrinsic.

[craig.topper]

Use VP_STORE. I couldn't copy the MachineMemOperand and had to have getStoreVP rebuild it. This is due to getStoreVP not taking the MemVT as an argument. This caused an assert if the MemOperand size, which was correctly one element, didn't match the VP_STORE VT. So now we have a MemOperand with an unknown size I guess.

[frasercrmck]

LGTM but I think you have a couple of test failures there?

[craig.topper]

In D109482#3023981, @frasercrmck wrote:

LGTM but I think you have a couple of test failures there?

Those may have ran while the vp.store with all ones mask patch was still outstanding. Everything passes with ninja check-llvm right now.