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[RISCV][VP] Custom lower VP_STORE and VP_LOAD

Authored by frasercrmck on Aug 31 2021, 8:01 AM.



This patch adds support for the vector-predicated VP_STORE and
VP_LOAD nodes. We do this in the same way we lower MSTORE and
MLOAD: to regular load/store instructions via intrinsics.

One necessary change was made to SelectionDAGLegalize so that
VP_STORE nodes' operation actions are taken from the stored "value"
operands, in the same vein as STORE or MSTORE.

Diff Detail

Unit TestsFailed

Event Timeline

frasercrmck created this revision.Aug 31 2021, 8:01 AM
frasercrmck requested review of this revision.Aug 31 2021, 8:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 31 2021, 8:01 AM
frasercrmck retitled this revision from [RISCV] Custom lower VP_STORE and VP_LOAD to [RISCV][VP] Custom lower VP_STORE and VP_LOAD.
rogfer01 accepted this revision.Sep 1 2021, 11:23 PM

LGTM. Thanks @frasercrmck !

This revision is now accepted and ready to land.Sep 1 2021, 11:23 PM
  • remove IsVP in a similar vein to D108987
  • rebase
  • use common MemSDNode base
This revision was landed with ongoing or failed builds.Sep 7 2021, 3:03 AM
This revision was automatically updated to reflect the committed changes.