[PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-features'.

[khchen]

Summary

riscv-isa-features records the march information for a module.
RISCVAsmPrinter reads the riscv-isa-features to generate corrent arch
attribute if -mattr is missing.

Currently RISC-V encodes arch information in function attribute
'target-features', so there are two issues we want to fix.

1. In IFUNC case (ex. https://godbolt.org/z/a1oTbacn9), the final arch

attribute information is ambiguous because one compilation unit have
different target-feature value in function attribute.
We could not just union of all target-features, because in IFUNC case,
the base arch string is excepted in elf arch attribute.

2. During the LTO, clang driver will not pass -march option to LTO code

generator, because users maybe specify the incorrect -march value if
some linked external libraries have been compiled with different arch
extensions.

The probably way is adding a new module flag metadata, riscv-isa-features,
to records -march info for one compilation unit, and each
riscv-isa-features get combined when linking.

In this PoC patch, I think the potential issue is illegal arch combination
will report an error in code generation stage, not in linking stage.
(For example, zfinx is conflict with f/d/q, and Zceb and Zcec are
conflict with d).
I'm not sure having a target dependence behaivor in bitcode linking does
make sense or not.

Thanks for @jrtc27, @MaskRay to address this issue in D102926 and
D102925, and @kito-cheng's reminder of exclusive extensions issue.

[jrtc27]

Why can't we just save target-features itself as a module flag instead of inventing yet another equivalent encoding? Especially since a long bitfield is brittle, you can't reorder or remove elements without breaking bitcode compatibility.

[khchen]

In D106347#2890123, @jrtc27 wrote:

Why can't we just save target-features itself as a module flag instead of inventing yet another equivalent encoding? Especially since a long bitfield is brittle, you can't reorder or remove elements without breaking bitcode compatibility.

I think the benefit of using bitfield is making link behavior simpler. I will try to investigate another link behavior to handle two different target-features strings especially have + or -.

[khchen]

store target-features string as module flag.

[jrtc27]

clang/lib/CodeGen/CodeGenModule.cpp

835

Why is this building a list? Just use a string so it's in the same format as the function attributes? We already have parsers for that. Yes, it means you do a small amount of redundant work but having a single format in the IR for representing the same thing in every place is better than having multiple different ways of representing the same thing.

843

Just like we call it target-abi not riscv-abi, this should just be called target-features.

llvm/lib/Support/RISCVISAInfo.cpp

187–197

Why do we need to do any filtering? Just emit the whole thing.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

53–60

This is unrelated

[jrtc27]

llvm/test/CodeGen/RISCV/riscv-isa-features.ll

1 ↗

(On Diff #360723)

Use update_llc_test_checks for these.

2 ↗

(On Diff #360723)

It's not overriding. It's just that #0 doesn't include -f,-d so applying #0 atop the default target-features keeps the default f and d features.

3 ↗

(On Diff #360723)

CHECK and ISA-F-D are not consistent with the check prefixes used in other RISC-V tests.

29 ↗

(On Diff #360723)

Space before }

[jrtc27]

clang/test/CodeGen/RISCV/riscv-metadata-isa-features-empty-target-feature.cpp

9 ↗

(On Diff #360723)

No check that the module flags actually includes this?

9–10 ↗

(On Diff #360723)

If you're not going to change the representation to be a single string, at least use a FileCheck variable so you can assert that this list is the one referenced by the module attribute above.

clang/test/CodeGen/RISCV/riscv-metadata-isa-features.c

15–21 ↗

(On Diff #360723)

These need check lines to ensure that these are actually being used for the right attribute. Especially !{!""}, that could easily be something else that you happen to match.

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

184

Don't delete this

187

This doesn't make sense. The module flag should have been parsed and applied to the subtarget long ago. And an empty feature string means no features, not that they're missing. The fact that you need to change this code here is a sign that code elsewhere is wrong.

[khchen]

clang/lib/CodeGen/CodeGenModule.cpp

835

Because I think maybe the merge behavior AppendUnique is the best way to merge two module with different value of metadata flag, and it requires a metadata node with operands list.
Personally, I did not like to to have a new merge behavior to merge two target-features string, but maybe there is another better merging behavior I never thought,

In addition, some target features are not related to extension information, for example, +relax, +save-restore. Should we really need to record those unnecessary information in module?

What do you think?

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

187

What's excepted elf attribute if llc with -mattr=+f,+d but the riscv-isa-features module flag is +a,+c+m?
I think it will be +f, +d, so we need to make sure -mattr is empty before use the module flag. Does it make sense?

The module flag should have been parsed and applied to the subtarget long ago.

Sorry, I didn't understand it. The module flag riscv-isa-features is not applied to subtarget, I only use it to generate the correct extension .attribute.

Maybe I misunderstood something?

clang/lib/CodeGen/CodeGenModule.cpp

 #include "llvm/IR/Module.h"
 #include "llvm/IR/ProfileSummary.h"
 #include "llvm/ProfileData/InstrProfReader.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ConvertUTF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MD5.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/TimeProfiler.h"
 
 using namespace clang;
 using namespace CodeGen;
 
 static llvm::cl::opt<bool> LimitedCoverage(
     "limited-coverage-experimental", llvm::cl::ZeroOrMore, llvm::cl::Hidden,
     llvm::cl::desc("Emit limited coverage mapping information (experimental)"),
if (   Arch == llvm::Triple::arm
       || Arch == llvm::Triple::armeb
       || Arch == llvm::Triple::thumb
       || Arch == llvm::Triple::thumbeb) {
     // The minimum width of an enum in bytes
     uint64_t EnumWidth = Context.getLangOpts().ShortEnums ? 1 : 4;
     getModule().addModuleFlag(llvm::Module::Error, "min_enum_size", EnumWidth);
   }
 
-  if (Arch == llvm::Triple::riscv32 || Arch == llvm::Triple::riscv64) {
-    StringRef ABIStr = Target.getABI();
-    llvm::LLVMContext &Ctx = TheModule.getContext();
-    getModule().addModuleFlag(llvm::Module::Error, "target-abi",
-                              llvm::MDString::get(Ctx, ABIStr));
-  }
-
   if (CodeGenOpts.SanitizeCfiCrossDso) {
     // Indicate that we want cross-DSO control flow integrity checks.
     getModule().addModuleFlag(llvm::Module::Override, "Cross-DSO CFI", 1);
   }
 
   if (CodeGenOpts.WholeProgramVTables) {
     // Indicate whether VFE was enabled for this module, so that the
     // vcall_visibility metadata added under whole program vtables is handled

 }
 
 void CodeGenModule::EmitBackendOptionsMetadata(
     const CodeGenOptions CodeGenOpts) {
   switch (getTriple().getArch()) {
   default:
     break;
   case llvm::Triple::riscv32:
-  case llvm::Triple::riscv64:
+  case llvm::Triple::riscv64: {
     getModule().addModuleFlag(llvm::Module::Error, "SmallDataLimit",
                               CodeGenOpts.SmallDataLimit);
+    StringRef ABIStr = Target.getABI();
+    llvm::LLVMContext &Ctx = TheModule.getContext();
+    getModule().addModuleFlag(llvm::Module::Error, "target-abi",
+                              llvm::MDString::get(Ctx, ABIStr));
+    std::vector<std::string> Features = getTarget().getTargetOpts().Features;
+    unsigned XLEN = getTriple().getArch() == llvm::Triple::riscv32 ? 32 : 64;
+    llvm::RISCVISAInfo ISAInfo;
+    ISAInfo.parse(XLEN, Features);
+    getModule().addModuleFlag(
+        llvm::Module::OR, "riscv-isa-bits",
+        llvm::ConstantInt::get(llvm::IntegerType::get(Ctx, 256),
+                               ISAInfo.toAPInt()));
     break;
   }
   }
+}
 
 void CodeGenModule::UpdateCompletedType(const TagDecl *TD) {
   // Make sure that this type is translated.
   Types.UpdateCompletedType(TD);
 }
 
 void CodeGenModule::RefreshTypeCacheForClass(const CXXRecordDecl *RD) {
   // Make sure that this type is translated.

clang/lib/CodeGen/CodeGenTypeCache.h

 
 /// This structure provides a set of types that are commonly used
 /// during IR emission.  It's initialized once in CodeGenModule's
 /// constructor and then copied around into new CodeGenFunctions.
 struct CodeGenTypeCache {
   /// void
   llvm::Type *VoidTy;
 
-  /// i8, i16, i32, and i64
+  /// i8, i16, i32 and i64
   llvm::IntegerType *Int8Ty, *Int16Ty, *Int32Ty, *Int64Ty;
   /// half, bfloat, float, double
   llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy;
 
   /// int
   llvm::IntegerType *IntTy;
 
   /// char

clang/test/CodeGen/RISCV/riscv-metadata-isa-bits-empty-target-feature.cpp

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: attributes #0 = {{[{].*}} "target-features"="+64bit,+f" {{.*[}]}}
+// CHECK: attributes #1 = {{[{].*}} "target-features"="+64bit,+f" {{.*[}]}}
+// CHECK: attributes #2 = {{[{].*}} "target-features"="+64bit,+f" {{.*[}]}}
+// CHECK: attributes #3 = {{[{].*}} nounwind {{.*[}]}}
+
+// Encode isa string as riscv-isa-bits due to some empty target-features attribute
+// CHECK: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 8}
+
+struct A {
+  A() {}
+};
+
+void test() noexcept {
+  A a;
+}
+
+int main() {
+  test();
+  return 0;
+}

clang/test/CodeGen/RISCV/riscv-metadata-isa-bits-ifunc.c

+// RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: attributes #0 = {{[{].*}} "target-features"="+64bit" {{.*[}]}}
+// CHECK: attributes #1 = {{[{].*}} "target-features"="+64bit,+m" {{.*[}]}}
+
+// Encode isa string as riscv-isa-bits for i function case.
+// CHECK: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 0}
+
+static int __attribute__((target("m")))
+mul_m(int x, int y) {
+  return x * y;
+}
+
+static int mul_i(int x, int y) {
+  return x * y;
+}
+
+static int (*foo_resolver(unsigned long hwcap))(int, int) {
+  if (hwcap & (1 << ('M' - 'A')))
+    return mul_m;
+  else
+    return mul_i;
+}
+
+int __attribute__((ifunc("foo_resolver")))
+foo(int, int);

clang/test/CodeGen/RISCV/riscv-metadata-isa-bits.c

+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=RV32-ISA %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=RV32D-ISA %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=RV32FD-ISA %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=RV64-ISA %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=RV64D-ISA %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=RV64FD-ISA %s
+
+// Test expected ISA result when giving many -target-feautre
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature -f -o - %s | FileCheck -check-prefix=RV32-ISA %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-feature +experimental-v -target-feature +experimental-zfh -o - %s | FileCheck -check-prefix=RV32FDVZFH-ISA %s
+
+// RV32-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 0}
+// RV32D-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 16}
+// RV32FD-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 24}
+// RV32FDVZFH-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 2097304}
+// RV64-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 0}
+// RV64D-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 16}
+// RV64FD-ISA: !{{[0-9]+}} = !{i32 8, !"riscv-isa-bits", i256 24}

llvm/include/llvm/IR/Module.h

enum ModFlagBehavior {
     /// Appends the two values, which are required to be metadata
     /// nodes. However, duplicate entries in the second list are dropped
     /// during the append operation.
     AppendUnique = 6,
 
     /// Takes the max of the two values, which are required to be integers.
     Max = 7,
 
+    /// OR two values, which are required to be integers.
+    OR = 8,
+
     // Markers:
     ModFlagBehaviorFirstVal = Error,
-    ModFlagBehaviorLastVal = Max
+    ModFlagBehaviorLastVal = OR
   };
 
   /// Checks if Metadata represents a valid ModFlagBehavior, and stores the
   /// converted result in MFB.
   static bool isValidModFlagBehavior(Metadata *MD, ModFlagBehavior &MFB);
 
   /// Check if the given module flag metadata represents a valid module flag,
   /// and store the flag behavior, the key string and the value metadata.

llvm/include/llvm/Support/RISCVISAInfo.h

 //===-- RISCVISAInfo.h - RISCV ISA Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_RISCVISAINFO_H
 #define LLVM_SUPPORT_RISCVISAINFO_H
 
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
 
 #include <map>
 #include <string>
 #include <vector>
 
 namespace llvm {
 struct RISCVExtensionInfo {
   std::string ExtName;
   unsigned MajorVersion;
   unsigned MinorVersion;
 };
 
 class RISCVISAInfo {
+  static constexpr unsigned NUM_ISA_BITS = 256;
+  static constexpr unsigned NUM_ISA_BYTES = NUM_ISA_BITS / 8;
+
 public:
   RISCVISAInfo();
 
   static bool compareExtension(const std::string &LHS, const std::string &RHS);
   // Helper class for OrderedExtensionMap.
   struct ExtensionComparator {
     bool operator()(const std::string &LHS, const std::string &RHS) const {
       return compareExtension(LHS, RHS);
     }
   };
   // OrderedExtensionMap is a StringMap-like container, but specialized to
   // keep entries in canonical order of extension.
   typedef std::map<std::string, RISCVExtensionInfo, ExtensionComparator>
       OrderedExtensionMap;
 
   // Parse RISCV ISA info from arch string.
   Error parse(StringRef Arch, bool EnableExperimentalExtension,
               bool ExperimentalExtensionVersionCheck = true);
 
   // Parse RISCV ISA info from feature vector.
   void parse(unsigned XLen, const std::vector<std::string> &Features);
 
+  // Parse RISCV ISA info from ConstantInt.
+  void parse(unsigned XLen, const ConstantInt &Val);
+
+  // Convert RISCV ISA info to APInt
+  APInt toAPInt();
+
   // Convert RISCV ISA info to a feature vector.
   void toFeatures(const llvm::opt::ArgList &Args,
                   std::vector<StringRef> &Features) const;
 
   const OrderedExtensionMap &getExtensions() const { return Exts; };
 
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };

 private:
   unsigned XLen;
   unsigned FLen;
 
   OrderedExtensionMap Exts;
 
   void addExtension(StringRef ExtName, unsigned MajorVersion = 0,
                     unsigned MinorVersion = 0);
+  void addBaseExtension() { addExtension("i", 2, 0); }
 
   void updateFLen();
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/IR/Verifier.cpp

Verifier::visitModuleFlag(const MDNode *Op,
   // Sanity check the values for behaviors with additional requirements.
   switch (MFB) {
   case Module::Error:
   case Module::Warning:
   case Module::Override:
     // These behavior types accept any value.
     break;
 
-  case Module::Max: {
+  case Module::Max:
+  case Module::OR: {
     Assert(mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(2)),
            "invalid value for 'max' module flag (expected constant integer)",
            Op->getOperand(2));
     break;
   }
 
   case Module::Require: {
     // The value should itself be an MDNode with two operands, a flag ID (an

llvm/lib/Linker/IRMover.cpp

for (unsigned I = 0, E = SrcModFlags->getNumOperands(); I != E; ++I) {
     } else if (SrcBehaviorValue == Module::Override) {
       // Update the destination flag to that of the source.
       overrideDstValue();
       continue;
     }
 
     // Diagnose inconsistent merge behavior types.
     if (SrcBehaviorValue != DstBehaviorValue) {
-      bool MaxAndWarn = (SrcBehaviorValue == Module::Max &&
+      bool IntBehaviorAndWarn = ((SrcBehaviorValue == Module::Max ||
+                                  SrcBehaviorValue == Module::OR) &&
                                  DstBehaviorValue == Module::Warning) ||
-                        (DstBehaviorValue == Module::Max &&
+                                ((DstBehaviorValue == Module::Max ||
+                                  DstBehaviorValue == Module::OR) &&
                                  SrcBehaviorValue == Module::Warning);
-      if (!MaxAndWarn)
+      if (!IntBehaviorAndWarn)
         return stringErr("linking module flags '" + ID->getString() +
                          "': IDs have conflicting behaviors in '" +
                          SrcM->getModuleIdentifier() + "' and '" +
                          DstM.getModuleIdentifier() + "'");
     }
 
     auto replaceDstValue = [&](MDNode *New) {
       Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New};
if (DstBehaviorValue == Module::Max || SrcBehaviorValue == Module::Max) {
           (SrcValue->getZExtValue() > DstValue->getZExtValue() ? SrcOp : DstOp)
               ->getOperand(2)};
       MDNode *Flag = MDNode::get(DstM.getContext(), FlagOps);
       DstModFlags->setOperand(DstIndex, Flag);
       Flags[ID].first = Flag;
       continue;
     }
 
+    // OR the two values if either source or destination request OR behavior.
+    if (DstBehaviorValue == Module::OR || SrcBehaviorValue == Module::OR) {
+      ConstantInt *DstValue =
+          mdconst::extract<ConstantInt>(DstOp->getOperand(2));
+      ConstantInt *SrcValue =
+          mdconst::extract<ConstantInt>(SrcOp->getOperand(2));
+
+      auto initBitVector = [](const ConstantInt &Val) {
+        BitVector BitVec(Val.getBitWidth());
+        std::memcpy((void *)BitVec.getData().data(),
+                    Val.getValue().getRawData(), BitVec.getMemorySize());
+        return BitVec;
+      };
+      auto orConstantValues = [&](const ConstantInt &SrcValue,
+                                  const ConstantInt &DstValue) {
+        uint64_t DstBit = DstValue.getBitWidth();
+        uint64_t SrcBit = SrcValue.getBitWidth();
+        auto ResultType =
+            DstBit < SrcBit ? SrcValue.getType() : DstValue.getType();
+        if (DstBit <= 64 && SrcBit <= 64) {
+          uint64_t Result = SrcValue.getZExtValue() | DstValue.getZExtValue();
+          return llvm::ConstantInt::get(ResultType, Result);
+        }
+        BitVector SrcBitVector = initBitVector(SrcValue);
+        BitVector DstBitVector = initBitVector(DstValue);
+        DstBitVector |= SrcBitVector;
+        return llvm::ConstantInt::get(
+            DstM.getContext(),
+            llvm::APInt(DstBitVector.getBitCapacity(), DstBitVector.getData()));
+      };
+      // The resulting flag should have a OR behavior, and OR two values from
+      // between the source and destination values.
+      Metadata *FlagOps[] = {
+          (DstBehaviorValue != Module::OR ? SrcOp : DstOp)->getOperand(0), ID,
+          ConstantAsMetadata::get(orConstantValues(*SrcValue, *DstValue))};
+      MDNode *Flag = MDNode::get(DstM.getContext(), FlagOps);
+      DstModFlags->setOperand(DstIndex, Flag);
+      Flags[ID].first = Flag;
+      continue;
+    }
+
     // Perform the merge for standard behavior types.
     switch (SrcBehaviorValue) {
     case Module::Require:
     case Module::Override:
       llvm_unreachable("not possible");
     case Module::Error: {
       // Emit an error if the values differ.
       if (SrcOp->getOperand(2) != DstOp->getOperand(2))
         return stringErr("linking module flags '" + ID->getString() +
                          "': IDs have conflicting values in '" +
                          SrcM->getModuleIdentifier() + "' and '" +
                          DstM.getModuleIdentifier() + "'");
       continue;
     }
     case Module::Warning: {
       break;
     }
     case Module::Max: {
       break;
     }
+    case Module::OR: {
+      break;
+    }
     case Module::Append: {
       MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2));
       MDNode *SrcValue = cast<MDNode>(SrcOp->getOperand(2));
       SmallVector<Metadata *, 8> MDs;
       MDs.reserve(DstValue->getNumOperands() + SrcValue->getNumOperands());
       MDs.append(DstValue->op_begin(), DstValue->op_end());
       MDs.append(SrcValue->op_begin(), SrcValue->op_end());
 

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISCV Arch String Parser --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/None.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <array>
struct RISCVSupportedExtensionInfo {
   /// Experimental extension?
   bool Experimental;
 };
 
 } // end anonymous namespace
 
 static const StringRef AllStdExts = "mafdqlcbjtpvn";
 
-static const RISCVSupportedExtensionInfo SupportedExtensionInfos[] = {
+static constexpr RISCVSupportedExtensionInfo SupportedExtensionInfos[] = {
     {"i", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"e", RISCVExtensionVersion{1, 9}, /* Experimental */ false},
     {"m", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"a", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"f", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"d", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"c", RISCVExtensionVersion{2, 0}, /* Experimental */ false},
     {"b", RISCVExtensionVersion{0, 93}, /* Experimental */ true},
static constexpr RISCVSupportedExtensionInfo SupportedExtensionInfos[] = {
     {"zbproposedc", RISCVExtensionVersion{0, 93}, /* Experimental */ true},
 
     {"zvamo", RISCVExtensionVersion{0, 10}, /* Experimental */ true},
     {"zvlsseg", RISCVExtensionVersion{0, 10}, /* Experimental */ true},
 
     {"zfh", RISCVExtensionVersion{0, 1}, /* Experimental */ true},
 };
 
+enum ISAFeautreBit {
+  RV32E = 0,
+  StdExtM = 1,
+  StdExtA = 2,
+  StdExtF = 3,
+  StdExtD = 4,
+  StdExtC = 5,
+  StdExtB = 6,
+  StdExtV = 7,
+  ExtZba = 8,
+  ExtZbb = 9,
+  ExtZbc = 10,
+  ExtZbe = 11,
+  ExtZbf = 12,
+  ExtZbm = 13,
+  ExtZbp = 14,
+  ExtZbr = 15,
+  ExtZbs = 16,
+  ExtZbt = 17,
+  ExtZbproposedc = 18,
+  ExtZvamo = 19,
+  StdExtZvlsseg = 20,
+  ExtZfh = 21,
+};
+
+// Bitmap[ISAFeatureBit] store the corresponding default SupportedExtensonInfo
+// we need maintain this table due to we want to support different version isa
+// in the future.
+static const RISCVSupportedExtensionInfo *const Bitmap[] = {
+    /*Bitmap[RV32E]=*/&SupportedExtensionInfos[1],
+    /*Bitmap[StdExtM]=*/&SupportedExtensionInfos[2],
+    /*Bitmap[StdExtA]=*/&SupportedExtensionInfos[3],
+    /*Bitmap[StdExtF]=*/&SupportedExtensionInfos[4],
+    /*Bitmap[StdExtD]=*/&SupportedExtensionInfos[5],
+    /*Bitmap[StdExtC]=*/&SupportedExtensionInfos[6],
+    /*Bitmap[StdExtB]=*/&SupportedExtensionInfos[7],
+    /*Bitmap[StdExtV]=*/&SupportedExtensionInfos[8],
+    /*Bitmap[ExtZba]=*/&SupportedExtensionInfos[9],
+    /*Bitmap[ExtZbb]=*/&SupportedExtensionInfos[10],
+    /*Bitmap[ExtZbc]=*/&SupportedExtensionInfos[11],
+    /*Bitmap[ExtZbe]=*/&SupportedExtensionInfos[12],
+    /*Bitmap[ExtZbf]=*/&SupportedExtensionInfos[13],
+    /*Bitmap[ExtZbm]=*/&SupportedExtensionInfos[14],
+    /*Bitmap[ExtZbp]=*/&SupportedExtensionInfos[15],
+    /*Bitmap[ExtZbr]=*/&SupportedExtensionInfos[16],
+    /*Bitmap[ExtZbs]=*/&SupportedExtensionInfos[17],
+    /*Bitmap[ExtZbt]=*/&SupportedExtensionInfos[18],
+    /*Bitmap[ExtZbproposedc]=*/&SupportedExtensionInfos[19],
+    /*Bitmap[ExtZvamo]=*/&SupportedExtensionInfos[20],
+    /*Bitmap[StdExtZvlsseg]=*/&SupportedExtensionInfos[21],
+    /*Bitmap[ExtZfh]=*/&SupportedExtensionInfos[22]};
+
+static constexpr int BitmapSize = sizeof(Bitmap) / sizeof(Bitmap[0]);
+
 // Remove 'experimental-' if it's prefix of string,
 // return true if did the strip.
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
 
 RISCVISAInfo::RISCVISAInfo() : XLen(0), FLen(0) {}
 
for (auto const &SupportedExtensionInfo :
     if (!SupportedExtensionInfo.Experimental)
       continue;
 
     return SupportedExtensionInfo.Version;
   }
   return None;
 }
 
 bool RISCVISAInfo::isSupportedExtension(StringRef Ext, bool CheckExperimental) {
   bool IsExperimental = false;
   if (CheckExperimental)
     IsExperimental = stripExperimentalPrefix(Ext);
 
   for (auto const &SupportedExtensionInfo :
        filterSupportedExtensionInfosByName(Ext)) {
     if (CheckExperimental)
       return SupportedExtensionInfo.Experimental == IsExperimental;
     return true;
   }
   return false;
 }
 
 bool RISCVISAInfo::isSupportedExtension(StringRef Ext, unsigned MajorVersion,
                                         unsigned MinorVersion,
                                         bool CheckExperimental) {
   bool IsExperimental = false;
   if (CheckExperimental)
if (Add) {
       }
       if (ExtName == "e")
         HasE = true;
     } else {
       Exts.erase(ExtName.str());
     }
   }
   if (!HasE)
-    addExtension("i", 2, 0);
+    addBaseExtension();
 
   updateFLen();
 }
 
 Error RISCVISAInfo::parse(StringRef Arch, bool EnableExperimentalExtension,
                           bool ExperimentalExtensionVersionCheck) {
   // RISC-V ISA strings must be lowercase.
   if (llvm::any_of(Arch, [](char C) { return isupper(C); })) {
for (auto Ext : AllExts) {
     }
   }
 
   updateFLen();
 
   return Error::success();
 }
 
+void RISCVISAInfo::parse(unsigned XLen, const ConstantInt &Val) {
+  assert(XLen == 32 || XLen == 64);
+  assert(Val.getBitWidth() == NUM_ISA_BITS);
+  this->XLen = XLen;
+  BitVector Bits(NUM_ISA_BITS);
+  std::memcpy((void *)Bits.getData().data(), Val.getValue().getRawData(),
+              NUM_ISA_BYTES);
+  for (int ISAFeatureBit = Bits.find_first(); ISAFeatureBit != -1;) {
+    auto Ext = *Bitmap[ISAFeatureBit];
+    addExtension(Ext.Name, Ext.Version.Major, Ext.Version.Minor);
+    ISAFeatureBit = Bits.find_first_in(ISAFeatureBit + 1, NUM_ISA_BITS);
+  }
+
+  if (!hasExtension("e"))
+    addBaseExtension();
+  updateFLen();
+}
+
+APInt RISCVISAInfo::toAPInt() {
+  BitVector Bits(NUM_ISA_BITS);
+  for (auto &Ext : Exts) {
+    StringRef ExtName = Ext.first;
+    if (ExtName == "i")
+      continue;
+    auto it =
+        std::find_if(Bitmap, Bitmap + BitmapSize,
+                     [ExtName](const RISCVSupportedExtensionInfo *const v) {
+                       return ExtName == v->Name;
+                     });
+    assert(it != std::end(Bitmap));
+    unsigned Bit = std::distance(Bitmap, it);
+    Bits.set(Bit);
+  }
+  return llvm::APInt(NUM_ISA_BITS, Bits.getData());
+}
+
 void RISCVISAInfo::updateFLen() {
   FLen = 0;
   // TODO: Handle q extension.
   if (Exts.count("d"))
     FLen = 64;
   else if (Exts.count("f"))
     FLen = 32;
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

 //===-- RISCVTargetStreamer.h - RISCV Target Streamer ----------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETSTREAMER_H
 #define LLVM_LIB_TARGET_RISCV_RISCVTARGETSTREAMER_H
 
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
 class formatted_raw_ostream;
 
 class RISCVTargetStreamer : public MCTargetStreamer {
 public:
   RISCVTargetStreamer(MCStreamer &S);
public:
   virtual void emitDirectiveOptionNoRelax();
   virtual void emitAttribute(unsigned Attribute, unsigned Value);
   virtual void finishAttributeSection();
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
   virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                                     StringRef StringValue);
 
   void emitTargetAttributes(const MCSubtargetInfo &STI);
+  void emitTargetAttributes(const RISCVISAInfo &ISAInfo);
 };
 
 // This part is for ascii assembly output
 class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
   formatted_raw_ostream &OS;
 
   void finishAttributeSection() override;
   void emitAttribute(unsigned Attribute, unsigned Value) override;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

if (STI.hasFeature(RISCV::FeatureRV32E))
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
   else
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
   llvm::RISCVISAInfo ISAInfo;
   unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
   std::vector<std::string> FeatureVector;
   RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
   ISAInfo.parse(XLen, FeatureVector);
+  emitTargetAttributes(ISAInfo);
+}
 
+void RISCVTargetStreamer::emitTargetAttributes(const RISCVISAInfo &ISAInfo) {
+  if (ISAInfo.hasExtension("e"))
+    emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
+  else
+    emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
   emitTextAttribute(RISCVAttrs::ARCH, ISAInfo.toString());
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
                                                formatted_raw_ostream &OS)
     : RISCVTargetStreamer(S), OS(OS) {}
 

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 STATISTIC(RISCVNumInstrsCompressed,
           "Number of RISC-V Compressed instructions emitted");
bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &NewSTI;
 
   SetupMachineFunction(MF);
   emitFunctionBody();
   return false;
 }
 
 void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
-  if (TM.getTargetTriple().isOSBinFormatELF())
-    emitAttributes();
+  if (TM.getTargetTriple().isOSBinFormatELF()) {
+    RISCVTargetStreamer &RTS =
+        static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
+    const auto *ISABitsVal =
+        dyn_cast_or_null<ValueAsMetadata>(M.getModuleFlag("riscv-isa-bits"));
+    if (ISABitsVal && STI->getFeatureString().empty()) {
+      const ConstantInt *ConstVal = cast<ConstantInt>(ISABitsVal->getValue());
+      unsigned XLEN =
+          TM.getTargetTriple().getArch() == llvm::Triple::riscv32 ? 32 : 64;
+      RISCVISAInfo ISAInfo;
+      ISAInfo.parse(XLEN, *ConstVal);
+      RTS.emitTargetAttributes(ISAInfo);
+    } else {
+      RTS.emitTargetAttributes(*STI);
+    }
+  }
 }
-
 void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
 
   if (TM.getTargetTriple().isOSBinFormatELF())
     RTS.finishAttributeSection();
 }
 

llvm/test/CodeGen/RISCV/riscv-isa-bits.ll

+; RUN: llc -o - < %s | FileCheck %s
+; -mattr option would overwrite target-feature and module flag riscv-isa-bits
+; RUN: llc -o - -mattr=+f,+d < %s | FileCheck %s -check-prefix=ISA-F-D
+; RUN: llc --filetype=obj -o - < %s | llvm-readelf -A - \
+; RUN:   | FileCheck %s -check-prefix=OBJFILE
+
+; CHECK: .attribute      5, "rv64i2p0_m2p0_a2p0_c2p0"
+; ISA-F-D: .attribute      5, "rv64i2p0_f2p0_d2p0"
+
+
+; OBJFILE: TagName: arch
+; OBJFILE: Value: rv64i2p0_m2p0_a2p0_c2p0
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define float @foo0(i32 %a) nounwind #0 {
+; CHECK: call    __floatsisf@plt
+; ISA-F-D: fcvt.s.w        ft0, a0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+define float @foo1(i32 %a) nounwind #1 {
+; CHECK: fcvt.s.w        ft0, a0
+; ISA-F-D: fcvt.s.w        ft0, a0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+attributes #0 = { "target-features"="+64bit,+a,+c,+m"}
+attributes #1 = { "target-features"="+64bit,+a,+c,+d,+f,+m"}
+
+!llvm.module.flags = !{!0}
+
+; +a,+c,+m
+!0 = !{i32 8, !"riscv-isa-bits", i256 38}

llvm/test/Linker/Inputs/module-flags-or-1.ll

+!0 = !{i32 8, !"or two small values", i32 16}
+!1 = !{i32 8, !"or two big values-1", i256 -9223372036854775808}
+!2 = !{i32 8, !"or two big values-2", i256 1157442765409226768}
+!3 = !{i32 8, !"or small and big value", i256 16}
+!4 = !{i32 8, !"foo", i44 16}
+!llvm.module.flags = !{!0, !1, !2, !3, !4}

llvm/test/Linker/module-flags-or-1.ll

+; RUN: llvm-link %s %p/Inputs/module-flags-or-1.ll -S -o - | FileCheck %s
+
+; Test OR functionality of module flags.
+
+!0 = !{i32 8, !"or two small values", i32 8}
+; or 7FFFFFFFFFFFFFFF and 8000000000000000
+!1 = !{i32 8, !"or two big values-1", i256 9223372036854775807}
+; or 1000000110000001 and 1010101010101010
+!2 = !{i32 8, !"or two big values-2", i256 1152921509170249729}
+!3 = !{i32 8, !"or small and big value", i32 8}
+!4 = !{i32 8, !"foo", i66 8}
+!llvm.module.flags = !{!0, !1, !2, !3, !4}
+
+;CHECK: !0 = !{i32 8, !"or two small values", i32 24}
+;CHECK: !1 = !{i32 8, !"or two big values-1", i256 -1}
+;CHECK: !2 = !{i32 8, !"or two big values-2", i256 1157442769704194065}
+;CHECK: !3 = !{i32 8, !"or small and big value", i256 24}
+;CHECK: !4 = !{i32 8, !"foo", i128 24}