[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[craig.topper]

Summary

My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.

Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.

[rogfer01]

The rationale looks reasonable to me.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1183–1184

Typo

[craig.topper]

Fix typo

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1184

Maybe this comment could be corrected/clarified. I see what it's trying to convey but saying we can't go below LMUL=64/SEW makes it sound like we can't have fractional types at all since they'd always be at least 1.

1184–1189

Is VT.getSizeInBits() * EltsPerBlock just VT.getVectorNumElements() * RISCV::RVVBitsPerBlock?

[craig.topper]

Rebase and address review comments

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1184

Oops I think I was thinking in terms of the denominator when I wrote that. So it's really SEW/64.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1176

I do wonder about this. So with min=128, a v2i1 would use a nxv8i1 container type, but v2i8 => nxv1i8? Might that make certain operations more difficult if we don't have legal nxv1i1, nxv2i1, nxv4i1?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1176

nxv1i1, nxv2i1, nxv4i1 are legal types they just won't be selected for mask only operations like vmand, vmor, vmxor, etc. They will be used for setcc results. Masks are messed up because a v2i16 setcc would use nxv1i16(lmul 1/4) and v2i8 setcc would use nxv1i8(lmul 1/8). We use nxv1i1 for the mask type for both. To minimize vsetvli changes vmand/vmor/vmxor/etc operations on the mask should use nxv2i1 if the producer was v2i16 or nxv1i1 if the producer was v2i8.

I think enabling fractional lmul here would make the i8 case correct but everything else would still be wrong. I guess I don't have a good reason not to do it. I'll try it and see what happens.

[craig.topper]

Use fractional lmul for masks too.
Modify the divideCeil slightly to divide MinVLen by RVVBitsPerBlock rather
than multiplying number of elements by RVVBitsPerBlock. Should be the same since
MinVLen is a power 2 that is at least 128. RVVBitsPerBlock is 64.

[craig.topper]

Ping

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

470

Do you know what's going on here? This strikes me as potentially a bug?

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

30

These are redundant but presumably we can optimize them away (with the new VSETVLI insertion pass)?

[craig.topper]

Rebase after fixing scatter VL calculation.

[craig.topper]

Updates for recently added tests

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
assert(((VT.isFixedLengthVector() && TLI.isTypeLegal(VT)) ||
          "Expected legal fixed length vector!");
 
   unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits();
 
   MVT EltVT = VT.getVectorElementType();
   switch (EltVT.SimpleTy) {
   default:
     llvm_unreachable("unexpected element type for RVV container");
-  case MVT::i1: {
-    // Masks are calculated assuming 8-bit elements since that's when we need
-    // the most elements.
-    MinVLen /= 8;
-    unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
-    unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / 8;
-    return MVT::getScalableVectorVT(MVT::i1, LMul * EltsPerBlock);
-  }
+  case MVT::i1:
   case MVT::i8:
   case MVT::i16:
   case MVT::i32:
   case MVT::i64:
   case MVT::f16:
   case MVT::f32:
   case MVT::f64: {
-    unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
-    unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / EltVT.getSizeInBits();
-    return MVT::getScalableVectorVT(EltVT, LMul * EltsPerBlock);
+    // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
+    // narrower types, but we can't have a fractional LMUL with demoninator less
+    // than 64/SEW.
+    unsigned NumElts =
+        divideCeil(VT.getVectorNumElements(), MinVLen / RISCV::RVVBitsPerBlock);
+    return MVT::getScalableVectorVT(EltVT, NumElts);
   }
   }
 }
 
 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT,
                                             const RISCVSubtarget &Subtarget) {
   return getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), VT,
                                           Subtarget);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

; CHECK-NEXT:    ret
   %c = bitcast <4 x i8> %a to <32 x i1>
   %d = xor <32 x i1> %b, %c
   ret <32 x i1> %d
 }
 
 define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
 ; CHECK-LABEL: bitcast_v1i8_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x i8> %a to i8
   ret i8 %b
 }
 
 define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
 ; CHECK-LABEL: bitcast_v2i8_i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <2 x i8> %a to i16
   ret i16 %b
 }
 
 define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
 ; CHECK-LABEL: bitcast_v1i16_i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x i16> %a to i16
   ret i16 %b
 }
 
 define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
 ; CHECK-LABEL: bitcast_v4i8_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <4 x i8> %a to i32
   ret i32 %b
 }
 
 define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
 ; CHECK-LABEL: bitcast_v2i16_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <2 x i16> %a to i32
   ret i32 %b
 }
 
 define i32 @bitcast_v1i32_i32(<1 x i32> %a) {
 ; CHECK-LABEL: bitcast_v1i32_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x i32> %a to i32
   ret i32 %b
 }
 
 define i64 @bitcast_v8i8_i64(<8 x i8> %a) {
 ; RV32-LABEL: bitcast_v8i8_i64:

 ; RV64-NEXT:    ret
   %b = bitcast <1 x i64> %a to i64
   ret i64 %b
 }
 
 define half @bitcast_v2i8_f16(<2 x i8> %a) {
 ; CHECK-LABEL: bitcast_v2i8_f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <2 x i8> %a to half
   ret half %b
 }
 
 define half @bitcast_v1i16_f16(<1 x i16> %a) {
 ; CHECK-LABEL: bitcast_v1i16_f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x i16> %a to half
   ret half %b
 }
 
 define float @bitcast_v4i8_f32(<4 x i8> %a) {
 ; CHECK-LABEL: bitcast_v4i8_f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <4 x i8> %a to float
   ret float %b
 }
 
 define float @bitcast_v2i16_f32(<2 x i16> %a) {
 ; CHECK-LABEL: bitcast_v2i16_f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <2 x i16> %a to float
   ret float %b
 }
 
 define float @bitcast_v1i32_f32(<1 x i32> %a) {
 ; CHECK-LABEL: bitcast_v1i32_f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x i32> %a to float
   ret float %b
 }
 
 define double @bitcast_v8i8_f64(<8 x i8> %a) {
 ; RV32-LABEL: bitcast_v8i8_f64:

 ; RV64-NEXT:    ret
   %b = bitcast <1 x i64> %a to double
   ret double %b
 }
 
 define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
 ; CHECK-LABEL: bitcast_i16_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.x v8, a0
 ; CHECK-NEXT:    ret
   %b = bitcast i16 %a to <1 x i16>
   ret <1 x i16> %b
 }
 
 define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
 ; RV32-LABEL: bitcast_i32_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vmv.s.x v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i32_v2i16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vmv.v.x v8, a0
 ; RV64-NEXT:    ret
   %b = bitcast i32 %a to <2 x i16>
   ret <2 x i16> %b
 }
 
 define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
 ; RV32-LABEL: bitcast_i32_v1i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vmv.s.x v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i32_v1i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vmv.v.x v8, a0
 ; RV64-NEXT:    ret
   %b = bitcast i32 %a to <1 x i32>
   ret <1 x i32> %b
 }
 
 define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v4i16:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

 ; LMULMAX2-RV32-NEXT:    lui a3, 16
 ; LMULMAX2-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX2-RV32-NEXT:    vand.vx v27, v27, a3
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v27, v26
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v27, v25, 24
 ; LMULMAX2-RV32-NEXT:    lui a4, 4080
 ; LMULMAX2-RV32-NEXT:    vand.vx v27, v27, a4
 ; LMULMAX2-RV32-NEXT:    addi a5, zero, 5
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 0
 ; LMULMAX2-RV32-NEXT:    lui a1, 1044480
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v29, v25, 8
 ; LMULMAX2-RV32-NEXT:    vand.vv v28, v29, v28

 ; LMULMAX1-RV32-NEXT:    lui a3, 16
 ; LMULMAX1-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a3
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v27, v26
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v27, v25, 24
 ; LMULMAX1-RV32-NEXT:    lui a4, 4080
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a4
 ; LMULMAX1-RV32-NEXT:    addi a5, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v28, 0
 ; LMULMAX1-RV32-NEXT:    lui a1, 1044480
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v29, v25, 8
 ; LMULMAX1-RV32-NEXT:    vand.vv v28, v29, v28

 ; LMULMAX2-RV32-NEXT:    lui a3, 16
 ; LMULMAX2-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX2-RV32-NEXT:    vand.vx v30, v30, a3
 ; LMULMAX2-RV32-NEXT:    vor.vv v28, v30, v28
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v30, v26, 24
 ; LMULMAX2-RV32-NEXT:    lui a4, 4080
 ; LMULMAX2-RV32-NEXT:    vand.vx v30, v30, a4
 ; LMULMAX2-RV32-NEXT:    addi a5, zero, 85
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v8, 0
 ; LMULMAX2-RV32-NEXT:    lui a1, 1044480
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v8, v8, a1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v10, v26, 8
 ; LMULMAX2-RV32-NEXT:    vand.vv v8, v10, v8

 ; LMULMAX1-RV32-NEXT:    lui a4, 16
 ; LMULMAX1-RV32-NEXT:    addi a4, a4, -256
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a4
 ; LMULMAX1-RV32-NEXT:    vor.vv v27, v27, v26
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v30, 24
 ; LMULMAX1-RV32-NEXT:    lui a6, 4080
 ; LMULMAX1-RV32-NEXT:    vand.vx v28, v26, a6
 ; LMULMAX1-RV32-NEXT:    addi a5, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-RV32-NEXT:    lui a2, 1044480
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v26, v26, a2, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v29, v30, 8
 ; LMULMAX1-RV32-NEXT:    vand.vv v29, v29, v26

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define <4 x i8> @ret_v4i8(<4 x i8>* %p) {
 ; CHECK-LABEL: ret_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %p
   ret <4 x i8> %v
 }
 
 define <4 x i32> @ret_v4i32(<4 x i32>* %p) {
 ; CHECK-LABEL: ret_v4i32:

 ; LMULMAX1-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %p
   ret <16 x i64> %v
 }
 
 define <8 x i1> @ret_mask_v8i1(<8 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %p
   ret <8 x i1> %v
 }
 
 define <32 x i1> @ret_mask_v32i1(<32 x i1>* %p) {
 ; LMULMAX8-LABEL: ret_mask_v32i1:

 ; LMULMAX1-NEXT:    ret
   %v = load <128 x i32>, <128 x i32>* %x
   ret <128 x i32> %v
 }
 
 define <4 x i8> @ret_v8i8_param_v4i8(<4 x i8> %v) {
 ; CHECK-LABEL: ret_v8i8_param_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vadd.vi v8, v8, 2
 ; CHECK-NEXT:    ret
   %r = add <4 x i8> %v, <i8 2, i8 2, i8 2, i8 2>
   ret <4 x i8> %r
 }
 
 define <4 x i8> @ret_v4i8_param_v4i8_v4i8(<4 x i8> %v, <4 x i8> %w) {
 ; CHECK-LABEL: ret_v4i8_param_v4i8_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vadd.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %r = add <4 x i8> %v, %w
   ret <4 x i8> %r
 }
 
 define <4 x i64> @ret_v4i64_param_v4i64_v4i64(<4 x i64> %v, <4 x i64> %w) {
 ; LMULMAX8-LABEL: ret_v4i64_param_v4i64_v4i64:

 ; LMULMAX1-NEXT:    ret
   %r = add <4 x i64> %v, %w
   ret <4 x i64> %r
 }
 
 define <8 x i1> @ret_v8i1_param_v8i1_v8i1(<8 x i1> %v, <8 x i1> %w) {
 ; CHECK-LABEL: ret_v8i1_param_v8i1_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmxor.mm v0, v0, v8
 ; CHECK-NEXT:    ret
   %r = xor <8 x i1> %v, %w
   ret <8 x i1> %r
 }
 
 define <32 x i1> @ret_v32i1_param_v32i1_v32i1(<32 x i1> %v, <32 x i1> %w) {
 ; LMULMAX8-LABEL: ret_v32i1_param_v32i1_v32i1:

 ; LMULMAX8-NEXT:    .cfi_def_cfa_offset 256
 ; LMULMAX8-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
 ; LMULMAX8-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
 ; LMULMAX8-NEXT:    .cfi_offset ra, -8
 ; LMULMAX8-NEXT:    .cfi_offset s0, -16
 ; LMULMAX8-NEXT:    addi s0, sp, 256
 ; LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX8-NEXT:    andi sp, sp, -128
-; LMULMAX8-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX8-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX8-NEXT:    vle32.v v8, (a0)
 ; LMULMAX8-NEXT:    addi a0, zero, 32
 ; LMULMAX8-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
 ; LMULMAX8-NEXT:    vle32.v v16, (a1)
 ; LMULMAX8-NEXT:    mv a0, sp
 ; LMULMAX8-NEXT:    vse32.v v16, (sp)
 ; LMULMAX8-NEXT:    vmv1r.v v9, v8
 ; LMULMAX8-NEXT:    vmv1r.v v10, v8

 ; LMULMAX4-NEXT:    .cfi_def_cfa_offset 256
 ; LMULMAX4-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
 ; LMULMAX4-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
 ; LMULMAX4-NEXT:    .cfi_offset ra, -8
 ; LMULMAX4-NEXT:    .cfi_offset s0, -16
 ; LMULMAX4-NEXT:    addi s0, sp, 256
 ; LMULMAX4-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX4-NEXT:    andi sp, sp, -128
-; LMULMAX4-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v8, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v16, (a1)
 ; LMULMAX4-NEXT:    addi a0, a1, 64
 ; LMULMAX4-NEXT:    vle32.v v20, (a0)
 ; LMULMAX4-NEXT:    addi a0, sp, 64
 ; LMULMAX4-NEXT:    vse32.v v20, (a0)
 ; LMULMAX4-NEXT:    mv a0, sp

 ; LMULMAX2-NEXT:    .cfi_def_cfa_offset 128
 ; LMULMAX2-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; LMULMAX2-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; LMULMAX2-NEXT:    .cfi_offset ra, -8
 ; LMULMAX2-NEXT:    .cfi_offset s0, -16
 ; LMULMAX2-NEXT:    addi s0, sp, 128
 ; LMULMAX2-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX2-NEXT:    andi sp, sp, -128
-; LMULMAX2-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v8, (a0)
 ; LMULMAX2-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v14, (a1)
 ; LMULMAX2-NEXT:    addi a0, a1, 32
 ; LMULMAX2-NEXT:    vle32.v v16, (a0)
 ; LMULMAX2-NEXT:    addi a0, a1, 64
 ; LMULMAX2-NEXT:    vle32.v v18, (a0)
 ; LMULMAX2-NEXT:    addi a0, a1, 96

 ; LMULMAX1-NEXT:    .cfi_def_cfa_offset 128
 ; LMULMAX1-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; LMULMAX1-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; LMULMAX1-NEXT:    .cfi_offset ra, -8
 ; LMULMAX1-NEXT:    .cfi_offset s0, -16
 ; LMULMAX1-NEXT:    addi s0, sp, 128
 ; LMULMAX1-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX1-NEXT:    andi sp, sp, -128
-; LMULMAX1-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v8, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v13, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vle32.v v14, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vle32.v v15, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 48

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
 
 define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) {
 ; CHECK-LABEL: sextload_v2i1_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v8, v25, -1, v0
 ; CHECK-NEXT:    ret
   %y = load <2 x i1>, <2 x i1>* %x
   %z = sext <2 x i1> %y to <2 x i16>
   ret <2 x i16> %z
 }
 
 define <2 x i16> @sextload_v2i8_v2i16(<2 x i8>* %x) {
 ; CHECK-LABEL: sextload_v2i8_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = sext <2 x i8> %y to <2 x i16>
   ret <2 x i16> %z
 }
 
 define <2 x i16> @zextload_v2i8_v2i16(<2 x i8>* %x) {
 ; CHECK-LABEL: zextload_v2i8_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = zext <2 x i8> %y to <2 x i16>
   ret <2 x i16> %z
 }
 
 define <2 x i32> @sextload_v2i8_v2i32(<2 x i8>* %x) {
 ; CHECK-LABEL: sextload_v2i8_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = sext <2 x i8> %y to <2 x i32>
   ret <2 x i32> %z
 }
 
 define <2 x i32> @zextload_v2i8_v2i32(<2 x i8>* %x) {
 ; CHECK-LABEL: zextload_v2i8_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vzext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = zext <2 x i8> %y to <2 x i32>
   ret <2 x i32> %z
 }
 
 define <2 x i64> @sextload_v2i8_v2i64(<2 x i8>* %x) {
 ; CHECK-LABEL: sextload_v2i8_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf8 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = sext <2 x i8> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define <2 x i64> @zextload_v2i8_v2i64(<2 x i8>* %x) {
 ; CHECK-LABEL: zextload_v2i8_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf8 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i8>, <2 x i8>* %x
   %z = zext <2 x i8> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define <4 x i16> @sextload_v4i8_v4i16(<4 x i8>* %x) {
 ; CHECK-LABEL: sextload_v4i8_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = sext <4 x i8> %y to <4 x i16>
   ret <4 x i16> %z
 }
 
 define <4 x i16> @zextload_v4i8_v4i16(<4 x i8>* %x) {
 ; CHECK-LABEL: zextload_v4i8_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = zext <4 x i8> %y to <4 x i16>
   ret <4 x i16> %z
 }
 
 define <4 x i32> @sextload_v4i8_v4i32(<4 x i8>* %x) {
 ; CHECK-LABEL: sextload_v4i8_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = sext <4 x i8> %y to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i32> @zextload_v4i8_v4i32(<4 x i8>* %x) {
 ; CHECK-LABEL: zextload_v4i8_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = zext <4 x i8> %y to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i64> @sextload_v4i8_v4i64(<4 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v4i8_v4i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v4i8_v4i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = sext <4 x i8> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <4 x i64> @zextload_v4i8_v4i64(<4 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v4i8_v4i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v4i8_v4i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = zext <4 x i8> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <8 x i16> @sextload_v8i8_v8i16(<8 x i8>* %x) {
 ; CHECK-LABEL: sextload_v8i8_v8i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = sext <8 x i8> %y to <8 x i16>
   ret <8 x i16> %z
 }
 
 define <8 x i16> @zextload_v8i8_v8i16(<8 x i8>* %x) {
 ; CHECK-LABEL: zextload_v8i8_v8i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = zext <8 x i8> %y to <8 x i16>
   ret <8 x i16> %z
 }
 
 define <8 x i32> @sextload_v8i8_v8i32(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i8_v8i32:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = sext <8 x i8> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i32> @zextload_v8i8_v8i32(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i8_v8i32:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = zext <8 x i8> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i64> @sextload_v8i8_v8i64(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i8_v8i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf8 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i8_v8i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = sext <8 x i8> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <8 x i64> @zextload_v8i8_v8i64(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i8_v8i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf8 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i8_v8i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = zext <8 x i8> %y to <8 x i64>
   ret <8 x i64> %z
 }

 ; LMULMAX1-LABEL: sextload_v16i8_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i8_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = sext <16 x i8> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i32> @zextload_v16i8_v16i32(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i8_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i8_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = zext <16 x i8> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i64> @sextload_v16i8_v16i64(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i8_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v12, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v14, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v15, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v9, v27
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v10, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v28, v26, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf8 v13, v28
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf8 v14, v26
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v11, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v13, v26
+; LMULMAX1-NEXT:    vsext.vf8 v15, v26
 ; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i8_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e8,m1,ta,mu

 ; LMULMAX1-LABEL: zextload_v16i8_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v12, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v14, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v15, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v9, v27
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v10, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v28, v26, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf8 v13, v28
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf8 v14, v26
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v11, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v13, v26
+; LMULMAX1-NEXT:    vzext.vf8 v15, v26
 ; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i8_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf8 v12, v26
 ; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = zext <16 x i8> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) {
 ; CHECK-LABEL: truncstore_v2i8_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vand.vi v25, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i8> %x to <2 x i1>
   store <2 x i1> %y, <2 x i1>* %z
   ret void
 }
 
 define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v2i16_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i16> %x to <2 x i8>
   store <2 x i8> %y, <2 x i8>* %z
   ret void
 }
 
 define <2 x i32> @sextload_v2i16_v2i32(<2 x i16>* %x) {
 ; CHECK-LABEL: sextload_v2i16_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i16>, <2 x i16>* %x
   %z = sext <2 x i16> %y to <2 x i32>
   ret <2 x i32> %z
 }
 
 define <2 x i32> @zextload_v2i16_v2i32(<2 x i16>* %x) {
 ; CHECK-LABEL: zextload_v2i16_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i16>, <2 x i16>* %x
   %z = zext <2 x i16> %y to <2 x i32>
   ret <2 x i32> %z
 }
 
 define <2 x i64> @sextload_v2i16_v2i64(<2 x i16>* %x) {
 ; CHECK-LABEL: sextload_v2i16_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i16>, <2 x i16>* %x
   %z = sext <2 x i16> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define <2 x i64> @zextload_v2i16_v2i64(<2 x i16>* %x) {
 ; CHECK-LABEL: zextload_v2i16_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf4 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i16>, <2 x i16>* %x
   %z = zext <2 x i16> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define void @truncstore_v4i16_v4i8(<4 x i16> %x, <4 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v4i16_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <4 x i16> %x to <4 x i8>
   store <4 x i8> %y, <4 x i8>* %z
   ret void
 }
 
 define <4 x i32> @sextload_v4i16_v4i32(<4 x i16>* %x) {
 ; CHECK-LABEL: sextload_v4i16_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i16>, <4 x i16>* %x
   %z = sext <4 x i16> %y to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i32> @zextload_v4i16_v4i32(<4 x i16>* %x) {
 ; CHECK-LABEL: zextload_v4i16_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <4 x i16>, <4 x i16>* %x
   %z = zext <4 x i16> %y to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i64> @sextload_v4i16_v4i64(<4 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v4i16_v4i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v4i16_v4i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i16>, <4 x i16>* %x
   %z = sext <4 x i16> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <4 x i64> @zextload_v4i16_v4i64(<4 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v4i16_v4i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v4i16_v4i64:
 ; LMULMAX4:       # %bb.0:
-; LMULMAX4-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX4-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i16>, <4 x i16>* %x
   %z = zext <4 x i16> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v8i16_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <8 x i16> %x to <8 x i8>
   store <8 x i8> %y, <8 x i8>* %z
   ret void
 }
 
 define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) {

 ; LMULMAX1-LABEL: sextload_v8i16_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i16_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i16>, <8 x i16>* %x
   %z = sext <8 x i16> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <8 x i64> @zextload_v8i16_v8i64(<8 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i16_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v9, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v11, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v26
 ; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i16_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu

 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v11, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
+; LMULMAX1-NEXT:    vslidedown.vi v28, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v14, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vsext.vf4 v14, v28
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v29, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v15, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsext.vf4 v9, v29
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v11, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v13, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v15, v27
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsext.vf4 v12, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i16_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)

 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v11, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
+; LMULMAX1-NEXT:    vslidedown.vi v28, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v14, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vzext.vf4 v14, v28
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v29, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v15, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT:    vzext.vf4 v9, v29
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v11, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v13, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v15, v27
 ; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vzext.vf4 v12, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i16_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vslidedown.vi v28, v26, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v12, v28
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i16>, <16 x i16>* %x
   %z = zext <16 x i16> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v2i32_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v26, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i32> %x to <2 x i8>
   store <2 x i8> %y, <2 x i8>* %z
   ret void
 }
 
 define void @truncstore_v2i32_v2i16(<2 x i32> %x, <2 x i16>* %z) {
 ; CHECK-LABEL: truncstore_v2i32_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i32> %x to <2 x i16>
   store <2 x i16> %y, <2 x i16>* %z
   ret void
 }
 
 define <2 x i64> @sextload_v2i32_v2i64(<2 x i32>* %x) {
 ; CHECK-LABEL: sextload_v2i32_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i32>, <2 x i32>* %x
   %z = sext <2 x i32> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define <2 x i64> @zextload_v2i32_v2i64(<2 x i32>* %x) {
 ; CHECK-LABEL: zextload_v2i32_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf2 v8, v25
 ; CHECK-NEXT:    ret
   %y = load <2 x i32>, <2 x i32>* %x
   %z = zext <2 x i32> %y to <2 x i64>
   ret <2 x i64> %z
 }
 
 define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v4i32_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v26, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <4 x i32> %x to <4 x i8>
   store <4 x i8> %y, <4 x i8>* %z
   ret void
 }
 
 define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %z) {
 ; CHECK-LABEL: truncstore_v4i32_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <4 x i32> %x to <4 x i16>
   store <4 x i16> %y, <4 x i16>* %z
   ret void
 }
 
 define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) {

 
 define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) {
 ; LMULMAX1-LABEL: truncstore_v8i32_v8i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v27, 4
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vse8.v v26, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <8 x i32> %x to <8 x i8>
   store <8 x i8> %y, <8 x i8>* %z
   ret void
 }
 
 define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) {
; LMULMAX4-NEXT:    ret
   %z = zext <8 x i32> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) {
 ; LMULMAX1-LABEL: truncstore_v16i32_v16i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vmv1r.v v27, v25
 ; LMULMAX1-NEXT:    vslideup.vi v27, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v11, 0
+; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v28, 4
+; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v10, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v11, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v28, 4
-; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v27, 8
+; LMULMAX1-NEXT:    vslideup.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vse8.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0

 ; CHECK-LABEL: truncstore_v2i64_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i64> %x to <2 x i8>
   store <2 x i8> %y, <2 x i8>* %z
   ret void
 }
 
 define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %z) {
 ; CHECK-LABEL: truncstore_v2i64_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v26, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i64> %x to <2 x i16>
   store <2 x i16> %y, <2 x i16>* %z
   ret void
 }
 
 define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %z) {
 ; CHECK-LABEL: truncstore_v2i64_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v8, 0
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
 ; CHECK-NEXT:    vse32.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i64> %x to <2 x i32>
   store <2 x i32> %y, <2 x i32>* %z
   ret void
 }
 
 define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) {
 ; LMULMAX1-LABEL: truncstore_v4i64_v4i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v27, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vse8.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v4i64_v4i8:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v25, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v26, 0
-; LMULMAX4-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vse8.v v25, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <4 x i64> %x to <4 x i8>
   store <4 x i8> %y, <4 x i8>* %z
   ret void
 }
 
 define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) {
 ; LMULMAX1-LABEL: truncstore_v4i64_v4i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v27, 2
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vse16.v v26, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <4 x i64> %x to <4 x i16>
   store <4 x i16> %y, <4 x i16>* %z
   ret void
 }
 
 define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) {
; LMULMAX4-NEXT:    ret
   store <4 x i32> %y, <4 x i32>* %z
   ret void
 }
 
 define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) {
 ; LMULMAX1-LABEL: truncstore_v8i64_v8i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vmv1r.v v27, v26
 ; LMULMAX1-NEXT:    vslideup.vi v27, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v28, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v25, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v10, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v25, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v11, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v25, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v27, 4
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vnsrl.wi v27, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v8i64_v8i8:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vse8.v v26, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <8 x i64> %x to <8 x i8>
   store <8 x i8> %y, <8 x i8>* %z
   ret void
 }
 
 define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) {
 ; LMULMAX1-LABEL: truncstore_v8i64_v8i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vmv1r.v v27, v25
 ; LMULMAX1-NEXT:    vslideup.vi v27, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v11, 0
+; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v28, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v10, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v11, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
+; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v28, 2
-; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v27, 4
+; LMULMAX1-NEXT:    vslideup.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0
; LMULMAX4-NEXT:    ret
   store <8 x i32> %y, <8 x i32>* %z
   ret void
 }
 
 define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) {
 ; LMULMAX1-LABEL: truncstore_v16i64_v16i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v14, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v26, v25
-; LMULMAX1-NEXT:    vslideup.vi v26, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v28, v25
+; LMULMAX1-NEXT:    vslideup.vi v28, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v15, 0
+; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v27, 2
+; LMULMAX1-NEXT:    vnsrl.wi v26, v27, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v26, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v27, v26
+; LMULMAX1-NEXT:    vslideup.vi v27, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v12, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v10, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v28, v25
-; LMULMAX1-NEXT:    vslideup.vi v28, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v29, v25
+; LMULMAX1-NEXT:    vslideup.vi v29, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v13, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v11, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v30, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v28, v27, 2
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v29, v27
-; LMULMAX1-NEXT:    vslideup.vi v29, v28, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v30, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v29, v28, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v27, v29, 4
+; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT:    vslideup.vi v28, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v10, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v12, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v28, v25
-; LMULMAX1-NEXT:    vslideup.vi v28, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v29, v25
+; LMULMAX1-NEXT:    vslideup.vi v29, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v11, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v13, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v30, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v30, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v28, v26, 2
+; LMULMAX1-NEXT:    vnsrl.wi v27, v30, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v29, v27, 2
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v14, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v30, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v15, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v30, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v26, 2
-; LMULMAX1-NEXT:    vslideup.vi v27, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v27, v28, 4
-; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v27, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v29, 8
+; LMULMAX1-NEXT:    vslideup.vi v28, v26, 8
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vse8.v v25, (a0)
+; LMULMAX1-NEXT:    vse8.v v28, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v25, v26, 0
; LMULMAX4-NEXT:    ret
   store <16 x i8> %y, <16 x i8>* %z
   ret void
 }
 
 define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) {
 ; LMULMAX1-LABEL: truncstore_v16i64_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT:    vnsrl.wi v25, v8, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v27, v25
-; LMULMAX1-NEXT:    vslideup.vi v27, v26, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v28, v25
+; LMULMAX1-NEXT:    vslideup.vi v28, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v11, 0
+; LMULMAX1-NEXT:    vnsrl.wi v26, v9, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v27, 2
+; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v27, v28, 2
+; LMULMAX1-NEXT:    vmv1r.v v27, v26
+; LMULMAX1-NEXT:    vslideup.vi v27, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v10, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v26, v25
-; LMULMAX1-NEXT:    vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v28, v25
+; LMULMAX1-NEXT:    vslideup.vi v28, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v9, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v11, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v29, 2
-; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v28, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v29, v28
-; LMULMAX1-NEXT:    vslideup.vi v29, v26, 0
+; LMULMAX1-NEXT:    vnsrl.wi v30, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v30, 2
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v29, v27, 4
+; LMULMAX1-NEXT:    vslideup.vi v27, v28, 4
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v14, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v12, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v26, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vmv1r.v v26, v25
-; LMULMAX1-NEXT:    vslideup.vi v26, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v28, v25
+; LMULMAX1-NEXT:    vslideup.vi v28, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v15, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v13, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v27, 0
+; LMULMAX1-NEXT:    vnsrl.wi v30, v29, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v30, 2
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v26, v30, 2
+; LMULMAX1-NEXT:    vslideup.vi v26, v28, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v12, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v14, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v27, 0
-; LMULMAX1-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v30, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v27, v13, 0
+; LMULMAX1-NEXT:    vnsrl.wi v28, v15, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v30, v27, 0
-; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v30, 2
-; LMULMAX1-NEXT:    vslideup.vi v28, v25, 0
+; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v29, 2
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v28, v26, 4
+; LMULMAX1-NEXT:    vslideup.vi v26, v25, 4
 ; LMULMAX1-NEXT:    addi a1, a0, 16
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vse16.v v28, (a1)
-; LMULMAX1-NEXT:    vse16.v v29, (a0)
+; LMULMAX1-NEXT:    vse16.v v26, (a1)
+; LMULMAX1-NEXT:    vse16.v v27, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v26, v12, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v28, v26, 0

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define i1 @extractelt_v1i1(<1 x i8>* %x, i64 %idx) nounwind {
 ; CHECK-LABEL: extractelt_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vslidedown.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %a = load <1 x i8>, <1 x i8>* %x
   %b = icmp eq <1 x i8> %a, zeroinitializer
   %c = extractelement <1 x i1> %b, i64 %idx
   ret i1 %c
 }
 
 define i1 @extractelt_v2i1(<2 x i8>* %x, i64 %idx) nounwind {
 ; CHECK-LABEL: extractelt_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %a = load <2 x i8>, <2 x i8>* %x
   %b = icmp eq <2 x i8> %a, zeroinitializer
   %c = extractelement <2 x i1> %b, i64 %idx
   ret i1 %c
 }
 
 define i1 @extractelt_v4i1(<4 x i8>* %x, i64 %idx) nounwind {
 ; CHECK-LABEL: extractelt_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, <4 x i8>* %x
   %b = icmp eq <4 x i8> %a, zeroinitializer
   %c = extractelement <4 x i1> %b, i64 %idx
   ret i1 %c
 }
 
 define i1 @extractelt_v8i1(<8 x i8>* %x, i64 %idx) nounwind {
 ; CHECK-LABEL: extractelt_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = icmp eq <8 x i8> %a, zeroinitializer
   %c = extractelement <8 x i1> %b, i64 %idx
   ret i1 %c
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_v4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, <4 x i8>* %x
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v2i8_v4i8_2(<4 x i8>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_v4i8_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v25, 2
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, <4 x i8>* %x
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v2i8_v8i8_0(<8 x i8>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_v8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v2i8_v8i8_6(<8 x i8>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_v8i8_6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v25, 6
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v2i32_v8i32_0(<8 x i32>* %x, <2 x i32>* %y) {
 ; LMULMAX2-LABEL: extract_v2i32_v8i32_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a0)
-; LMULMAX2-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i32_v8i32_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
   store <2 x i32> %c, <2 x i32>* %y
   ret void
 }
 
 define void @extract_v2i32_v8i32_2(<8 x i32>* %x, <2 x i32>* %y) {
 ; LMULMAX2-LABEL: extract_v2i32_v8i32_2:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a0)
 ; LMULMAX2-NEXT:    vsetivli a0, 2, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 2
-; LMULMAX2-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i32_v8i32_2:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
   store <2 x i32> %c, <2 x i32>* %y
   ret void
 }
 
 define void @extract_v2i32_v8i32_6(<8 x i32>* %x, <2 x i32>* %y) {
 ; LMULMAX2-LABEL: extract_v2i32_v8i32_6:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a0)
 ; LMULMAX2-NEXT:    vsetivli a0, 2, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 6
-; LMULMAX2-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i32_v8i32_6:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
   store <2 x i32> %c, <2 x i32>* %y
   ret void
 }
 
 define void @extract_v2i32_nxv16i32_0(<vscale x 16 x i32> %x, <2 x i32>* %y) {
 ; CHECK-LABEL: extract_v2i32_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 0)
   store <2 x i32> %c, <2 x i32>* %y
   ret void
 }
 
 define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, <2 x i32>* %y) {
 ; CHECK-LABEL: extract_v2i32_nxv16i32_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 6
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6)
   store <2 x i32> %c, <2 x i32>* %y
   ret void
 }
 
 define void @extract_v2i8_nxv2i8_0(<vscale x 2 x i8> %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 0)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, <2 x i8>* %y) {
 ; CHECK-LABEL: extract_v2i8_nxv2i8_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2)
   store <2 x i8> %c, <2 x i8>* %y
   ret void
 }
 
 define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, <8 x i32>* %y) {

 }
 
 define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_8:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 1, e8,mf4,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v25, v25, 1
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_48:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a0, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 1, e8,mf4,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v25, v25, 2
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_48:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 6
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv2i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v0, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv2i1_2(<vscale x 2 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv2i1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v25, 2
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
 ; CHECK-NEXT:    vse1.v v26, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v0, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 1
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_48:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 6
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 
 define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v0, (a0)
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v0, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_2:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v0, (a0)
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vmerge.vim v26, v26, 1, v0
 ; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 2
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX2-NEXT:    vmsne.vi v0, v26, 0
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v0, (a0)
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_42:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a0, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v0, (a0)
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vmerge.vim v26, v26, 1, v0
 ; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 10
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX2-NEXT:    vmsne.vi v0, v26, 0
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
-; LMULMAX2-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX2-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 4
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v0, (a0)
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 10
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv2i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv2i1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v25, 2
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    vsetivli a1, 2, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_42:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    addi a1, zero, 42
 ; CHECK-NEXT:    vsetivli a2, 2, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a1
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv32i1_26:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v28, 0
 ; CHECK-NEXT:    vmerge.vim v28, v28, 1, v0
 ; CHECK-NEXT:    vsetivli a1, 2, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v28, 26
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v28, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv32i1_16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 2
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 declare <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP
 
 define i16 @bitcast_v1f16_i16(<1 x half> %a) {
 ; CHECK-LABEL: bitcast_v1f16_i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x half> %a to i16
   ret i16 %b
 }
 
 define half @bitcast_v1f16_f16(<1 x half> %a) {
 ; CHECK-LABEL: bitcast_v1f16_f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fmv.x.h a0, ft0
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x half> %a to half
   ret half %b
 }
 
 define i32 @bitcast_v2f16_i32(<2 x half> %a) {
 ; CHECK-LABEL: bitcast_v2f16_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <2 x half> %a to i32
   ret i32 %b
 }
 
 define i32 @bitcast_v1f32_i32(<1 x float> %a) {
 ; CHECK-LABEL: bitcast_v1f32_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %b = bitcast <1 x float> %a to i32
   ret i32 %b
 }
 
 define float @bitcast_v2f16_f32(<2 x half> %a) {
 ; RV32-FP-LABEL: bitcast_v2f16_f32:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.x.s a0, v8
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_v2f16_f32:
 ; RV64-FP:       # %bb.0:
-; RV64-FP-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.f.s ft0, v8
 ; RV64-FP-NEXT:    fmv.x.w a0, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast <2 x half> %a to float
   ret float %b
 }
 
 define float @bitcast_v1f32_f32(<1 x float> %a) {
 ; RV32-FP-LABEL: bitcast_v1f32_f32:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.x.s a0, v8
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_v1f32_f32:
 ; RV64-FP:       # %bb.0:
-; RV64-FP-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.f.s ft0, v8
 ; RV64-FP-NEXT:    fmv.x.w a0, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast <1 x float> %a to float
   ret float %b
 }
 
 define i64 @bitcast_v4f16_i64(<4 x half> %a) {

 ; RV64-FP-NEXT:    ret
   %b = bitcast <1 x double> %a to double
   ret double %b
 }
 
 define <1 x half> @bitcast_i16_v1f16(i16 %a) {
 ; CHECK-LABEL: bitcast_i16_v1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.x v8, a0
 ; CHECK-NEXT:    ret
   %b = bitcast i16 %a to <1 x half>
   ret <1 x half> %b
 }
 
 define <2 x half> @bitcast_i32_v2f16(i32 %a) {
 ; RV32-FP-LABEL: bitcast_i32_v2f16:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i32_v2f16:
 ; RV64-FP:       # %bb.0:
-; RV64-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vmv.v.x v8, a0
 ; RV64-FP-NEXT:    ret
   %b = bitcast i32 %a to <2 x half>
   ret <2 x half> %b
 }
 
 define <1 x float> @bitcast_i32_v1f32(i32 %a) {
 ; RV32-FP-LABEL: bitcast_i32_v1f32:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i32_v1f32:
 ; RV64-FP:       # %bb.0:
-; RV64-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vmv.v.x v8, a0
 ; RV64-FP-NEXT:    ret
   %b = bitcast i32 %a to <1 x float>
   ret <1 x float> %b
 }
 
 define <4 x half> @bitcast_i64_v4f16(i64 %a) {
 ; RV32-FP-LABEL: bitcast_i64_v4f16:
; RV64-FP-NEXT:    ret
   %b = bitcast i64 %a to <1 x double>
   ret <1 x double> %b
 }
 
 define <1 x i16> @bitcast_f16_v1i16(half %a) {
 ; CHECK-LABEL: bitcast_f16_v1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, a0
-; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.s.f v8, ft0
 ; CHECK-NEXT:    ret
   %b = bitcast half %a to <1 x i16>
   ret <1 x i16> %b
 }
 
 define <1 x half> @bitcast_f16_v1f16(half %a) {
 ; CHECK-LABEL: bitcast_f16_v1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x ft0, a0
-; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.s.f v8, ft0
 ; CHECK-NEXT:    ret
   %b = bitcast half %a to <1 x half>
   ret <1 x half> %b
 }
 
 define <2 x i16> @bitcast_f32_v2i16(float %a) {
 ; RV32-FP-LABEL: bitcast_f32_v2i16:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_f32_v2i16:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    fmv.w.x ft0, a0
-; RV64-FP-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.s.f v8, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast float %a to <2 x i16>
   ret <2 x i16> %b
 }
 
 define <2 x half> @bitcast_f32_v2f16(float %a) {
 ; RV32-FP-LABEL: bitcast_f32_v2f16:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_f32_v2f16:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    fmv.w.x ft0, a0
-; RV64-FP-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.s.f v8, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast float %a to <2 x half>
   ret <2 x half> %b
 }
 
 define <1 x i32> @bitcast_f32_v1i32(float %a) {
 ; RV32-FP-LABEL: bitcast_f32_v1i32:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_f32_v1i32:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    fmv.w.x ft0, a0
-; RV64-FP-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.s.f v8, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast float %a to <1 x i32>
   ret <1 x i32> %b
 }
 
 define <1 x float> @bitcast_f32_v1f32(float %a) {
 ; RV32-FP-LABEL: bitcast_f32_v1f32:
 ; RV32-FP:       # %bb.0:
-; RV32-FP-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-FP-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-FP-NEXT:    vmv.s.x v8, a0
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_f32_v1f32:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    fmv.w.x ft0, a0
-; RV64-FP-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; RV64-FP-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-FP-NEXT:    vfmv.s.f v8, ft0
 ; RV64-FP-NEXT:    ret
   %b = bitcast float %a to <1 x float>
   ret <1 x float> %b
 }
 
 define <4 x i16> @bitcast_f64_v4i16(double %a) {
 ; RV32-FP-LABEL: bitcast_f64_v4i16:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

; CHECK-NEXT:    ret
   store <4 x float> %v3, <4 x float>* %x
   ret void
 }
 
 define void @buildvec_merge0_v4f32(<4 x float>* %x, float %f) {
 ; CHECK-LABEL: buildvec_merge0_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 6
-; CHECK-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    lui a2, %hi(.LCPI4_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI4_0)(a2)
 ; CHECK-NEXT:    vmv.s.x v0, a1
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vfmerge.vfm v25, v25, ft0, v0
 ; CHECK-NEXT:    vse32.v v25, (a0)
 ; CHECK-NEXT:    ret
   %v0 = insertelement <4 x float> undef, float %f, i32 0
   %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
   %v2 = insertelement <4 x float> %v1, float 2.0, i32 2
   %v3 = insertelement <4 x float> %v2, float %f, i32 3
   store <4 x float> %v3, <4 x float>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @fpext_v2f16_v2f32(<2 x half>* %x, <2 x float>* %y) {
 ; CHECK-LABEL: fpext_v2f16_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vse32.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %d = fpext <2 x half> %a to <2 x float>
   store <2 x float> %d, <2 x float>* %y
   ret void
 }
 
 define void @fpext_v2f16_v2f64(<2 x half>* %x, <2 x double>* %y) {
 ; CHECK-LABEL: fpext_v2f16_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v25, v26
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vse64.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %d = fpext <2 x half> %a to <2 x double>

 ; LMULMAX8-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX8-NEXT:    vse64.v v28, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fpext_v8f16_v8f64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfwcvt.f.f.v v26, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v28, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfwcvt.f.f.v v29, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v27
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v29, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v28
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v25
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v29, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v25, v28
-; LMULMAX1-NEXT:    addi a0, a1, 48
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v25, v29
+; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vse64.v v27, (a0)
-; LMULMAX1-NEXT:    addi a0, a1, 32
-; LMULMAX1-NEXT:    vse64.v v29, (a0)
 ; LMULMAX1-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-NEXT:    addi a0, a1, 48
+; LMULMAX1-NEXT:    vse64.v v28, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %d = fpext <8 x half> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }
 
 define void @fpround_v2f32_v2f16(<2 x float>* %x, <2 x half>* %y) {
 ; CHECK-LABEL: fpround_v2f32_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfncvt.f.f.w v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, <2 x float>* %x
   %d = fptrunc <2 x float> %a to <2 x half>
   store <2 x half> %d, <2 x half>* %y
   ret void
 }
 
 define void @fpround_v2f64_v2f16(<2 x double>* %x, <2 x half>* %y) {
 ; CHECK-LABEL: fpround_v2f64_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.rod.f.f.w v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfncvt.f.f.w v25, v26
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %d = fptrunc <2 x double> %a to <2 x half>
   store <2 x half> %d, <2 x half>* %y
   ret void
 }
 

 ; LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a2, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v25, (a2)
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v27, v25
 ; LMULMAX1-NEXT:    addi a0, sp, 8
-; LMULMAX1-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v27, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v25, v26
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v25, (sp)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (sp)
 ; LMULMAX1-NEXT:    vse16.v v25, (a1)
 ; LMULMAX1-NEXT:    addi sp, sp, 16
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %d = fptrunc <8 x float> %a to <8 x half>

 ; LMULMAX1-NEXT:    vle64.v v27, (a2)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle64.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rod.f.f.w v29, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v27, v29
 ; LMULMAX1-NEXT:    addi a0, sp, 12
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v27, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rod.f.f.w v27, v28
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v28, v27
 ; LMULMAX1-NEXT:    addi a0, sp, 4
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rod.f.f.w v27, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v26, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
 ; LMULMAX1-NEXT:    addi a0, sp, 24
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rod.f.f.w v26, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v25, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v25, (sp)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (sp)
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vse16.v v25, (a1)
 ; LMULMAX1-NEXT:    addi sp, sp, 32
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %d = fptrunc <8 x double> %a to <8 x half>
   store <8 x half> %d, <8 x half>* %y
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vv_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vle16.v v26, (a1)
 ; CHECK-NEXT:    vmfeq.vv v27, v25, v26
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = load <8 x half>, <8 x half>* %y
   %c = fcmp oeq <8 x half> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vv_v8f16_nonans(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vv_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vle16.v v26, (a1)
 ; CHECK-NEXT:    vmfeq.vv v27, v25, v26
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = load <8 x half>, <8 x half>* %y
   %c = fcmp nnan oeq <8 x half> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vv_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vle32.v v26, (a1)
 ; CHECK-NEXT:    vmfne.vv v0, v25, v26
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = load <4 x float>, <4 x float>* %y
   %c = fcmp une <4 x float> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vle32.v v26, (a1)
 ; CHECK-NEXT:    vmfne.vv v0, v25, v26
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = load <4 x float>, <4 x float>* %y
   %c = fcmp nnan une <4 x float> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vv_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vle64.v v26, (a1)
 ; CHECK-NEXT:    vmflt.vv v0, v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = load <2 x double>, <2 x double>* %y
   %c = fcmp ogt <2 x double> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vle64.v v26, (a1)
 ; CHECK-NEXT:    vmflt.vv v0, v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = load <2 x double>, <2 x double>* %y
   %c = fcmp nnan ogt <2 x double> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void

 
 define void @fcmp_oge_vv_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v28, v26
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = load <8 x float>, <8 x float>* %y
   %c = fcmp oge <8 x float> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vv_v8f32_nonans(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v28, v26
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = load <8 x float>, <8 x float>* %y
   %c = fcmp nnan oge <8 x float> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vv_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vle64.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v0, v26, v28
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = load <4 x double>, <4 x double>* %y
   %c = fcmp ole <4 x double> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vle64.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v0, v26, v28
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = load <4 x double>, <4 x double>* %y
   %c = fcmp nnan ole <4 x double> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void

 
 define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v8, v28
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = load <8 x double>, <8 x double>* %y
   %c = fcmp ult <8 x double> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vv_v8f64_nonans(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v28, v8
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = load <8 x double>, <8 x double>* %y
   %c = fcmp nnan ult <8 x double> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
; CHECK-NEXT:    ret
   %c = fcmp nnan one <16 x double> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ord_vv_v4f16(<4 x half>* %x, <4 x half>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ord_vv_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmfeq.vv v27, v25, v25
 ; CHECK-NEXT:    vmfeq.vv v25, v26, v26
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmand.mm v0, v25, v27
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = load <4 x half>, <4 x half>* %y
   %c = fcmp ord <4 x half> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uno_vv_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmfne.vv v27, v25, v25
 ; CHECK-NEXT:    vmfne.vv v25, v26, v26
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmor.mm v0, v25, v27
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = load <2 x half>, <2 x half>* %y
   %c = fcmp uno <2 x half> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vf_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vf_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v26, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp oeq <8 x half> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vf_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vf_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v26, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oeq <8 x half> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vf_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp une <4 x float> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan une <4 x float> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vf_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmfgt.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp ogt <2 x double> %a, %c
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmfgt.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp nnan ogt <2 x double> %a, %c
   store <2 x i1> %d, <2 x i1>* %z

 }
 
 define void @fcmp_oge_vf_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vf_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp oge <8 x float> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vf_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oge <8 x float> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vf_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v0, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp ole <4 x double> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v0, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan ole <4 x double> %a, %c
   store <4 x i1> %d, <4 x i1>* %z

 }
 
 define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vf_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v28, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp ult <8 x double> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vf_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v28, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan ult <8 x double> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
; CHECK-NEXT:    ret
   %d = fcmp nnan one <16 x double> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ord_vf_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ord_vf_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vmfeq.vf v27, v26, fa0
 ; CHECK-NEXT:    vmfeq.vv v26, v25, v25
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmand.mm v0, v26, v27
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = insertelement <4 x half> undef, half %y, i32 0
   %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
   %d = fcmp ord <4 x half> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uno_vf_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vmfne.vf v27, v26, fa0
 ; CHECK-NEXT:    vmfne.vv v26, v25, v25
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmor.mm v0, v26, v27
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = insertelement <2 x half> undef, half %y, i32 0
   %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
   %d = fcmp uno <2 x half> %a, %c
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_fv_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_fv_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v26, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp oeq <8 x half> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_fv_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_fv_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v26, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oeq <8 x half> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_fv_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp une <4 x float> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan une <4 x float> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_fv_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmflt.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp ogt <2 x double> %c, %a
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmflt.vf v0, v25, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp nnan ogt <2 x double> %c, %a
   store <2 x i1> %d, <2 x i1>* %z

 }
 
 define void @fcmp_oge_fv_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_fv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp oge <8 x float> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_fv_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oge <8 x float> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_fv_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v0, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp ole <4 x double> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v0, v26, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan ole <4 x double> %c, %a
   store <4 x i1> %d, <4 x i1>* %z

 }
 
 define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_fv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v28, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp ult <8 x double> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_fv_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v28, fa0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan ult <8 x double> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
; CHECK-NEXT:    ret
   %d = fcmp nnan one <16 x double> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ord_fv_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vmfeq.vf v27, v26, fa0
 ; CHECK-NEXT:    vmfeq.vv v26, v25, v25
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmand.mm v0, v27, v26
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = insertelement <4 x half> undef, half %y, i32 0
   %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
   %d = fcmp ord <4 x half> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uno_fv_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vmfne.vf v27, v26, fa0
 ; CHECK-NEXT:    vmfne.vv v26, v25, v25
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmor.mm v0, v27, v26
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = insertelement <2 x half> undef, half %y, i32 0
   %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
   %d = fcmp uno <2 x half> %c, %a
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <4 x half> @shuffle_v4f16(<4 x half> %x, <4 x half> %y) {
 ; CHECK-LABEL: shuffle_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 11
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x half> %x, <4 x half> %y, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
   ret <4 x half> %s
 }
 
 define <8 x float> @shuffle_v8f32(<8 x float> %x, <8 x float> %y) {
 ; CHECK-LABEL: shuffle_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 236
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 12, i32 5, i32 6, i32 7>
   ret <8 x float> %s
 }
 
 define <4 x double> @shuffle_fv_v4f64(<4 x double> %x) {
 ; CHECK-LABEL: shuffle_fv_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 9
 ; CHECK-NEXT:    lui a1, %hi(.LCPI2_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI2_0)(a1)
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmerge.vfm v8, v8, ft0, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
   ret <4 x double> %s
 }
 
 define <4 x double> @shuffle_vf_v4f64(<4 x double> %x) {
 ; CHECK-LABEL: shuffle_vf_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 6
 ; CHECK-NEXT:    lui a1, %hi(.LCPI3_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI3_0)(a1)
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmerge.vfm v8, v8, ft0, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) {
 ; RV32-LABEL: vrgather_permute_shuffle_vu_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a0, %hi(.LCPI4_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v25
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_permute_shuffle_vu_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, %hi(.LCPI4_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI4_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vrgather.vv v26, v8, v28
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> %x, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 1>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_permute_shuffle_uv_v4f64(<4 x double> %x) {
 ; RV32-LABEL: vrgather_permute_shuffle_uv_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v25
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_permute_shuffle_uv_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI5_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vrgather.vv v26, v8, v28
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> undef, <4 x double> %x, <4 x i32> <i32 5, i32 6, i32 4, i32 5>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y) {
 ; RV32-LABEL: vrgather_shuffle_vv_v4f64:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, 1
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
+; RV32-NEXT:    vmv.s.x v25, a0
+; RV32-NEXT:    vmv.v.i v28, 0
+; RV32-NEXT:    vsetivli a0, 4, e16,mf2,tu,mu
+; RV32-NEXT:    vslideup.vi v28, v25, 3
 ; RV32-NEXT:    lui a0, %hi(.LCPI6_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI6_0)
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v25
 ; RV32-NEXT:    addi a0, zero, 8
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
-; RV32-NEXT:    addi a0, zero, 1
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vmv.v.i v28, 0
-; RV32-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
-; RV32-NEXT:    vslideup.vi v28, v25, 3
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v10, v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vv_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.s.x v26, a0
 ; RV64-NEXT:    vmv.v.i v28, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vslideup.vi v28, v26, 3
 ; RV64-NEXT:    lui a0, %hi(.LCPI6_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI6_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v30, (a0)
 ; RV64-NEXT:    vrgather.vv v26, v8, v30
 ; RV64-NEXT:    addi a0, zero, 8
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vrgather.vv v26, v10, v28, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
 ; RV32-LABEL: vrgather_shuffle_xv_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 12
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI7_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; RV32-NEXT:    vlse64.v v26, (a0), zero
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
+; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    lui a0, %hi(.LCPI7_1)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI7_1)
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
-; RV32-NEXT:    vle16.v v25, (a0)
+; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; RV32-NEXT:    vlse64.v v26, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v25, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_xv_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 12
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI7_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI7_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    lui a0, %hi(.LCPI7_1)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI7_1)
 ; RV64-NEXT:    vlse64.v v26, (a0), zero
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vrgather.vv v26, v8, v28, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
 ; RV32-LABEL: vrgather_shuffle_vx_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 3
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a0
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vmv.s.x v25, a0
 ; RV32-NEXT:    vmv.v.i v28, 0
-; RV32-NEXT:    vsetivli a0, 2, e16,m1,tu,mu
+; RV32-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; RV32-NEXT:    vslideup.vi v28, v25, 1
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI8_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI8_0)
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vlse64.v v26, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vx_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 3
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.s.x v26, a0
 ; RV64-NEXT:    vmv.v.i v28, 0
 ; RV64-NEXT:    vsetivli a1, 2, e64,m2,tu,mu
 ; RV64-NEXT:    vslideup.vi v28, v26, 1
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI8_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI8_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vlse64.v v26, (a0), zero
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vrgather.vv v26, v8, v28, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
   ret <4 x double> %s
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

; CHECK-NEXT:    ret
   %d = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %c)
   store <2 x double> %d, <2 x double>* %x
   ret void
 }
 
 define void @copysign_neg_trunc_v4f16_v4f32(<4 x half>* %x, <4 x float>* %y) {
 ; CHECK-LABEL: copysign_neg_trunc_v4f16_v4f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.f.f.w v27, v26
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; CHECK-NEXT:    vfsgnjn.vv v25, v25, v27
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = load <4 x float>, <4 x float>* %y
   %c = fneg <4 x float> %b
   %d = fptrunc <4 x float> %c to <4 x half>
   %e = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %d)
   store <4 x half> %e, <4 x half>* %x
   ret void
 }
 declare <4 x half> @llvm.copysign.v4f16(<4 x half>, <4 x half>)
 
 define void @copysign_neg_ext_v2f64_v2f32(<2 x double>* %x, <2 x float>* %y) {
 ; CHECK-LABEL: copysign_neg_ext_v2f64_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a1)
-; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v27, v26
 ; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vfsgnjn.vv v25, v25, v27
 ; CHECK-NEXT:    vse64.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = load <2 x float>, <2 x float>* %y
   %c = fneg <2 x float> %b

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @fp2si_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
 ; CHECK-LABEL: fp2si_v2f32_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vfcvt.rtz.x.f.v v25, v25
 ; CHECK-NEXT:    vse32.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, <2 x float>* %x
   %d = fptosi <2 x float> %a to <2 x i32>
   store <2 x i32> %d, <2 x i32>* %y
   ret void
 }
 
 define void @fp2ui_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
 ; CHECK-LABEL: fp2ui_v2f32_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vfcvt.rtz.xu.f.v v25, v25
 ; CHECK-NEXT:    vse32.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, <2 x float>* %x
   %d = fptoui <2 x float> %a to <2 x i32>
   store <2 x i32> %d, <2 x i32>* %y
   ret void
; LMULMAX1-NEXT:    ret
   %d = fptoui <8 x float> %a to <8 x i32>
   store <8 x i32> %d, <8 x i32>* %y
   ret void
 }
 
 define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
 ; CHECK-LABEL: fp2si_v2f32_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.rtz.x.f.v v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vse64.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, <2 x float>* %x
   %d = fptosi <2 x float> %a to <2 x i64>
   store <2 x i64> %d, <2 x i64>* %y
   ret void
 }
 
 define void @fp2ui_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
 ; CHECK-LABEL: fp2ui_v2f32_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vse64.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, <2 x float>* %x
   %d = fptoui <2 x float> %a to <2 x i64>
   store <2 x i64> %d, <2 x i64>* %y
   ret void
; LMULMAX1-NEXT:    ret
   %d = fptoui <8 x float> %a to <8 x i64>
   store <8 x i64> %d, <8 x i64>* %y
   ret void
 }
 
 define void @fp2si_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) {
 ; CHECK-LABEL: fp2si_v2f16_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.rtz.x.f.v v25, v26
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vse64.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %d = fptosi <2 x half> %a to <2 x i64>
   store <2 x i64> %d, <2 x i64>* %y
   ret void
 }
 
 define void @fp2ui_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) {
 ; CHECK-LABEL: fp2ui_v2f16_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.f.f.v v26, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v25, v26
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vse64.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %d = fptoui <2 x half> %a to <2 x i64>
   store <2 x i64> %d, <2 x i64>* %y
   ret void
 }
 
 define void @fp2si_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: fp2si_v2f64_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.rtz.x.f.w v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %d = fptosi <2 x double> %a to <2 x i8>
   store <2 x i8> %d, <2 x i8>* %y
   ret void
 }
 
 define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
 ; CHECK-LABEL: fp2ui_v2f64_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.rtz.xu.f.w v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %d = fptoui <2 x double> %a to <2 x i8>
   store <2 x i8> %d, <2 x i8>* %y
   ret void
 }
 
 define void @fp2si_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
 ; LMULMAX8-LABEL: fp2si_v8f64_v8i8:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; LMULMAX8-NEXT:    vle64.v v28, (a0)
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX8-NEXT:    vfncvt.rtz.x.f.w v26, v28
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX8-NEXT:    vse8.v v26, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fp2si_v8f64_v8i8:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a2, a0, 48
 ; LMULMAX1-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vle64.v v25, (a2)
-; LMULMAX1-NEXT:    vle64.v v26, (a0)
 ; LMULMAX1-NEXT:    addi a2, a0, 32
-; LMULMAX1-NEXT:    vle64.v v27, (a2)
-; LMULMAX1-NEXT:    addi a0, a0, 48
+; LMULMAX1-NEXT:    vle64.v v26, (a2)
+; LMULMAX1-NEXT:    vle64.v v27, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle64.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vmv1r.v v30, v27
 ; LMULMAX1-NEXT:    vslideup.vi v30, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v28, v29, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v30, v29, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v28, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v28, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v27, v28, 0
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v28, 0
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v30, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v26
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
+; LMULMAX1-NEXT:    vnsrl.wi v26, v29, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vnsrl.wi v29, v26, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v27, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v26, v25
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v26, 2
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v30, 4
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vse8.v v25, (a1)
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v27, 4
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vse8.v v28, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %d = fptosi <8 x double> %a to <8 x i8>
   store <8 x i8> %d, <8 x i8>* %y
   ret void
 }
 
 define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
 ; LMULMAX8-LABEL: fp2ui_v8f64_v8i8:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
 ; LMULMAX8-NEXT:    vle64.v v28, (a0)
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX8-NEXT:    vfncvt.rtz.xu.f.w v26, v28
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX8-NEXT:    vse8.v v26, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fp2ui_v8f64_v8i8:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    addi a2, a0, 48
 ; LMULMAX1-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vle64.v v25, (a2)
-; LMULMAX1-NEXT:    vle64.v v26, (a0)
 ; LMULMAX1-NEXT:    addi a2, a0, 32
-; LMULMAX1-NEXT:    vle64.v v27, (a2)
-; LMULMAX1-NEXT:    addi a0, a0, 48
+; LMULMAX1-NEXT:    vle64.v v26, (a2)
+; LMULMAX1-NEXT:    vle64.v v27, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle64.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v29, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v29, v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vmv1r.v v30, v27
 ; LMULMAX1-NEXT:    vslideup.vi v30, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v28, v29, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v29, v28, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v30, v29, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v28, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v26, v28, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
-; LMULMAX1-NEXT:    vnsrl.wi v28, v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v27, v28, 0
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v28, 0
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v30, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v26
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
+; LMULMAX1-NEXT:    vnsrl.wi v26, v29, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vnsrl.wi v29, v26, 0
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v27, v29, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v26, v25
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v26, 0
-; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v26, 2
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT:    vslideup.vi v25, v30, 4
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vse8.v v25, (a1)
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v27, 4
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vse8.v v28, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %d = fptoui <8 x double> %a to <8 x i8>
   store <8 x i8> %d, <8 x i8>* %y
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @si2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
 ; CHECK-LABEL: si2fp_v2i32_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vfcvt.f.x.v v25, v25
 ; CHECK-NEXT:    vse32.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i32>, <2 x i32>* %x
   %d = sitofp <2 x i32> %a to <2 x float>
   store <2 x float> %d, <2 x float>* %y
   ret void
 }
 
 define void @ui2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
 ; CHECK-LABEL: ui2fp_v2i32_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vfcvt.f.xu.v v25, v25
 ; CHECK-NEXT:    vse32.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i32>, <2 x i32>* %x
   %d = uitofp <2 x i32> %a to <2 x float>
   store <2 x float> %d, <2 x float>* %y
   ret void
; LMULMAX1-NEXT:    ret
   %d = uitofp <8 x i32> %a to <8 x float>
   store <8 x float> %d, <8 x float>* %y
   ret void
 }
 
 define void @si2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) {
 ; CHECK-LABEL: si2fp_v2i16_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf4 v26, v25
 ; CHECK-NEXT:    vfcvt.f.x.v v25, v26
 ; CHECK-NEXT:    vse64.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i16>, <2 x i16>* %x
   %d = sitofp <2 x i16> %a to <2 x double>
   store <2 x double> %d, <2 x double>* %y
   ret void
 }
 
 define void @ui2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) {
 ; CHECK-LABEL: ui2fp_v2i16_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf4 v26, v25
 ; CHECK-NEXT:    vfcvt.f.xu.v v25, v26
 ; CHECK-NEXT:    vse64.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i16>, <2 x i16>* %x
   %d = uitofp <2 x i16> %a to <2 x double>

 ; LMULMAX8-NEXT:    vfcvt.f.x.v v28, v28
 ; LMULMAX8-NEXT:    vse64.v v28, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: si2fp_v8i16_v8f64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v27, v26
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v26, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v28, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v28, v27
-; LMULMAX1-NEXT:    vfcvt.f.x.v v28, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v29, v28
+; LMULMAX1-NEXT:    vfcvt.f.x.v v28, v29
 ; LMULMAX1-NEXT:    vsext.vf4 v29, v27
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v27, v29
 ; LMULMAX1-NEXT:    vsext.vf4 v29, v25
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v25, v29
-; LMULMAX1-NEXT:    addi a0, a1, 48
-; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
-; LMULMAX1-NEXT:    vse64.v v28, (a0)
+; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-NEXT:    addi a0, a1, 48
+; LMULMAX1-NEXT:    vse64.v v28, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x
   %d = sitofp <8 x i16> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }
 
 define void @ui2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) {
 ; LMULMAX8-LABEL: ui2fp_v8i16_v8f64:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX8-NEXT:    vle16.v v25, (a0)
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX8-NEXT:    vzext.vf4 v28, v25
 ; LMULMAX8-NEXT:    vfcvt.f.xu.v v28, v28
 ; LMULMAX8-NEXT:    vse64.v v28, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: ui2fp_v8i16_v8f64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v27, v26
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v26, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v28, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v28, v27
-; LMULMAX1-NEXT:    vfcvt.f.xu.v v28, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v29, v28
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v28, v29
 ; LMULMAX1-NEXT:    vzext.vf4 v29, v27
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v27, v29
 ; LMULMAX1-NEXT:    vzext.vf4 v29, v25
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v25, v29
-; LMULMAX1-NEXT:    addi a0, a1, 48
-; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
-; LMULMAX1-NEXT:    vse64.v v28, (a0)
+; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-NEXT:    addi a0, a1, 48
+; LMULMAX1-NEXT:    vse64.v v28, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x
   %d = uitofp <8 x i16> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }
 
 define void @si2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) {
 ; CHECK-LABEL: si2fp_v2i64_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.f.x.w v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfncvt.f.f.w v25, v26
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %d = sitofp <2 x i64> %a to <2 x half>
   store <2 x half> %d, <2 x half>* %y
   ret void
 }
 
 define void @ui2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) {
 ; CHECK-LABEL: ui2fp_v2i64_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfncvt.f.xu.w v26, v25
-; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfncvt.f.f.w v25, v26
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %d = uitofp <2 x i64> %a to <2 x half>
   store <2 x half> %d, <2 x half>* %y
   ret void
 }
 

 ; LMULMAX1-NEXT:    addi a2, a0, 32
 ; LMULMAX1-NEXT:    vle64.v v26, (a2)
 ; LMULMAX1-NEXT:    addi a2, a0, 48
 ; LMULMAX1-NEXT:    vle64.v v27, (a2)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle64.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.x.w v29, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v27, v29
 ; LMULMAX1-NEXT:    addi a0, sp, 12
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v27, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.x.w v27, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v28, v27
 ; LMULMAX1-NEXT:    addi a0, sp, 4
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.x.w v27, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v26, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
 ; LMULMAX1-NEXT:    addi a0, sp, 24
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.x.w v26, v25
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v25, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v25, (sp)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (sp)
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vse16.v v25, (a1)
 ; LMULMAX1-NEXT:    addi sp, sp, 32

 ; LMULMAX1-NEXT:    addi a2, a0, 32
 ; LMULMAX1-NEXT:    vle64.v v26, (a2)
 ; LMULMAX1-NEXT:    addi a2, a0, 48
 ; LMULMAX1-NEXT:    vle64.v v27, (a2)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle64.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.xu.w v29, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v27, v29
 ; LMULMAX1-NEXT:    addi a0, sp, 12
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v27, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.xu.w v27, v28
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v28, v27
 ; LMULMAX1-NEXT:    addi a0, sp, 4
-; LMULMAX1-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v28, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.xu.w v27, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v26, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 8
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
 ; LMULMAX1-NEXT:    addi a0, sp, 24
 ; LMULMAX1-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.xu.w v26, v25
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfncvt.f.f.w v25, v26
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v25, (sp)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (sp)
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a0, sp, 16
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vse16.v v25, (a1)
 ; LMULMAX1-NEXT:    addi sp, sp, 32
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i64>, <8 x i64>* %x
   %d = uitofp <8 x i64> %a to <8 x half>
   store <8 x half> %d, <8 x half>* %y
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e32,m4,tu,mu
 ; CHECK-NEXT:    vslideup.vi v8, v28, 0
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m4,tu,mu
 ; CHECK-NEXT:    vslideup.vi v8, v28, 2
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m4,tu,mu
 ; CHECK-NEXT:    vslideup.vi v8, v28, 6
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)
   ret <vscale x 8 x i32> %v
 }
; LMULMAX1-NEXT:    ret
   %sv = load <8 x i32>, <8 x i32>* %svp
   %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(<2 x i32>* %svp) {
 ; CHECK-LABEL: insert_nxv8i32_undef_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> undef, <2 x i32> %sv, i64 0)
   ret <vscale x 8 x i32> %v
 }
 
 define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_v4i32_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetivli a1, 2, e32,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vse32.v v26, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %vec = load <4 x i32>, <4 x i32>* %vp
   %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)
   store <4 x i32> %v, <4 x i32>* %vp
   ret void
 }
 
 define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_v4i32_v2i32_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 2
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vse32.v v26, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %vec = load <4 x i32>, <4 x i32>* %vp
   %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2)
   store <4 x i32> %v, <4 x i32>* %vp
   ret void
 }
 
 define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_v4i32_undef_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a1, 2, e32,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vse32.v v26, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
   store <4 x i32> %v, <4 x i32>* %vp
   ret void
 }
 
 define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) {
 ; LMULMAX2-LABEL: insert_v8i32_v2i32_0:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v28, (a0)
 ; LMULMAX2-NEXT:    vsetivli a1, 2, e32,m2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v28, v26, 0
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v28, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v8i32_v2i32_0:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e32,m1,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %vec = load <8 x i32>, <8 x i32>* %vp
   %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)
   store <8 x i32> %v, <8 x i32>* %vp
   ret void
 }
 
 define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) {
 ; LMULMAX2-LABEL: insert_v8i32_v2i32_2:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v28, (a0)
 ; LMULMAX2-NEXT:    vsetivli a1, 4, e32,m2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v28, v26, 2
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v28, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v8i32_v2i32_2:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %vec = load <8 x i32>, <8 x i32>* %vp
   %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2)
   store <8 x i32> %v, <8 x i32>* %vp
   ret void
 }
 
 define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
 ; LMULMAX2-LABEL: insert_v8i32_v2i32_6:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v28, (a0)
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v28, v26, 6
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vse32.v v28, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v8i32_v2i32_6:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %vec = load <8 x i32>, <8 x i32>* %vp
   %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6)
   store <8 x i32> %v, <8 x i32>* %vp
   ret void
 }
 
 define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
 ; LMULMAX2-LABEL: insert_v8i32_undef_v2i32_6:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vslideup.vi v28, v26, 6
 ; LMULMAX2-NEXT:    vse32.v v28, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 2
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %sv = load <2 x i32>, <2 x i32>* %svp
   %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6)
   store <8 x i32> %v, <8 x i32>* %vp
   ret void
 }
 
 define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) {
 ; CHECK-LABEL: insert_v4i16_v2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a1)
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 0
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %vp
   %sv = load <2 x i16>, <2 x i16>* %svp
   %c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0)
   store <4 x i16> %c, <4 x i16>* %vp
   ret void
 }
 
 define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) {
 ; CHECK-LABEL: insert_v4i16_v2i16_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
-; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a1)
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 2
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %vp
   %sv = load <2 x i16>, <2 x i16>* %svp
   %c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2)
   store <4 x i16> %c, <4 x i16>* %vp
   ret void
 }
 
 define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
 ; LMULMAX2-LABEL: insert_v32i1_v8i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a3, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v26, (a1)
-; LMULMAX2-NEXT:    vsetivli a1, 1, e8,m1,tu,mu
+; LMULMAX2-NEXT:    vsetivli a1, 1, e8,mf4,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX2-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vse1.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v32i1_v8i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v26, (a1)
-; LMULMAX1-NEXT:    vsetivli a1, 1, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 1, e8,mf8,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %vp
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)
   store <32 x i1> %c, <32 x i1>* %vp
   ret void
 }
 
 define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
 ; LMULMAX2-LABEL: insert_v32i1_v8i1_16:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a3, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle1.v v26, (a1)
-; LMULMAX2-NEXT:    vsetivli a1, 3, e8,m1,tu,mu
+; LMULMAX2-NEXT:    vsetivli a1, 3, e8,mf4,tu,mu
 ; LMULMAX2-NEXT:    vslideup.vi v25, v26, 2
 ; LMULMAX2-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vse1.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v32i1_v8i1_16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 2
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle1.v v26, (a1)
-; LMULMAX1-NEXT:    vsetivli a1, 1, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a1, 1, e8,mf8,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %vp
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
   store <32 x i1> %c, <32 x i1>* %vp
   ret void
 }
 
 define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_v8i1_v4i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
-; CHECK-NEXT:    vle1.v v27, (a0)
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
+; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
+; CHECK-NEXT:    vle1.v v27, (a1)
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
-; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
-; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v25, v26, 0
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsne.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %vp
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0)
   store <8 x i1> %c, <8 x i1>* %vp
   ret void
 }
 
 define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_v8i1_v4i1_4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
-; CHECK-NEXT:    vle1.v v27, (a0)
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
+; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
+; CHECK-NEXT:    vle1.v v27, (a1)
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,tu,mu
-; CHECK-NEXT:    vslideup.vi v26, v25, 4
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
-; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v25, v26, 4
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsne.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %vp
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)
   store <8 x i1> %c, <8 x i1>* %vp
   ret void
 }
 
 define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
 ; CHECK-LABEL: insert_nxv2i16_v2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v8, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <2 x i16>, <2 x i16>* %svp
   %c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)
   ret <vscale x 2 x i16> %c
 }
 
 define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
 ; CHECK-LABEL: insert_nxv2i16_v2i16_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 6, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v8, v25, 4
 ; CHECK-NEXT:    ret
   %sv = load <2 x i16>, <2 x i16>* %svp
   %c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)
   ret <vscale x 2 x i16> %c
 }
 
 define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv2i1_v4i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle1.v v27, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,tu,mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
   ret <vscale x 2 x i1> %c
 }
 
 define <vscale x 2 x i1> @insert_nxv2i1_v4i1_6(<vscale x 2 x i1> %v, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv2i1_v4i1_6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle1.v v27, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
 ; CHECK-NEXT:    vsetivli a0, 10, e8,mf4,tu,mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 6
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 6)
   ret <vscale x 2 x i1> %c
 }
 
 define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv8i1_v4i1_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf8,tu,mu
 ; CHECK-NEXT:    vslideup.vi v0, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)
   ret <vscale x 8 x i1> %c
 }
 
 define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv8i1_v8i1_16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 3, e8,mf8,tu,mu
 ; CHECK-NEXT:    vslideup.vi v0, v25, 2
 ; CHECK-NEXT:    ret
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)
   ret <vscale x 8 x i1> %c
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 ; CHECK-NEXT:    ret
   store <2 x i8> <i8 undef, i8 undef>, <2 x i8>* %x
   ret void
 }
 
 define void @buildvec_dominant1_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: buildvec_dominant1_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <2 x i8> <i8 undef, i8 -1>, <2 x i8>* %x
   ret void
 }
 
 define void @buildvec_dominant2_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: buildvec_dominant2_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vmv.s.x v25, zero
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x
   ret void
 }
 
; RV64-NEXT:    ret
   store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
   ret void
 }
 
 define void @buildvec_seq_v8i8_v4i16(<8 x i8>* %x) {
 ; CHECK-LABEL: buildvec_seq_v8i8_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 513
-; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <8 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 undef, i8 2>, <8 x i8>* %x
   ret void
 }
 
 define void @buildvec_seq_v8i8_v2i32(<8 x i8>* %x) {
 ; RV32-LABEL: buildvec_seq_v8i8_v2i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a1, 48
 ; RV32-NEXT:    addi a1, a1, 513
-; RV32-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a1
-; RV32-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; RV32-NEXT:    vse8.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: buildvec_seq_v8i8_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a1, 48
 ; RV64-NEXT:    addiw a1, a1, 513
-; RV64-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a1
-; RV64-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; RV64-NEXT:    vse8.v v25, (a0)
 ; RV64-NEXT:    ret
   store <8 x i8> <i8 1, i8 2, i8 3, i8 undef, i8 1, i8 2, i8 3, i8 undef>, <8 x i8>* %x
   ret void
 }
 
 define void @buildvec_seq_v16i8_v2i64(<16 x i8>* %x) {
 ; RV32-LABEL: buildvec_seq_v16i8_v2i64:

 }
 
 define void @buildvec_seq_v9i8(<9 x i8>* %x) {
 ; RV32-LABEL: buildvec_seq_v9i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 3
 ; RV32-NEXT:    sb a1, 8(a0)
 ; RV32-NEXT:    addi a1, zero, 73
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
-; RV32-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 2
 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    addi a1, zero, 36
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
-; RV32-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; RV32-NEXT:    vmerge.vim v25, v25, 3, v0
 ; RV32-NEXT:    vse8.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: buildvec_seq_v9i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 3
 ; RV64-NEXT:    sb a1, 8(a0)
 ; RV64-NEXT:    lui a1, 4104
 ; RV64-NEXT:    addiw a1, a1, 385
 ; RV64-NEXT:    slli a1, a1, 17
 ; RV64-NEXT:    addi a1, a1, 259
 ; RV64-NEXT:    slli a1, a1, 16
 ; RV64-NEXT:    addi a1, a1, 513
 ; RV64-NEXT:    sd a1, 0(a0)
 ; RV64-NEXT:    ret
   store <9 x i8> <i8 1, i8 2, i8 3, i8 1, i8 2, i8 3, i8 1, i8 2, i8 3>, <9 x i8>* %x
   ret void
 }
 
 define void @buildvec_seq_v4i16_v2i32(<4 x i16>* %x) {
 ; CHECK-LABEL: buildvec_seq_v4i16_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, -127
-; CHECK-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vse16.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <4 x i16> <i16 -127, i16 -1, i16 -127, i16 -1>, <4 x i16>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @sext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) {
 ; CHECK-LABEL: sext_v4i8_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vsext.vf4 v26, v25
 ; CHECK-NEXT:    vse32.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, <4 x i8>* %x
   %b = sext <4 x i8> %a to <4 x i32>
   store <4 x i32> %b, <4 x i32>* %z
   ret void
 }
 
 define void @zext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) {
 ; CHECK-LABEL: zext_v4i8_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vzext.vf4 v26, v25
 ; CHECK-NEXT:    vse32.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, <4 x i8>* %x
   %b = zext <4 x i8> %a to <4 x i32>
   store <4 x i32> %b, <4 x i32>* %z
   ret void
 }
 
 define void @sext_v8i8_v8i32(<8 x i8>* %x, <8 x i32>* %z) {
 ; LMULMAX8-LABEL: sext_v8i8_v8i32:
 ; LMULMAX8:       # %bb.0:
-; LMULMAX8-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; LMULMAX8-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; LMULMAX8-NEXT:    vle8.v v25, (a0)
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX8-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX8-NEXT:    vse32.v v26, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: sext_v8i8_v8i32:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vle8.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX2-NEXT:    vse32.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: sext_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v27, v26
 ; LMULMAX1-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse32.v v27, (a0)
 ; LMULMAX1-NEXT:    vse32.v v26, (a1)
 ; LMULMAX1-NEXT:    ret

 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: sext_v32i8_v32i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a2, a0, 16
 ; LMULMAX1-NEXT:    vle8.v v25, (a2)
 ; LMULMAX1-NEXT:    vle8.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v28, v27
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v29, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 8
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v29, v27, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v30, v27
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
+; LMULMAX1-NEXT:    vsext.vf4 v30, v29
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v29, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v31, v27
+; LMULMAX1-NEXT:    vsext.vf4 v31, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 8
+; LMULMAX1-NEXT:    vslidedown.vi v29, v26, 8
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v8, v29, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v9, v8
 ; LMULMAX1-NEXT:    vsext.vf4 v8, v27
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v27
-; LMULMAX1-NEXT:    vsext.vf4 v27, v25
+; LMULMAX1-NEXT:    vsext.vf4 v27, v29
+; LMULMAX1-NEXT:    vsext.vf4 v29, v25
 ; LMULMAX1-NEXT:    vsext.vf4 v25, v26
-; LMULMAX1-NEXT:    addi a0, a1, 48
-; LMULMAX1-NEXT:    vse32.v v9, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
-; LMULMAX1-NEXT:    vse32.v v8, (a0)
+; LMULMAX1-NEXT:    vse32.v v27, (a0)
 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
-; LMULMAX1-NEXT:    addi a0, a1, 112
-; LMULMAX1-NEXT:    vse32.v v31, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 96
-; LMULMAX1-NEXT:    vse32.v v30, (a0)
+; LMULMAX1-NEXT:    vse32.v v8, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 64
-; LMULMAX1-NEXT:    vse32.v v27, (a0)
-; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse32.v v29, (a0)
+; LMULMAX1-NEXT:    addi a0, a1, 48
+; LMULMAX1-NEXT:    vse32.v v9, (a0)
+; LMULMAX1-NEXT:    addi a0, a1, 16
+; LMULMAX1-NEXT:    vse32.v v31, (a0)
+; LMULMAX1-NEXT:    addi a0, a1, 112
+; LMULMAX1-NEXT:    vse32.v v30, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 80
 ; LMULMAX1-NEXT:    vse32.v v28, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = sext <32 x i8> %a to <32 x i32>
   store <32 x i32> %b, <32 x i32>* %z
   ret void
 }
 
 define void @trunc_v4i8_v4i32(<4 x i32>* %x, <4 x i8>* %z) {
 ; CHECK-LABEL: trunc_v4i8_v4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vnsrl.wi v25, v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i32>, <4 x i32>* %x
   %b = trunc <4 x i32> %a to <4 x i8>
   store <4 x i8> %b, <4 x i8>* %z
   ret void
 }
 
 define void @trunc_v8i8_v8i32(<8 x i32>* %x, <8 x i8>* %z) {
 ; LMULMAX8-LABEL: trunc_v8i8_v8i32:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX8-NEXT:    vle32.v v26, (a0)
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX8-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX8-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX8-NEXT:    vse8.v v26, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: trunc_v8i8_v8i32:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a0)
 ; LMULMAX2-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; LMULMAX2-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX2-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX2-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX2-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX2-NEXT:    vse8.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: trunc_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v27, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v25, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; LMULMAX1-NEXT:    vnsrl.wi v26, v25, 0
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,tu,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,tu,mu
 ; LMULMAX1-NEXT:    vslideup.vi v27, v26, 4
-; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; LMULMAX1-NEXT:    vse8.v v27, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %b = trunc <8 x i32> %a to <8 x i8>
   store <8 x i8> %b, <8 x i8>* %z
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

; CHECK-NEXT:    ret
   %c = icmp slt <128 x i8> %a, %b
   store <128 x i1> %c, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vv_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vle8.v v26, (a1)
 ; CHECK-NEXT:    vmsle.vv v27, v26, v25
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = load <8 x i8>, <8 x i8>* %y
   %c = icmp sge <8 x i8> %a, %b
; CHECK-NEXT:    ret
   %c = icmp uge <128 x i8> %a, %b
   store <128 x i1> %c, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vv_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vle8.v v26, (a1)
 ; CHECK-NEXT:    vmsleu.vv v27, v25, v26
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = load <8 x i8>, <8 x i8>* %y
   %c = icmp ule <8 x i8> %a, %b
; CHECK-NEXT:    ret
   %d = icmp slt <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vx_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vmsle.vv v27, v26, v25
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
; CHECK-NEXT:    ret
   %d = icmp uge <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vx_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsleu.vx v26, v25, a1
 ; CHECK-NEXT:    vse1.v v26, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp ule <8 x i8> %a, %c
; CHECK-NEXT:    ret
   %d = icmp slt <128 x i8> %c, %a
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_xv_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsle.vx v26, v25, a1
 ; CHECK-NEXT:    vse1.v v26, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp sge <8 x i8> %c, %a
; CHECK-NEXT:    ret
   %d = icmp uge <128 x i8> %c, %a
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_xv_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vmsleu.vv v27, v26, v25
 ; CHECK-NEXT:    vse1.v v27, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
; CHECK-NEXT:    ret
   %d = icmp slt <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vi_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsgt.vi v26, v25, -1
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 0, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp sge <8 x i8> %a, %c
; CHECK-NEXT:    ret
   %d = icmp uge <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vi_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsleu.vi v26, v25, 5
 ; CHECK-NEXT:    vse1.v v26, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 5, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp ule <8 x i8> %a, %c

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <4 x i16> @shuffle_v4i16(<4 x i16> %x, <4 x i16> %y) {
 ; CHECK-LABEL: shuffle_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 11
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
   ret <4 x i16> %s
 }
 
 define <8 x i32> @shuffle_v8i32(<8 x i32> %x, <8 x i32> %y) {
 ; CHECK-LABEL: shuffle_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 203
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7>
   ret <8 x i32> %s
 }
 
 define <4 x i16> @shuffle_xv_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: shuffle_xv_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 9
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmerge.vim v8, v8, 5, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @shuffle_vx_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: shuffle_vx_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 6
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmerge.vim v8, v8, 5, v0
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @vrgather_permute_shuffle_vu_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: vrgather_permute_shuffle_vu_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI4_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vrgather.vv v25, v8, v26
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 1>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @vrgather_permute_shuffle_uv_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: vrgather_permute_shuffle_uv_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI5_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vrgather.vv v25, v8, v26
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> undef, <4 x i16> %x, <4 x i32> <i32 5, i32 6, i32 4, i32 5>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) {
 ; CHECK-LABEL: vrgather_shuffle_vv_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 1
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.s.x v25, a0
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 3
 ; CHECK-NEXT:    lui a0, %hi(.LCPI6_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI6_0)
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v27, (a0)
 ; CHECK-NEXT:    vrgather.vv v25, v8, v27
 ; CHECK-NEXT:    addi a0, zero, 8
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,tu,mu
 ; CHECK-NEXT:    vrgather.vv v25, v9, v26, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: vrgather_shuffle_xv_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 12
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    lui a0, %hi(.LCPI7_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 5
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,tu,mu
 ; CHECK-NEXT:    vrgather.vv v25, v8, v26, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) {
 ; CHECK-LABEL: vrgather_shuffle_vx_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 3
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.s.x v25, a0
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 1
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 5
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,tu,mu
 ; CHECK-NEXT:    vrgather.vv v25, v8, v26, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
   ret <4 x i16> %s
 }
 
 define <8 x i64> @vrgather_permute_shuffle_vu_v8i64(<8 x i64> %x) {

 
 define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
 ; RV32-LABEL: vrgather_shuffle_vv_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 5
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v25, a0
 ; RV32-NEXT:    addi a0, zero, 36
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vmerge.vim v26, v26, 2, v0
 ; RV32-NEXT:    vsetivli a0, 8, e16,m1,tu,mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 7
 ; RV32-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI11_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v8, v25
 ; RV32-NEXT:    addi a0, zero, 164
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v12, v26, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vv_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 5
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.s.x v28, a0
 ; RV64-NEXT:    addi a0, zero, 36
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    vmerge.vim v16, v16, 2, v0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vslideup.vi v16, v28, 7
 ; RV64-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI11_0)
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v20, (a0)
 ; RV64-NEXT:    vrgather.vv v28, v8, v20
 ; RV64-NEXT:    addi a0, zero, 164
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vrgather.vv v28, v12, v16, v0.t
 ; RV64-NEXT:    vmv4r.v v8, v28
 ; RV64-NEXT:    ret
   %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
   ret <8 x i64> %s
 }

 ; RV32-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI12_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vmv.v.i v12, -1
 ; RV32-NEXT:    vrgatherei16.vv v28, v12, v25
 ; RV32-NEXT:    addi a0, zero, 113
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v8, v27, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_xv_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 6
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.s.x v28, a0
 ; RV64-NEXT:    addi a0, zero, 4
 ; RV64-NEXT:    vmv.s.x v12, a0
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    vsetivli a0, 6, e64,m4,tu,mu
 ; RV64-NEXT:    vslideup.vi v16, v12, 5
 ; RV64-NEXT:    vsetivli a0, 7, e64,m4,tu,mu
 ; RV64-NEXT:    vslideup.vi v16, v28, 6
 ; RV64-NEXT:    addi a0, zero, 113
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.v.i v28, -1
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vrgather.vv v28, v8, v16, v0.t
 ; RV64-NEXT:    vmv4r.v v8, v28
 ; RV64-NEXT:    ret
   %s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3>
   ret <8 x i64> %s
 }
 
 define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
 ; RV32-LABEL: vrgather_shuffle_vx_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI13_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vmv4r.v v28, v8
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v8, v28, v25
 ; RV32-NEXT:    addi a0, zero, 140
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI13_1)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI13_1)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vmv.v.i v28, 5
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v8, v28, v25, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vx_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 115
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI13_0)
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v12, (a0)
 ; RV64-NEXT:    vmv.v.i v28, 5
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vrgather.vv v28, v8, v12, v0.t
 ; RV64-NEXT:    vmv4r.v v8, v28
 ; RV64-NEXT:    ret
   %s = shufflevector <8 x i64> %x, <8 x i64> <i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5>, <8 x i32> <i32 0, i32 3, i32 10, i32 9, i32 4, i32 1, i32 7, i32 14>
   ret <8 x i64> %s
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

 ; LMULMAX2-RV32-NEXT:    vlse64.v v26, (a1), zero
 ; LMULMAX2-RV32-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,mf8,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a3
 ; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a2
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v25, v25, a1, v0
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret

 ; LMULMAX2-RV32-NEXT:    vsetivli a5, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a4)
 ; LMULMAX2-RV32-NEXT:    addi a4, a0, 96
 ; LMULMAX2-RV32-NEXT:    vle64.v v28, (a4)
 ; LMULMAX2-RV32-NEXT:    vle64.v v30, (a0)
 ; LMULMAX2-RV32-NEXT:    addi a0, a0, 32
 ; LMULMAX2-RV32-NEXT:    vle64.v v8, (a0)
 ; LMULMAX2-RV32-NEXT:    addi a0, zero, 85
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a4, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a0
 ; LMULMAX2-RV32-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v10, a2
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v10, v10, a1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vadd.vv v8, v8, v10
 ; LMULMAX2-RV32-NEXT:    vadd.vv v30, v30, v10
 ; LMULMAX2-RV32-NEXT:    vadd.vv v28, v28, v10

 ; LMULMAX1-RV32-NEXT:    addi a4, a0, 32
 ; LMULMAX1-RV32-NEXT:    vle64.v v29, (a4)
 ; LMULMAX1-RV32-NEXT:    addi a4, a0, 48
 ; LMULMAX1-RV32-NEXT:    vle64.v v30, (a4)
 ; LMULMAX1-RV32-NEXT:    vle64.v v31, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a0, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle64.v v8, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a0, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,mf8,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a0
 ; LMULMAX1-RV32-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v9, a2
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v9, v9, a1, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vadd.vv v8, v8, v9
 ; LMULMAX1-RV32-NEXT:    vadd.vv v31, v31, v9
 ; LMULMAX1-RV32-NEXT:    vadd.vv v30, v30, v9

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 }
 
 define void @mulhu_v16i8(<16 x i8>* %x) {
 ; RV32-LABEL: mulhu_v16i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vle8.v v25, (a0)
 ; RV32-NEXT:    addi a1, zero, 513
-; RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v26, 4
 ; RV32-NEXT:    vmerge.vim v26, v26, 1, v0
 ; RV32-NEXT:    lui a1, 1
 ; RV32-NEXT:    addi a2, a1, 78
-; RV32-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a2
 ; RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vmerge.vim v26, v26, 3, v0
 ; RV32-NEXT:    lui a2, 8
 ; RV32-NEXT:    addi a2, a2, 304
-; RV32-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a2
 ; RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vmerge.vim v26, v26, 2, v0
 ; RV32-NEXT:    lui a2, 3
 ; RV32-NEXT:    addi a2, a2, -2044
-; RV32-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a2
 ; RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v27, 0
 ; RV32-NEXT:    addi a2, zero, -128
 ; RV32-NEXT:    vmerge.vxm v28, v27, a2, v0
 ; RV32-NEXT:    addi a1, a1, 32
-; RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    lui a1, %hi(.LCPI52_0)
 ; RV32-NEXT:    addi a1, a1, %lo(.LCPI52_0)
 ; RV32-NEXT:    vle8.v v29, (a1)
 ; RV32-NEXT:    vmerge.vim v27, v27, 1, v0
 ; RV32-NEXT:    vsrl.vv v27, v25, v27
 ; RV32-NEXT:    vmulhu.vv v27, v27, v29
 ; RV32-NEXT:    vsub.vv v25, v25, v27
 ; RV32-NEXT:    vmulhu.vv v25, v25, v28
 ; RV32-NEXT:    vadd.vv v25, v25, v27
 ; RV32-NEXT:    vsrl.vv v25, v25, v26
 ; RV32-NEXT:    vse8.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhu_v16i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vle8.v v25, (a0)
 ; RV64-NEXT:    addi a1, zero, 513
-; RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a1
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v26, 4
 ; RV64-NEXT:    vmerge.vim v26, v26, 1, v0
 ; RV64-NEXT:    lui a1, 1
 ; RV64-NEXT:    addiw a2, a1, 78
-; RV64-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a2
 ; RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vmerge.vim v26, v26, 3, v0
 ; RV64-NEXT:    lui a2, 8
 ; RV64-NEXT:    addiw a2, a2, 304
-; RV64-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a2
 ; RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vmerge.vim v26, v26, 2, v0
 ; RV64-NEXT:    lui a2, 3
 ; RV64-NEXT:    addiw a2, a2, -2044
-; RV64-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a2
 ; RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v27, 0
 ; RV64-NEXT:    addi a2, zero, -128
 ; RV64-NEXT:    vmerge.vxm v28, v27, a2, v0
 ; RV64-NEXT:    addiw a1, a1, 32
-; RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a1
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    lui a1, %hi(.LCPI52_0)
 ; RV64-NEXT:    addi a1, a1, %lo(.LCPI52_0)
 ; RV64-NEXT:    vle8.v v29, (a1)
 ; RV64-NEXT:    vmerge.vim v27, v27, 1, v0
 ; RV64-NEXT:    vsrl.vv v27, v25, v27
 ; RV64-NEXT:    vmulhu.vv v27, v27, v29

 define void @mulhu_v8i16(<8 x i16>* %x) {
 ; CHECK-LABEL: mulhu_v8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    vmv.s.x v26, a1
 ; CHECK-NEXT:    addi a1, zero, 33
-; CHECK-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a1
 ; CHECK-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v27, 3
 ; CHECK-NEXT:    vmerge.vim v27, v27, 2, v0
 ; CHECK-NEXT:    vsetivli a1, 7, e16,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v27, v26, 6
 ; CHECK-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v28, 0

 
 define void @mulhs_v16i8(<16 x i8>* %x) {
 ; RV32-LABEL: mulhs_v16i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vle8.v v25, (a0)
 ; RV32-NEXT:    lui a1, 5
 ; RV32-NEXT:    addi a1, a1, -1452
-; RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v26, 7
 ; RV32-NEXT:    vmerge.vim v26, v26, 1, v0
 ; RV32-NEXT:    addi a1, zero, -123
 ; RV32-NEXT:    vmv.v.x v27, a1
 ; RV32-NEXT:    addi a1, zero, 57
 ; RV32-NEXT:    vmerge.vxm v27, v27, a1, v0
 ; RV32-NEXT:    vmulhu.vv v25, v25, v27
 ; RV32-NEXT:    vsrl.vv v25, v25, v26
 ; RV32-NEXT:    vse8.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhs_v16i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vle8.v v25, (a0)
 ; RV64-NEXT:    lui a1, 5
 ; RV64-NEXT:    addiw a1, a1, -1452
-; RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a1
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v26, 7
 ; RV64-NEXT:    vmerge.vim v26, v26, 1, v0
 ; RV64-NEXT:    addi a1, zero, -123
 ; RV64-NEXT:    vmv.v.x v27, a1
 ; RV64-NEXT:    addi a1, zero, 57
 ; RV64-NEXT:    vmerge.vxm v27, v27, a1, v0
 ; RV64-NEXT:    vmulhu.vv v25, v25, v27
 ; RV64-NEXT:    vsrl.vv v25, v25, v26
 ; RV64-NEXT:    vse8.v v25, (a0)
 ; RV64-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
   store <16 x i8> %b, <16 x i8>* %x
   ret void
 }
 
 define void @mulhs_v8i16(<8 x i16>* %x) {
 ; RV32-LABEL: mulhs_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    addi a1, zero, 105
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    lui a1, 5
 ; RV32-NEXT:    addi a1, a1, -1755
 ; RV32-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a1
 ; RV32-NEXT:    lui a1, 1048571
 ; RV32-NEXT:    addi a1, a1, 1755
 ; RV32-NEXT:    vmerge.vxm v26, v26, a1, v0
 ; RV32-NEXT:    vmulh.vv v25, v25, v26
 ; RV32-NEXT:    vsra.vi v25, v25, 1
 ; RV32-NEXT:    vsrl.vi v26, v25, 15
 ; RV32-NEXT:    vadd.vv v25, v25, v26
 ; RV32-NEXT:    vse16.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhs_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    addi a1, zero, 105
-; RV64-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a1
 ; RV64-NEXT:    lui a1, 5
 ; RV64-NEXT:    addiw a1, a1, -1755
 ; RV64-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a1
 ; RV64-NEXT:    lui a1, 1048571
 ; RV64-NEXT:    addiw a1, a1, 1755
 ; RV64-NEXT:    vmerge.vxm v26, v26, a1, v0

 }
 
 define void @mulhs_v4i32(<4 x i32>* %x) {
 ; RV32-LABEL: mulhs_v4i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vle32.v v25, (a0)
 ; RV32-NEXT:    addi a1, zero, 5
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    lui a1, 419430
 ; RV32-NEXT:    addi a1, a1, 1639
 ; RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a1
 ; RV32-NEXT:    lui a1, 629146
 ; RV32-NEXT:    addi a1, a1, -1639
 ; RV32-NEXT:    vmerge.vxm v26, v26, a1, v0

 ; RV32-NEXT:    addi a2, a1, 1365
 ; RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a2
 ; RV32-NEXT:    addi a1, a1, 1366
 ; RV32-NEXT:    vmv.s.x v26, a1
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vmulh.vv v26, v25, v26
 ; RV32-NEXT:    addi a1, zero, 3
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v27, -1
 ; RV32-NEXT:    vmerge.vim v27, v27, 0, v0
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vmul.vv v25, v25, v27
 ; RV32-NEXT:    vadd.vv v25, v26, v25
 ; RV32-NEXT:    addi a1, zero, 63

 define void @mulhu_v32i8(<32 x i8>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhu_v32i8:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    lui a2, 66049
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    lui a2, %hi(.LCPI129_0)
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, %lo(.LCPI129_0)
 ; LMULMAX2-RV32-NEXT:    vle8.v v28, (a2)
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v8, v30, 1, v0
 ; LMULMAX2-RV32-NEXT:    vsrl.vv v8, v26, v8
 ; LMULMAX2-RV32-NEXT:    vmulhu.vv v28, v8, v28
 ; LMULMAX2-RV32-NEXT:    vsub.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a2, 163907
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, -2044
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    addi a2, zero, -128
 ; LMULMAX2-RV32-NEXT:    vsetvli a3, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a2, v0
 ; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a2, 8208
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 513
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 4
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV32-NEXT:    lui a2, 66785
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 78
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 3, v0
 ; LMULMAX2-RV32-NEXT:    lui a2, 529160
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 304
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV32-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhu_v32i8:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    lui a2, 66049
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 32
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    lui a2, %hi(.LCPI129_0)
 ; LMULMAX2-RV64-NEXT:    addi a2, a2, %lo(.LCPI129_0)
 ; LMULMAX2-RV64-NEXT:    vle8.v v28, (a2)
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v8, v30, 1, v0
 ; LMULMAX2-RV64-NEXT:    vsrl.vv v8, v26, v8
 ; LMULMAX2-RV64-NEXT:    vmulhu.vv v28, v8, v28
 ; LMULMAX2-RV64-NEXT:    vsub.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a2, 163907
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, -2044
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    addi a2, zero, -128
 ; LMULMAX2-RV64-NEXT:    vsetvli a3, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vxm v30, v30, a2, v0
 ; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v30
 ; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a2, 8208
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 513
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 4
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV64-NEXT:    lui a2, 66785
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 78
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 3, v0
 ; LMULMAX2-RV64-NEXT:    lui a2, 529160
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 304
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV64-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: mulhu_v32i8:

 
 define void @mulhu_v16i16(<16 x i16>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhu_v16i16:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle16.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    lui a1, 2
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 289
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 3
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV32-NEXT:    lui a1, 4
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 64
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV32-NEXT:    vmv1r.v v12, v0
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 257
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-RV32-NEXT:    lui a1, 1048568
 ; LMULMAX2-RV32-NEXT:    lui a2, %hi(.LCPI130_0)
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, %lo(.LCPI130_0)
 ; LMULMAX2-RV32-NEXT:    vle16.v v8, (a2)
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v10, v30, a1, v0

 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhu_v16i16:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle16.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    lui a1, 2
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 289
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 3
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV64-NEXT:    lui a1, 4
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 64
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV64-NEXT:    vmv1r.v v12, v0
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 257
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-RV64-NEXT:    lui a1, 1048568
 ; LMULMAX2-RV64-NEXT:    lui a2, %hi(.LCPI130_0)
 ; LMULMAX2-RV64-NEXT:    addi a2, a2, %lo(.LCPI130_0)
 ; LMULMAX2-RV64-NEXT:    vle16.v v8, (a2)
 ; LMULMAX2-RV64-NEXT:    vmerge.vxm v10, v30, a1, v0

 }
 
 define void @mulhu_v8i32(<8 x i32>* %x) {
 ; LMULMAX2-LABEL: mulhu_v8i32:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vle32.v v26, (a0)
 ; LMULMAX2-NEXT:    addi a1, zero, 68
-; LMULMAX2-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    lui a1, %hi(.LCPI131_0)
 ; LMULMAX2-NEXT:    addi a1, a1, %lo(.LCPI131_0)
 ; LMULMAX2-NEXT:    vle32.v v28, (a1)
 ; LMULMAX2-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-NEXT:    lui a1, 524288
 ; LMULMAX2-NEXT:    vmerge.vxm v30, v30, a1, v0
 ; LMULMAX2-NEXT:    vmulhu.vv v28, v26, v28
 ; LMULMAX2-NEXT:    vsub.vv v26, v26, v28
 ; LMULMAX2-NEXT:    vmulhu.vv v26, v26, v30
 ; LMULMAX2-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-NEXT:    addi a1, zero, 136
-; LMULMAX2-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v28, 2
 ; LMULMAX2-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;

 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    addi a2, zero, -123
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a2
 ; LMULMAX2-RV32-NEXT:    lui a2, 304453
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, -1452
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    addi a2, zero, 57
 ; LMULMAX2-RV32-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a2, v0
 ; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 7
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV32-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhs_v32i8:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    addi a2, zero, -123
 ; LMULMAX2-RV64-NEXT:    vmv.v.x v28, a2
 ; LMULMAX2-RV64-NEXT:    lui a2, 304453
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, -1452
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    addi a2, zero, 57
 ; LMULMAX2-RV64-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vxm v28, v28, a2, v0
 ; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 7
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV64-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: mulhs_v32i8:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle8.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    lui a2, 5
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -1452
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v27, -9
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v27, v27, 9, v0
 ; LMULMAX1-RV32-NEXT:    vdivu.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vdivu.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    vse8.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: mulhs_v32i8:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vle8.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV64-NEXT:    vle8.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    lui a2, 5
 ; LMULMAX1-RV64-NEXT:    addiw a2, a2, -1452
-; LMULMAX1-RV64-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX1-RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v27, -9
 ; LMULMAX1-RV64-NEXT:    vmerge.vim v27, v27, 9, v0
 ; LMULMAX1-RV64-NEXT:    vdivu.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vdivu.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    vse8.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = udiv <32 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
   store <32 x i8> %b, <32 x i8>* %x
   ret void
 }
 
 define void @mulhs_v16i16(<16 x i16>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhs_v16i16:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle16.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    lui a1, 7
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1687
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 5
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1755
 ; LMULMAX2-RV32-NEXT:    vsetivli a2, 16, e16,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 1048571
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1755
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
 ; LMULMAX2-RV32-NEXT:    vmulh.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vsra.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v28, v26, 15
 ; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhs_v16i16:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle16.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    lui a1, 7
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1687
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e16,mf4,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    lui a1, 5
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1755
 ; LMULMAX2-RV64-NEXT:    vsetivli a2, 16, e16,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.x v28, a1
 ; LMULMAX2-RV64-NEXT:    lui a1, 1048571
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1755
 ; LMULMAX2-RV64-NEXT:    vmerge.vxm v28, v28, a1, v0
 ; LMULMAX2-RV64-NEXT:    vmulh.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vsra.vi v26, v26, 1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v28, v26, 15
 ; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: mulhs_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a1, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a1)
 ; LMULMAX1-NEXT:    addi a2, zero, 105
-; LMULMAX1-NEXT:    vsetivli a3, 1, e8,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a3, 1, e8,mf8,ta,mu
 ; LMULMAX1-NEXT:    vmv.s.x v0, a2
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v27, 7
 ; LMULMAX1-NEXT:    vmerge.vim v27, v27, -7, v0
 ; LMULMAX1-NEXT:    vdiv.vv v26, v26, v27
 ; LMULMAX1-NEXT:    vdiv.vv v25, v25, v27
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    vse16.v v26, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <16 x i16>, <16 x i16>* %x
   %b = sdiv <16 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7, i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
   store <16 x i16> %b, <16 x i16>* %x
   ret void
 }
 
 define void @mulhs_v8i32(<8 x i32>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhs_v8i32:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle32.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 85
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 419430
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1639
 ; LMULMAX2-RV32-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 629146
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1639
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0

 ;
 ; LMULMAX1-RV32-LABEL: mulhs_v8i32:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle32.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a2, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a3, 1, e8,mf8,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX1-RV32-NEXT:    lui a2, 419430
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 1639
 ; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v27, a2
 ; LMULMAX1-RV32-NEXT:    lui a2, 629146
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -1639
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v27, v27, a2, v0

 }
 
 define void @mulhs_v4i64(<4 x i64>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhs_v4i64:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 51
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, -1
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmul.vv v28, v26, v28
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 17
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a2, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a2
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1366
 ; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmulh.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 63
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a1
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 68
-; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v30, v30, 1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsra.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhs_v4i64:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 5
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, -1
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 0, v0
 ; LMULMAX2-RV64-NEXT:    vmul.vv v28, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 21845
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX4
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX4
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8
 
 define <3 x i1> @buildvec_mask_v1i1() {
 ; CHECK-LABEL: buildvec_mask_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 2
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <3 x i1> <i1 0, i1 1, i1 0>
 }
 
 define <3 x i1> @buildvec_mask_optsize_v1i1() optsize {
 ; CHECK-LABEL: buildvec_mask_optsize_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 2
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <3 x i1> <i1 0, i1 1, i1 0>
 }
 
 define <4 x i1> @buildvec_mask_v4i1() {
 ; CHECK-LABEL: buildvec_mask_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 6
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <4 x i1> <i1 0, i1 1, i1 1, i1 0>
 }
 
 define <8 x i1> @buildvec_mask_v8i1() {
 ; CHECK-LABEL: buildvec_mask_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 182
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
 }
 
 define <10 x i1> @buildvec_mask_v10i1() {
 ; CHECK-LABEL: buildvec_mask_v10i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 949
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1>
 }
 
 define <16 x i1> @buildvec_mask_v16i1() {
 ; CHECK-RV32-LABEL: buildvec_mask_v16i1:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    lui a0, 11
 ; CHECK-RV32-NEXT:    addi a0, a0, 1718
-; CHECK-RV32-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-RV32-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-RV32-NEXT:    vmv.s.x v0, a0
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: buildvec_mask_v16i1:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    lui a0, 11
 ; CHECK-RV64-NEXT:    addiw a0, a0, 1718
-; CHECK-RV64-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-RV64-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-RV64-NEXT:    vmv.s.x v0, a0
 ; CHECK-RV64-NEXT:    ret
   ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
 }
 
 define <16 x i1> @buildvec_mask_v16i1_undefs() {
 ; CHECK-LABEL: buildvec_mask_v16i1_undefs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 1722
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    ret
   ret <16 x i1> <i1 undef, i1 1, i1 undef, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>
 }
 
 define <32 x i1> @buildvec_mask_v32i1() {
 ; RV32-LMULMAX1-LABEL: buildvec_mask_v32i1:
 ; RV32-LMULMAX1:       # %bb.0:
 ; RV32-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 11
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX1-NEXT:    ret
 ;
 ; RV64-LMULMAX1-LABEL: buildvec_mask_v32i1:
 ; RV64-LMULMAX1:       # %bb.0:
 ; RV64-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 11
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX1-NEXT:    ret
 ;
 ; RV32-LMULMAX2-LABEL: buildvec_mask_v32i1:
 ; RV32-LMULMAX2:       # %bb.0:
 ; RV32-LMULMAX2-NEXT:    lui a0, 748384
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX2-NEXT:    ret
 ;
 ; RV64-LMULMAX2-LABEL: buildvec_mask_v32i1:
 ; RV64-LMULMAX2:       # %bb.0:
 ; RV64-LMULMAX2-NEXT:    lui a0, 748384
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX2-NEXT:    ret
 ;
 ; RV32-LMULMAX4-LABEL: buildvec_mask_v32i1:
 ; RV32-LMULMAX4:       # %bb.0:
 ; RV32-LMULMAX4-NEXT:    lui a0, 748384
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX4-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX4-NEXT:    ret
 ;
 ; RV64-LMULMAX4-LABEL: buildvec_mask_v32i1:
 ; RV64-LMULMAX4:       # %bb.0:
 ; RV64-LMULMAX4-NEXT:    lui a0, 748384
 ; RV64-LMULMAX4-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX4-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX4-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX4-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX4-NEXT:    ret
 ;
 ; RV32-LMULMAX8-LABEL: buildvec_mask_v32i1:
 ; RV32-LMULMAX8:       # %bb.0:
 ; RV32-LMULMAX8-NEXT:    lui a0, 748384
 ; RV32-LMULMAX8-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX8-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX8-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX8-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX8-NEXT:    ret
 ;
 ; RV64-LMULMAX8-LABEL: buildvec_mask_v32i1:
 ; RV64-LMULMAX8:       # %bb.0:
 ; RV64-LMULMAX8-NEXT:    lui a0, 748384
 ; RV64-LMULMAX8-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX8-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX8-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX8-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX8-NEXT:    ret
   ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
 }
 
 define <64 x i1> @buildvec_mask_v64i1() {
 ; RV32-LMULMAX1-LABEL: buildvec_mask_v64i1:
 ; RV32-LMULMAX1:       # %bb.0:
 ; RV32-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 4
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 11
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV32-LMULMAX1-NEXT:    ret
 ;
 ; RV64-LMULMAX1-LABEL: buildvec_mask_v64i1:
 ; RV64-LMULMAX1:       # %bb.0:
 ; RV64-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 4
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 11
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV64-LMULMAX1-NEXT:    ret
 ;
 ; RV32-LMULMAX2-LABEL: buildvec_mask_v64i1:
 ; RV32-LMULMAX2:       # %bb.0:
 ; RV32-LMULMAX2-NEXT:    lui a0, 748384
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 748388
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX2-NEXT:    ret
 ;
 ; RV64-LMULMAX2-LABEL: buildvec_mask_v64i1:
 ; RV64-LMULMAX2:       # %bb.0:
 ; RV64-LMULMAX2-NEXT:    lui a0, 748384
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 748388
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX2-NEXT:    ret
 ;
 ; RV32-LMULMAX4-LABEL: buildvec_mask_v64i1:
 ; RV32-LMULMAX4:       # %bb.0:
 ; RV32-LMULMAX4-NEXT:    lui a0, 748388
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, -1793
-; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v25, a0
 ; RV32-LMULMAX4-NEXT:    lui a0, 748384
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v0, a0
-; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-LMULMAX4-NEXT:    vslideup.vi v0, v25, 1
 ; RV32-LMULMAX4-NEXT:    ret
 ;
 ; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1:
 ; RV64-LMULMAX4:       # %bb.0:
 ; RV64-LMULMAX4-NEXT:    lui a0, 1048429
 ; RV64-LMULMAX4-NEXT:    addiw a0, a0, 1735
 ; RV64-LMULMAX4-NEXT:    slli a0, a0, 13
 ; RV64-LMULMAX4-NEXT:    addi a0, a0, 1023
 ; RV64-LMULMAX4-NEXT:    slli a0, a0, 13
 ; RV64-LMULMAX4-NEXT:    addi a0, a0, -1189
 ; RV64-LMULMAX4-NEXT:    slli a0, a0, 17
 ; RV64-LMULMAX4-NEXT:    addi a0, a0, 1776
 ; RV64-LMULMAX4-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-LMULMAX4-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX4-NEXT:    ret
 ;
 ; RV32-LMULMAX8-LABEL: buildvec_mask_v64i1:
 ; RV32-LMULMAX8:       # %bb.0:
 ; RV32-LMULMAX8-NEXT:    lui a0, 748388
 ; RV32-LMULMAX8-NEXT:    addi a0, a0, -1793
-; RV32-LMULMAX8-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV32-LMULMAX8-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-LMULMAX8-NEXT:    vmv.s.x v25, a0
 ; RV32-LMULMAX8-NEXT:    lui a0, 748384
 ; RV32-LMULMAX8-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX8-NEXT:    vmv.s.x v0, a0
-; RV32-LMULMAX8-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-LMULMAX8-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-LMULMAX8-NEXT:    vslideup.vi v0, v25, 1
 ; RV32-LMULMAX8-NEXT:    ret
 ;
 ; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1:
 ; RV64-LMULMAX8:       # %bb.0:
 ; RV64-LMULMAX8-NEXT:    lui a0, 1048429
 ; RV64-LMULMAX8-NEXT:    addiw a0, a0, 1735
 ; RV64-LMULMAX8-NEXT:    slli a0, a0, 13
 ; RV64-LMULMAX8-NEXT:    addi a0, a0, 1023
 ; RV64-LMULMAX8-NEXT:    slli a0, a0, 13
 ; RV64-LMULMAX8-NEXT:    addi a0, a0, -1189
 ; RV64-LMULMAX8-NEXT:    slli a0, a0, 17
 ; RV64-LMULMAX8-NEXT:    addi a0, a0, 1776
 ; RV64-LMULMAX8-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-LMULMAX8-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX8-NEXT:    ret
   ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
 }
 
 define <128 x i1> @buildvec_mask_v128i1() {
 ; RV32-LMULMAX1-LABEL: buildvec_mask_v128i1:
 ; RV32-LMULMAX1:       # %bb.0:
 ; RV32-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 11
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 8
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v12, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 4
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 14
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1722
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v14, a0
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v11, v0
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v13, v9
 ; RV32-LMULMAX1-NEXT:    ret
 ;
 ; RV64-LMULMAX1-LABEL: buildvec_mask_v128i1:
 ; RV64-LMULMAX1:       # %bb.0:
 ; RV64-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 11
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 8
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v12, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 4
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 14
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1722
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v14, a0
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v11, v0
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v13, v9
 ; RV64-LMULMAX1-NEXT:    ret
 ;
 ; RV32-LMULMAX2-LABEL: buildvec_mask_v128i1:
 ; RV32-LMULMAX2:       # %bb.0:
 ; RV32-LMULMAX2-NEXT:    lui a0, 748384
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 748388
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 551776
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 945060
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v10, a0
 ; RV32-LMULMAX2-NEXT:    ret
 ;
 ; RV64-LMULMAX2-LABEL: buildvec_mask_v128i1:
 ; RV64-LMULMAX2:       # %bb.0:
 ; RV64-LMULMAX2-NEXT:    lui a0, 748384
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 748388
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 551776
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v9, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 945060
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v10, a0
 ; RV64-LMULMAX2-NEXT:    ret
 ;
 ; RV32-LMULMAX4-LABEL: buildvec_mask_v128i1:
 ; RV32-LMULMAX4:       # %bb.0:
 ; RV32-LMULMAX4-NEXT:    lui a0, 748388
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, -1793
-; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v25, a0
 ; RV32-LMULMAX4-NEXT:    lui a0, 748384
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v0, a0
-; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-LMULMAX4-NEXT:    vslideup.vi v0, v25, 1
 ; RV32-LMULMAX4-NEXT:    lui a0, 945060
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, -1793
-; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v25, a0
 ; RV32-LMULMAX4-NEXT:    lui a0, 551776
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX4-NEXT:    vmv.s.x v8, a0
-; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-LMULMAX4-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-LMULMAX4-NEXT:    vslideup.vi v8, v25, 1
 ; RV32-LMULMAX4-NEXT:    ret
 ;
 ; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1:
 ; RV64-LMULMAX4:       # %bb.0:
 ; RV64-LMULMAX4-NEXT:    lui a0, 841543
 ; RV64-LMULMAX4-NEXT:    addiw a0, a0, 511
 ; RV64-LMULMAX4-NEXT:    slli a0, a0, 14

 ; RV64-LMULMAX8-NEXT:    ret
   ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
 }
 
 define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
 ; RV32-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1:
 ; RV32-LMULMAX1:       # %bb.0:
 ; RV32-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV32-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 11
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 8
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v12, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 4
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 14
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1722
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v14, a0
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v11, v0
 ; RV32-LMULMAX1-NEXT:    vmv1r.v v13, v9
 ; RV32-LMULMAX1-NEXT:    ret
 ;
 ; RV64-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1:
 ; RV64-LMULMAX1:       # %bb.0:
 ; RV64-LMULMAX1-NEXT:    addi a0, zero, 1776
-; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV64-LMULMAX1-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 11
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 8
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1718
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v12, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 4
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV64-LMULMAX1-NEXT:    lui a0, 14
 ; RV64-LMULMAX1-NEXT:    addiw a0, a0, 1722
 ; RV64-LMULMAX1-NEXT:    vmv.s.x v14, a0
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v11, v0
 ; RV64-LMULMAX1-NEXT:    vmv1r.v v13, v9
 ; RV64-LMULMAX1-NEXT:    ret
 ;
 ; RV32-LMULMAX2-LABEL: buildvec_mask_optsize_v128i1:
 ; RV32-LMULMAX2:       # %bb.0:
 ; RV32-LMULMAX2-NEXT:    lui a0, 748384
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV32-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 748388
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 551776
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, 1776
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX2-NEXT:    lui a0, 945060
 ; RV32-LMULMAX2-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX2-NEXT:    vmv.s.x v10, a0
 ; RV32-LMULMAX2-NEXT:    ret
 ;
 ; RV64-LMULMAX2-LABEL: buildvec_mask_optsize_v128i1:
 ; RV64-LMULMAX2:       # %bb.0:
 ; RV64-LMULMAX2-NEXT:    lui a0, 748384
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; RV64-LMULMAX2-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v0, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 748388
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, -1793
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v8, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 551776
 ; RV64-LMULMAX2-NEXT:    addiw a0, a0, 1776
 ; RV64-LMULMAX2-NEXT:    vmv.s.x v9, a0
 ; RV64-LMULMAX2-NEXT:    lui a0, 945060

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
 
 define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
 ; CHECK-LABEL: load_store_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 1, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 1, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <1 x i1>, <1 x i1>* %x
   store <1 x i1> %a, <1 x i1>* %y
   ret void
 }
 
 define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
 ; CHECK-LABEL: load_store_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i1>, <2 x i1>* %x
   store <2 x i1> %a, <2 x i1>* %y
   ret void
 }
 
 define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
 ; CHECK-LABEL: load_store_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i1>, <4 x i1>* %x
   store <4 x i1> %a, <4 x i1>* %y
   ret void
 }
 
 define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: load_store_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   store <8 x i1> %a, <8 x i1>* %y
   ret void
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: and_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vle1.v v26, (a1)
 ; CHECK-NEXT:    vmand.mm v25, v25, v26
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = and <8 x i1> %a, %b
; CHECK-NEXT:    ret
   %c = xor <64 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   store <64 x i1> %c, <64 x i1>* %x
   ret void
 }
 
 define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: andnot_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vle1.v v26, (a1)
 ; CHECK-NEXT:    vmandnot.mm v25, v25, v26
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = xor <8 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
; CHECK-NEXT:    ret
   %d = xor <32 x i1> %b, %c
   store <32 x i1> %d, <32 x i1>* %x
   ret void
 }
 
 define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: nand_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vle1.v v26, (a1)
 ; CHECK-NEXT:    vmnand.mm v25, v25, v26
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = and <8 x i1> %a, %b

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
 
 define void @splat_ones_v1i1(<1 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <1 x i1> <i1 1>, <1 x i1>* %x
   ret void
 }
 
 define void @splat_zeros_v2i1(<2 x i1>* %x) {
 ; CHECK-LABEL: splat_zeros_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <2 x i1> zeroinitializer, <2 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v4i1(<4 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf2,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
   ret void
 }
 
 define void @splat_zeros_v8i1(<8 x i1>* %x) {
 ; CHECK-LABEL: splat_zeros_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmclr.m v25
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <8 x i1> zeroinitializer, <8 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v16i1(<16 x i1>* %x) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
 
 declare <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*>, i32, <1 x i1>, <1 x i8>)
 
 define <1 x i8> @mgather_v1i8(<1 x i8*> %ptrs, <1 x i1> %m, <1 x i8> %passthru) {
 ; RV32-LABEL: mgather_v1i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 1, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v1i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*> %ptrs, i32 1, <1 x i1> %m, <1 x i8> %passthru)
   ret <1 x i8> %v
 }
 
 declare <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*>, i32, <2 x i1>, <2 x i8>)
 
 define <2 x i8> @mgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   ret <2 x i8> %v
 }
 
 define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_sextload_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vsext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_sextload_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vsext.vf2 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   %ev = sext <2 x i8> %v to <2 x i16>
   ret <2 x i16> %ev
 }
 
 define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_zextload_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vzext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_zextload_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vzext.vf2 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   %ev = zext <2 x i8> %v to <2 x i16>
   ret <2 x i16> %ev
 }
 
 define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_sextload_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vsext.vf4 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_sextload_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vsext.vf4 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   %ev = sext <2 x i8> %v to <2 x i32>
   ret <2 x i32> %ev
 }
 
 define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_zextload_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vzext.vf4 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_zextload_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vzext.vf4 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   %ev = zext <2 x i8> %v to <2 x i32>
   ret <2 x i32> %ev
 }
 
 define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_sextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vsext.vf8 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_sextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vsext.vf8 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
   %ev = sext <2 x i8> %v to <2 x i64>
   ret <2 x i64> %ev
 }
 
 define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
 ; RV32-LABEL: mgather_v2i8_zextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vzext.vf8 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i8_zextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e8,mf8,tu,mu
; RV64-NEXT:    ret
   ret <8 x i8> %v
 }
 
 declare <1 x i16> @llvm.masked.gather.v1i16.v1p0i16(<1 x i16*>, i32, <1 x i1>, <1 x i16>)
 
 define <1 x i16> @mgather_v1i16(<1 x i16*> %ptrs, <1 x i1> %m, <1 x i16> %passthru) {
 ; RV32-LABEL: mgather_v1i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 1, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v1i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <1 x i16> @llvm.masked.gather.v1i16.v1p0i16(<1 x i16*> %ptrs, i32 2, <1 x i1> %m, <1 x i16> %passthru)
   ret <1 x i16> %v
 }
 
 declare <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*>, i32, <2 x i1>, <2 x i16>)
 
 define <2 x i16> @mgather_v2i16(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
 ; RV32-LABEL: mgather_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
   ret <2 x i16> %v
 }
 
 define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
 ; RV32-LABEL: mgather_v2i16_sextload_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vsext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i16_sextload_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vsext.vf2 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
   %ev = sext <2 x i16> %v to <2 x i32>
   ret <2 x i32> %ev
 }
 
 define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
 ; RV32-LABEL: mgather_v2i16_zextload_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vzext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i16_zextload_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vzext.vf2 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
   %ev = zext <2 x i16> %v to <2 x i32>
   ret <2 x i32> %ev
 }
 
 define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
 ; RV32-LABEL: mgather_v2i16_sextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vsext.vf4 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i16_sextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vsext.vf4 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
   %ev = sext <2 x i16> %v to <2 x i64>
   ret <2 x i64> %ev
 }
 
 define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
 ; RV32-LABEL: mgather_v2i16_zextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vzext.vf4 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i16_zextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
; RV64-NEXT:    ret
   ret <8 x i16> %v
 }
 
 declare <1 x i32> @llvm.masked.gather.v1i32.v1p0i32(<1 x i32*>, i32, <1 x i1>, <1 x i32>)
 
 define <1 x i32> @mgather_v1i32(<1 x i32*> %ptrs, <1 x i1> %m, <1 x i32> %passthru) {
 ; RV32-LABEL: mgather_v1i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 1, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v1i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <1 x i32> @llvm.masked.gather.v1i32.v1p0i32(<1 x i32*> %ptrs, i32 4, <1 x i1> %m, <1 x i32> %passthru)
   ret <1 x i32> %v
 }
 
 declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
 
 define <2 x i32> @mgather_v2i32(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
 ; RV32-LABEL: mgather_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
   ret <2 x i32> %v
 }
 
 define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
 ; RV32-LABEL: mgather_v2i32_sextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vsext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i32_sextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vsext.vf2 v8, v9
 ; RV64-NEXT:    ret
   %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
   %ev = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %ev
 }
 
 define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
 ; RV32-LABEL: mgather_v2i32_zextload_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vzext.vf2 v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2i32_zextload_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
; RV64-NEXT:    ret
   ret <8 x i64> %v
 }
 
 declare <1 x half> @llvm.masked.gather.v1f16.v1p0f16(<1 x half*>, i32, <1 x i1>, <1 x half>)
 
 define <1 x half> @mgather_v1f16(<1 x half*> %ptrs, <1 x i1> %m, <1 x half> %passthru) {
 ; RV32-LABEL: mgather_v1f16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 1, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v1f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <1 x half> @llvm.masked.gather.v1f16.v1p0f16(<1 x half*> %ptrs, i32 2, <1 x i1> %m, <1 x half> %passthru)
   ret <1 x half> %v
 }
 
 declare <2 x half> @llvm.masked.gather.v2f16.v2p0f16(<2 x half*>, i32, <2 x i1>, <2 x half>)
 
 define <2 x half> @mgather_v2f16(<2 x half*> %ptrs, <2 x i1> %m, <2 x half> %passthru) {
 ; RV32-LABEL: mgather_v2f16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT:    ret
   ret <8 x half> %v
 }
 
 declare <1 x float> @llvm.masked.gather.v1f32.v1p0f32(<1 x float*>, i32, <1 x i1>, <1 x float>)
 
 define <1 x float> @mgather_v1f32(<1 x float*> %ptrs, <1 x i1> %m, <1 x float> %passthru) {
 ; RV32-LABEL: mgather_v1f32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 1, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v1f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %v = call <1 x float> @llvm.masked.gather.v1f32.v1p0f32(<1 x float*> %ptrs, i32 4, <1 x i1> %m, <1 x float> %passthru)
   ret <1 x float> %v
 }
 
 declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1>, <2 x float>)
 
 define <2 x float> @mgather_v2f32(<2 x float*> %ptrs, <2 x i1> %m, <2 x float> %passthru) {
 ; RV32-LABEL: mgather_v2f32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,tu,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV32-NEXT:    vloxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_v2f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,tu,mu
 ; RV64-NEXT:    vloxei64.v v9, (zero), v8, v0.t

 ; RV64-LABEL: mgather_baseidx_v32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v25, v0
 ; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 16
 ; RV64-NEXT:    vslidedown.vi v28, v8, 16
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vsext.vf8 v16, v28
-; RV64-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 2, e8,mf4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
 ; RV64-NEXT:    vloxei64.v v26, (a0), v16, v0.t
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
 ; RV64-NEXT:    vmv1r.v v0, v25
 ; RV64-NEXT:    vloxei64.v v10, (a0), v16, v0.t

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <1 x half>, <1 x half>* %m_ptr
   %mask = fcmp oeq <1 x half> %m, zeroinitializer
   %load = call <1 x half> @llvm.masked.load.v1f16(<1 x half>* %a, i32 8, <1 x i1> %mask, <1 x half> undef)
   store <1 x half> %load, <1 x half>* %res_ptr
   ret void
 }
 declare <1 x half> @llvm.masked.load.v1f16(<1 x half>*, i32, <1 x i1>, <1 x half>)
 
 define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    fmv.w.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vle32.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse32.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <1 x float>, <1 x float>* %m_ptr
   %mask = fcmp oeq <1 x float> %m, zeroinitializer
; RV64-NEXT:    ret
   store <1 x double> %load, <1 x double>* %res_ptr
   ret void
 }
 declare <1 x double> @llvm.masked.load.v1f64(<1 x double>*, i32, <1 x i1>, <1 x double>)
 
 define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <2 x half>, <2 x half>* %m_ptr
   %mask = fcmp oeq <2 x half> %m, zeroinitializer
   %load = call <2 x half> @llvm.masked.load.v2f16(<2 x half>* %a, i32 8, <2 x i1> %mask, <2 x half> undef)
   store <2 x half> %load, <2 x half>* %res_ptr
   ret void
 }
 declare <2 x half> @llvm.masked.load.v2f16(<2 x half>*, i32, <2 x i1>, <2 x half>)
 
 define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    fmv.w.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vle32.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse32.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <2 x float>, <2 x float>* %m_ptr
   %mask = fcmp oeq <2 x float> %m, zeroinitializer
; RV64-NEXT:    ret
   store <2 x double> %load, <2 x double>* %res_ptr
   ret void
 }
 declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
 
 define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <4 x half>, <4 x half>* %m_ptr
   %mask = fcmp oeq <4 x half> %m, zeroinitializer

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define void @masked_load_v1i8(<1 x i8>* %a, <1 x i8>* %m_ptr, <1 x i8>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle8.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <1 x i8>, <1 x i8>* %m_ptr
   %mask = icmp eq <1 x i8> %m, zeroinitializer
   %load = call <1 x i8> @llvm.masked.load.v1i8(<1 x i8>* %a, i32 8, <1 x i1> %mask, <1 x i8> undef)
   store <1 x i8> %load, <1 x i8>* %res_ptr
   ret void
 }
 declare <1 x i8> @llvm.masked.load.v1i8(<1 x i8>*, i32, <1 x i1>, <1 x i8>)
 
 define void @masked_load_v1i16(<1 x i16>* %a, <1 x i16>* %m_ptr, <1 x i16>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <1 x i16>, <1 x i16>* %m_ptr
   %mask = icmp eq <1 x i16> %m, zeroinitializer
   %load = call <1 x i16> @llvm.masked.load.v1i16(<1 x i16>* %a, i32 8, <1 x i1> %mask, <1 x i16> undef)
   store <1 x i16> %load, <1 x i16>* %res_ptr
   ret void
 }
 declare <1 x i16> @llvm.masked.load.v1i16(<1 x i16>*, i32, <1 x i1>, <1 x i16>)
 
 define void @masked_load_v1i32(<1 x i32>* %a, <1 x i32>* %m_ptr, <1 x i32>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle32.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse32.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <1 x i32>, <1 x i32>* %m_ptr
   %mask = icmp eq <1 x i32> %m, zeroinitializer
   %load = call <1 x i32> @llvm.masked.load.v1i32(<1 x i32>* %a, i32 8, <1 x i1> %mask, <1 x i32> undef)
; CHECK-NEXT:    ret
   store <1 x i64> %load, <1 x i64>* %res_ptr
   ret void
 }
 declare <1 x i64> @llvm.masked.load.v1i64(<1 x i64>*, i32, <1 x i1>, <1 x i64>)
 
 define void @masked_load_v2i8(<2 x i8>* %a, <2 x i8>* %m_ptr, <2 x i8>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle8.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <2 x i8>, <2 x i8>* %m_ptr
   %mask = icmp eq <2 x i8> %m, zeroinitializer
   %load = call <2 x i8> @llvm.masked.load.v2i8(<2 x i8>* %a, i32 8, <2 x i1> %mask, <2 x i8> undef)
   store <2 x i8> %load, <2 x i8>* %res_ptr
   ret void
 }
 declare <2 x i8> @llvm.masked.load.v2i8(<2 x i8>*, i32, <2 x i1>, <2 x i8>)
 
 define void @masked_load_v2i16(<2 x i16>* %a, <2 x i16>* %m_ptr, <2 x i16>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <2 x i16>, <2 x i16>* %m_ptr
   %mask = icmp eq <2 x i16> %m, zeroinitializer
   %load = call <2 x i16> @llvm.masked.load.v2i16(<2 x i16>* %a, i32 8, <2 x i1> %mask, <2 x i16> undef)
   store <2 x i16> %load, <2 x i16>* %res_ptr
   ret void
 }
 declare <2 x i16> @llvm.masked.load.v2i16(<2 x i16>*, i32, <2 x i1>, <2 x i16>)
 
 define void @masked_load_v2i32(<2 x i32>* %a, <2 x i32>* %m_ptr, <2 x i32>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle32.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse32.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <2 x i32>, <2 x i32>* %m_ptr
   %mask = icmp eq <2 x i32> %m, zeroinitializer
   %load = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %a, i32 8, <2 x i1> %mask, <2 x i32> undef)
; CHECK-NEXT:    ret
   store <2 x i64> %load, <2 x i64>* %res_ptr
   ret void
 }
 declare <2 x i64> @llvm.masked.load.v2i64(<2 x i64>*, i32, <2 x i1>, <2 x i64>)
 
 define void @masked_load_v4i8(<4 x i8>* %a, <4 x i8>* %m_ptr, <4 x i8>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle8.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <4 x i8>, <4 x i8>* %m_ptr
   %mask = icmp eq <4 x i8> %m, zeroinitializer
   %load = call <4 x i8> @llvm.masked.load.v4i8(<4 x i8>* %a, i32 8, <4 x i1> %mask, <4 x i8> undef)
   store <4 x i8> %load, <4 x i8>* %res_ptr
   ret void
 }
 declare <4 x i8> @llvm.masked.load.v4i8(<4 x i8>*, i32, <4 x i1>, <4 x i8>)
 
 define void @masked_load_v4i16(<4 x i16>* %a, <4 x i16>* %m_ptr, <4 x i16>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle16.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse16.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <4 x i16>, <4 x i16>* %m_ptr
   %mask = icmp eq <4 x i16> %m, zeroinitializer
   %load = call <4 x i16> @llvm.masked.load.v4i16(<4 x i16>* %a, i32 8, <4 x i1> %mask, <4 x i16> undef)
; CHECK-NEXT:    ret
   store <4 x i64> %load, <4 x i64>* %res_ptr
   ret void
 }
 declare <4 x i64> @llvm.masked.load.v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)
 
 define void @masked_load_v8i8(<8 x i8>* %a, <8 x i8>* %m_ptr, <8 x i8>* %res_ptr) nounwind {
 ; CHECK-LABEL: masked_load_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a1)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vle8.v v25, (a0), v0.t
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    ret
   %m = load <8 x i8>, <8 x i8>* %m_ptr
   %mask = icmp eq <8 x i8> %m, zeroinitializer
   %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %a, i32 8, <8 x i1> %mask, <8 x i8> undef)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
 
 declare void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8>, <1 x i8*>, i32, <1 x i1>)
 
 define void @mscatter_v1i8(<1 x i8> %val, <1 x i8*> %ptrs, <1 x i1> %m) {
 ; RV32-LABEL: mscatter_v1i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v1i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8> %val, <1 x i8*> %ptrs, i32 1, <1 x i1> %m)
   ret void
 }
 
 declare void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8>, <2 x i8*>, i32, <2 x i1>)
 
 define void @mscatter_v2i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i16_truncstore_v2i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e8,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vsoxei32.v v25, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i16_truncstore_v2i8:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a0, 2, e8,mf2,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
 ; RV64-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vsoxei64.v v25, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   %tval = trunc <2 x i16> %val to <2 x i8>
   call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i32_truncstore_v2i8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; RV32-NEXT:    vnsrl.wi v26, v25, 0
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vsoxei32.v v26, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i32_truncstore_v2i8:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
-; RV64-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; RV64-NEXT:    vnsrl.wi v26, v25, 0
 ; RV64-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV64-NEXT:    vsoxei64.v v26, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   %tval = trunc <2 x i32> %val to <2 x i8>
   call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i64_truncstore_v2i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
 ; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vnsrl.wi v26, v25, 0
 ; RV32-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v26, 0
-; RV32-NEXT:    vsetivli a0, 2, e8,mf4,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; RV32-NEXT:    vsoxei32.v v25, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i64_truncstore_v2i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT:    ret
   ret void
 }
 
 declare void @llvm.masked.scatter.v1i16.v1p0i16(<1 x i16>, <1 x i16*>, i32, <1 x i1>)
 
 define void @mscatter_v1i16(<1 x i16> %val, <1 x i16*> %ptrs, <1 x i1> %m) {
 ; RV32-LABEL: mscatter_v1i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v1i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v1i16.v1p0i16(<1 x i16> %val, <1 x i16*> %ptrs, i32 2, <1 x i1> %m)
   ret void
 }
 
 declare void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16>, <2 x i16*>, i32, <2 x i1>)
 
 define void @mscatter_v2i16(<2 x i16> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i32_truncstore_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v25, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i32_truncstore_v2i16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vsoxei64.v v25, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   %tval = trunc <2 x i32> %val to <2 x i16>
   call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i64_truncstore_v2i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
 ; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vnsrl.wi v26, v25, 0
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v26, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i64_truncstore_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT:    ret
   ret void
 }
 
 declare void @llvm.masked.scatter.v1i32.v1p0i32(<1 x i32>, <1 x i32*>, i32, <1 x i1>)
 
 define void @mscatter_v1i32(<1 x i32> %val, <1 x i32*> %ptrs, <1 x i1> %m) {
 ; RV32-LABEL: mscatter_v1i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v1i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v1i32.v1p0i32(<1 x i32> %val, <1 x i32*> %ptrs, i32 4, <1 x i1> %m)
   ret void
 }
 
 declare void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32>, <2 x i32*>, i32, <2 x i1>)
 
 define void @mscatter_v2i32(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, i32 4, <2 x i1> %m)
   ret void
 }
 
 define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2i64_truncstore_v2i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vnsrl.wi v25, v8, 0
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v25, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2i64_truncstore_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vnsrl.wi v25, v8, 0
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
; RV64-NEXT:    ret
   ret void
 }
 
 declare void @llvm.masked.scatter.v1f16.v1p0f16(<1 x half>, <1 x half*>, i32, <1 x i1>)
 
 define void @mscatter_v1f16(<1 x half> %val, <1 x half*> %ptrs, <1 x i1> %m) {
 ; RV32-LABEL: mscatter_v1f16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v1f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v1f16.v1p0f16(<1 x half> %val, <1 x half*> %ptrs, i32 2, <1 x i1> %m)
   ret void
 }
 
 declare void @llvm.masked.scatter.v2f16.v2p0f16(<2 x half>, <2 x half*>, i32, <2 x i1>)
 
 define void @mscatter_v2f16(<2 x half> %val, <2 x half*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2f16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e16,mf2,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
; RV64-NEXT:    ret
   ret void
 }
 
 declare void @llvm.masked.scatter.v1f32.v1p0f32(<1 x float>, <1 x float*>, i32, <1 x i1>)
 
 define void @mscatter_v1f32(<1 x float> %val, <1 x float*> %ptrs, <1 x i1> %m) {
 ; RV32-LABEL: mscatter_v1f32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v1f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.masked.scatter.v1f32.v1p0f32(<1 x float> %val, <1 x float*> %ptrs, i32 4, <1 x i1> %m)
   ret void
 }
 
 declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float>, <2 x float*>, i32, <2 x i1>)
 
 define void @mscatter_v2f32(<2 x float> %val, <2 x float*> %ptrs, <2 x i1> %m) {
 ; RV32-LABEL: mscatter_v2f32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_v2f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret

 ; RV64-NEXT:    vsext.vf8 v16, v10
 ; RV64-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 16
 ; RV64-NEXT:    vslidedown.vi v28, v10, 16
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vsext.vf8 v8, v28
-; RV64-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 2, e8,mf4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; RV64-NEXT:    vsoxei64.v v26, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
   call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> %val, <32 x i8*> %ptrs, i32 1, <32 x i1> %m)
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <1 x half>, <1 x half>* %m_ptr
   %mask = fcmp oeq <1 x half> %m, zeroinitializer
   %val = load <1 x half>, <1 x half>* %val_ptr
   call void @llvm.masked.store.v1f16.p0v1f16(<1 x half> %val, <1 x half>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1f16.p0v1f16(<1 x half>, <1 x half>*, i32, <1 x i1>)
 
 define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x float>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a2)
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    fmv.w.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vse32.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <1 x float>, <1 x float>* %m_ptr
   %mask = fcmp oeq <1 x float> %m, zeroinitializer
; RV64-NEXT:    ret
   call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> %val, <1 x double>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32, <1 x i1>)
 
 define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <2 x half>, <2 x half>* %m_ptr
   %mask = fcmp oeq <2 x half> %m, zeroinitializer
   %val = load <2 x half>, <2 x half>* %val_ptr
   call void @llvm.masked.store.v2f16.p0v2f16(<2 x half> %val, <2 x half>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2f16.p0v2f16(<2 x half>, <2 x half>*, i32, <2 x i1>)
 
 define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x float>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a2)
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    fmv.w.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vse32.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <2 x float>, <2 x float>* %m_ptr
   %mask = fcmp oeq <2 x float> %m, zeroinitializer
; RV64-NEXT:    ret
   call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
 
 define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    vmfeq.vf v0, v25, ft0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <4 x half>, <4 x half>* %m_ptr
   %mask = fcmp oeq <4 x half> %m, zeroinitializer

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a2)
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse8.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <1 x i8>, <1 x i8>* %m_ptr
   %mask = icmp eq <1 x i8> %m, zeroinitializer
   %val = load <1 x i8>, <1 x i8>* %val_ptr
   call void @llvm.masked.store.v1i8.p0v1i8(<1 x i8> %val, <1 x i8>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1i8.p0v1i8(<1 x i8>, <1 x i8>*, i32, <1 x i1>)
 
 define void @masked_store_v1i16(<1 x i16>* %val_ptr, <1 x i16>* %a, <1 x i16>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <1 x i16>, <1 x i16>* %m_ptr
   %mask = icmp eq <1 x i16> %m, zeroinitializer
   %val = load <1 x i16>, <1 x i16>* %val_ptr
   call void @llvm.masked.store.v1i16.p0v1i16(<1 x i16> %val, <1 x i16>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1i16.p0v1i16(<1 x i16>, <1 x i16>*, i32, <1 x i1>)
 
 define void @masked_store_v1i32(<1 x i32>* %val_ptr, <1 x i32>* %a, <1 x i32>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a2)
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse32.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <1 x i32>, <1 x i32>* %m_ptr
   %mask = icmp eq <1 x i32> %m, zeroinitializer
   %val = load <1 x i32>, <1 x i32>* %val_ptr
; CHECK-NEXT:    ret
   call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> %val, <1 x i64>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1i64.p0v1i64(<1 x i64>, <1 x i64>*, i32, <1 x i1>)
 
 define void @masked_store_v2i8(<2 x i8>* %val_ptr, <2 x i8>* %a, <2 x i8>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a2)
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse8.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <2 x i8>, <2 x i8>* %m_ptr
   %mask = icmp eq <2 x i8> %m, zeroinitializer
   %val = load <2 x i8>, <2 x i8>* %val_ptr
   call void @llvm.masked.store.v2i8.p0v2i8(<2 x i8> %val, <2 x i8>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2i8.p0v2i8(<2 x i8>, <2 x i8>*, i32, <2 x i1>)
 
 define void @masked_store_v2i16(<2 x i16>* %val_ptr, <2 x i16>* %a, <2 x i16>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <2 x i16>, <2 x i16>* %m_ptr
   %mask = icmp eq <2 x i16> %m, zeroinitializer
   %val = load <2 x i16>, <2 x i16>* %val_ptr
   call void @llvm.masked.store.v2i16.p0v2i16(<2 x i16> %val, <2 x i16>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2i16.p0v2i16(<2 x i16>, <2 x i16>*, i32, <2 x i1>)
 
 define void @masked_store_v2i32(<2 x i32>* %val_ptr, <2 x i32>* %a, <2 x i32>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a2)
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse32.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <2 x i32>, <2 x i32>* %m_ptr
   %mask = icmp eq <2 x i32> %m, zeroinitializer
   %val = load <2 x i32>, <2 x i32>* %val_ptr
; CHECK-NEXT:    ret
   call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %val, <2 x i64>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
 
 define void @masked_store_v4i8(<4 x i8>* %val_ptr, <4 x i8>* %a, <4 x i8>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a2)
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse8.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <4 x i8>, <4 x i8>* %m_ptr
   %mask = icmp eq <4 x i8> %m, zeroinitializer
   %val = load <4 x i8>, <4 x i8>* %val_ptr
   call void @llvm.masked.store.v4i8.p0v4i8(<4 x i8> %val, <4 x i8>* %a, i32 8, <4 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v4i8.p0v4i8(<4 x i8>, <4 x i8>*, i32, <4 x i1>)
 
 define void @masked_store_v4i16(<4 x i16>* %val_ptr, <4 x i16>* %a, <4 x i16>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a2)
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse16.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <4 x i16>, <4 x i16>* %m_ptr
   %mask = icmp eq <4 x i16> %m, zeroinitializer
   %val = load <4 x i16>, <4 x i16>* %val_ptr
; CHECK-NEXT:    ret
   call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %val, <4 x i64>* %a, i32 8, <4 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
 
 define void @masked_store_v8i8(<8 x i8>* %val_ptr, <8 x i8>* %a, <8 x i8>* %m_ptr) nounwind {
 ; CHECK-LABEL: masked_store_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a3, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a3, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a2)
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v25, 0
 ; CHECK-NEXT:    vse8.v v26, (a1), v0.t
 ; CHECK-NEXT:    ret
   %m = load <8 x i8>, <8 x i8>* %m_ptr
   %mask = icmp eq <8 x i8> %m, zeroinitializer
   %val = load <8 x i8>, <8 x i8>* %val_ptr

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128  -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
 
 define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <1 x half>, <1 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x half>, <1 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
 
 define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
 
 define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
; CHECK-NEXT:    ret
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
 
 define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <1 x float>, <1 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x float>, <1 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
 
 define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128  -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8>)
 
 define i8 @vreduce_add_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
 
 define i8 @vreduce_add_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
 
 define i8 @vreduce_add_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
 
 define i8 @vreduce_add_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16>)
 
 define i16 @vreduce_add_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v2i16(<2 x i16>)
 
 define i16 @vreduce_add_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
 
 define i16 @vreduce_add_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32>)
 
 define i32 @vreduce_add_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_add_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
 
 define i32 @vreduce_add_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_add_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)
 
 define i8 @vreduce_and_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)
 
 define i8 @vreduce_and_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
 
 define i8 @vreduce_and_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
 
 define i8 @vreduce_and_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16>)
 
 define i16 @vreduce_and_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v2i16(<2 x i16>)
 
 define i16 @vreduce_and_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
 
 define i16 @vreduce_and_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32>)
 
 define i32 @vreduce_and_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_and_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
 
 define i32 @vreduce_and_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_and_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
 
 define i8 @vreduce_or_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>)
 
 define i8 @vreduce_or_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
 
 define i8 @vreduce_or_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
 
 define i8 @vreduce_or_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v1i16(<1 x i16>)
 
 define i16 @vreduce_or_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v2i16(<2 x i16>)
 
 define i16 @vreduce_or_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
 
 define i16 @vreduce_or_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v1i32(<1 x i32>)
 
 define i32 @vreduce_or_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_or_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
 
 define i32 @vreduce_or_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_or_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)
 
 define i8 @vreduce_xor_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
 
 define i8 @vreduce_xor_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
 
 define i8 @vreduce_xor_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
 
 define i8 @vreduce_xor_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v1i16(<1 x i16>)
 
 define i16 @vreduce_xor_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v2i16(<2 x i16>)
 
 define i16 @vreduce_xor_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
 
 define i16 @vreduce_xor_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v1i32(<1 x i32>)
 
 define i32 @vreduce_xor_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_xor_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
 
 define i32 @vreduce_xor_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_xor_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v1i8(<1 x i8>)
 
 define i8 @vreduce_smin_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
 
 define i8 @vreduce_smin_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
 
 define i8 @vreduce_smin_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
 
 define i8 @vreduce_smin_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v1i16(<1 x i16>)
 
 define i16 @vreduce_smin_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smin_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v2i16(<2 x i16>)
 
 define i16 @vreduce_smin_v2i16(<2 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v2i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
-; RV32-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
+; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v2i16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
-; RV64-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
+; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
 
 define i16 @vreduce_smin_v4i16(<4 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v4i16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
-; RV32-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
+; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v4i16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
-; RV64-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
+; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
; RV64-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v1i32(<1 x i32>)
 
 define i32 @vreduce_smin_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smin_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
 
 define i32 @vreduce_smin_v2i32(<2 x i32>* %x) {
 ; RV32-LABEL: vreduce_smin_v2i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vle32.v v25, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
+; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v2i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vle32.v v25, (a0)
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
-; RV64-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
+; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v1i8(<1 x i8>)
 
 define i8 @vreduce_smax_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)
 
 define i8 @vreduce_smax_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
 
 define i8 @vreduce_smax_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
 
 define i8 @vreduce_smax_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v1i16(<1 x i16>)
 
 define i16 @vreduce_smax_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v2i16(<2 x i16>)
 
 define i16 @vreduce_smax_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
 
 define i16 @vreduce_smax_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v1i32(<1 x i32>)
 
 define i32 @vreduce_smax_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smax_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
 
 define i32 @vreduce_smax_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smax_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v1i8(<1 x i8>)
 
 define i8 @vreduce_umin_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
 
 define i8 @vreduce_umin_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
 
 define i8 @vreduce_umin_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
 
 define i8 @vreduce_umin_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v1i16(<1 x i16>)
 
 define i16 @vreduce_umin_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v2i16(<2 x i16>)
 
 define i16 @vreduce_umin_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
 
 define i16 @vreduce_umin_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v1i32(<1 x i32>)
 
 define i32 @vreduce_umin_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umin_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
 
 define i32 @vreduce_umin_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umin_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
; RV64-NEXT:    ret
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8>)
 
 define i8 @vreduce_umax_v1i8(<1 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i8>, <1 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
 
 define i8 @vreduce_umax_v2i8(<2 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
 
 define i8 @vreduce_umax_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
 
 define i8 @vreduce_umax_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
; CHECK-NEXT:    ret
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16>)
 
 define i16 @vreduce_umax_v1i16(<1 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v1i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i16>, <1 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v2i16(<2 x i16>)
 
 define i16 @vreduce_umax_v2i16(<2 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
 
 define i16 @vreduce_umax_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
; CHECK-NEXT:    ret
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32>)
 
 define i32 @vreduce_umax_v1i32(<1 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umax_v1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x i32>, <1 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
 
 define i32 @vreduce_umax_v2i32(<2 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umax_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 
 declare <2 x i8> @llvm.experimental.stepvector.v2i8()
 
 define <2 x i8> @stepvector_v2i8() {
 ; CHECK-LABEL: stepvector_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
   ret <2 x i8> %v
 }
 
 declare <4 x i8> @llvm.experimental.stepvector.v4i8()
 
 define <4 x i8> @stepvector_v4i8() {
 ; CHECK-LABEL: stepvector_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
   ret <4 x i8> %v
 }
 
 declare <8 x i8> @llvm.experimental.stepvector.v8i8()
 
 define <8 x i8> @stepvector_v8i8() {
 ; CHECK-LABEL: stepvector_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
   ret <8 x i8> %v
 }
 
 declare <16 x i8> @llvm.experimental.stepvector.v16i8()
 
 define <16 x i8> @stepvector_v16i8() {
 ; CHECK-LABEL: stepvector_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <16 x i8> @llvm.experimental.stepvector.v16i8()
   ret <16 x i8> %v
 }
 
 declare <2 x i16> @llvm.experimental.stepvector.v2i16()
 
 define <2 x i16> @stepvector_v2i16() {
 ; CHECK-LABEL: stepvector_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
   ret <2 x i16> %v
 }
 
 declare <4 x i16> @llvm.experimental.stepvector.v4i16()
 
 define <4 x i16> @stepvector_v4i16() {
 ; CHECK-LABEL: stepvector_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
   ret <4 x i16> %v
 }
 
 declare <8 x i16> @llvm.experimental.stepvector.v8i16()
 
; LMULMAX2-NEXT:    ret
   ret <16 x i16> %v
 }
 
 declare <2 x i32> @llvm.experimental.stepvector.v2i32()
 
 define <2 x i32> @stepvector_v2i32() {
 ; CHECK-LABEL: stepvector_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
   ret <2 x i32> %v
 }
 
 declare <4 x i32> @llvm.experimental.stepvector.v4i32()
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 
 declare <2 x i8> @llvm.experimental.stepvector.v2i8()
 
 define <2 x i8> @stepvector_v2i8() {
 ; CHECK-LABEL: stepvector_v2i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
   ret <2 x i8> %v
 }
 
 declare <4 x i8> @llvm.experimental.stepvector.v4i8()
 
 define <4 x i8> @stepvector_v4i8() {
 ; CHECK-LABEL: stepvector_v4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
   ret <4 x i8> %v
 }
 
 declare <8 x i8> @llvm.experimental.stepvector.v8i8()
 
 define <8 x i8> @stepvector_v8i8() {
 ; CHECK-LABEL: stepvector_v8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
   ret <8 x i8> %v
 }
 
 declare <16 x i8> @llvm.experimental.stepvector.v16i8()
 
 define <16 x i8> @stepvector_v16i8() {
 ; CHECK-LABEL: stepvector_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <16 x i8> @llvm.experimental.stepvector.v16i8()
   ret <16 x i8> %v
 }
 
 declare <2 x i16> @llvm.experimental.stepvector.v2i16()
 
 define <2 x i16> @stepvector_v2i16() {
 ; CHECK-LABEL: stepvector_v2i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
   ret <2 x i16> %v
 }
 
 declare <4 x i16> @llvm.experimental.stepvector.v4i16()
 
 define <4 x i16> @stepvector_v4i16() {
 ; CHECK-LABEL: stepvector_v4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
   ret <4 x i16> %v
 }
 
 declare <8 x i16> @llvm.experimental.stepvector.v8i16()
 
; LMULMAX2-NEXT:    ret
   ret <16 x i16> %v
 }
 
 declare <2 x i32> @llvm.experimental.stepvector.v2i32()
 
 define <2 x i32> @stepvector_v2i32() {
 ; CHECK-LABEL: stepvector_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    ret
   %v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
   ret <2 x i32> %v
 }
 
 declare <4 x i32> @llvm.experimental.stepvector.v4i32()
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
 
 define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
 ; CHECK-LABEL: vfmax_v2f16_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
   ret <2 x half> %v
 }
 
 define <2 x half> @vfmax_v2f16_vf(<2 x half> %a, half %b) {
 ; CHECK-LABEL: vfmax_v2f16_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmax.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x half> undef, half %b, i32 0
   %splat = shufflevector <2 x half> %head, <2 x half> undef, <2 x i32> zeroinitializer
   %v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %splat)
   ret <2 x half> %v
 }
 
 declare <4 x half> @llvm.maxnum.v4f16(<4 x half>, <4 x half>)
 
 define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: vfmax_v4f16_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %b)
   ret <4 x half> %v
 }
 
 define <4 x half> @vfmax_v4f16_vf(<4 x half> %a, half %b) {
 ; CHECK-LABEL: vfmax_v4f16_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmax.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <4 x half> undef, half %b, i32 0
   %splat = shufflevector <4 x half> %head, <4 x half> undef, <4 x i32> zeroinitializer
   %v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %splat)
   ret <4 x half> %v
 }
 
; CHECK-NEXT:    ret
   ret <16 x half> %v
 }
 
 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
 
 define <2 x float> @vfmax_v2f32_vv(<2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: vfmax_v2f32_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
   ret <2 x float> %v
 }
 
 define <2 x float> @vfmax_v2f32_vf(<2 x float> %a, float %b) {
 ; CHECK-LABEL: vfmax_v2f32_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmax.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x float> undef, float %b, i32 0
   %splat = shufflevector <2 x float> %head, <2 x float> undef, <2 x i32> zeroinitializer
   %v = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %splat)
   ret <2 x float> %v
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
 
 define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
 ; CHECK-LABEL: vfmin_v2f16_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
   ret <2 x half> %v
 }
 
 define <2 x half> @vfmin_v2f16_vf(<2 x half> %a, half %b) {
 ; CHECK-LABEL: vfmin_v2f16_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmin.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x half> undef, half %b, i32 0
   %splat = shufflevector <2 x half> %head, <2 x half> undef, <2 x i32> zeroinitializer
   %v = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %splat)
   ret <2 x half> %v
 }
 
 declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>)
 
 define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: vfmin_v4f16_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %b)
   ret <4 x half> %v
 }
 
 define <4 x half> @vfmin_v4f16_vf(<4 x half> %a, half %b) {
 ; CHECK-LABEL: vfmin_v4f16_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmin.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <4 x half> undef, half %b, i32 0
   %splat = shufflevector <4 x half> %head, <4 x half> undef, <4 x i32> zeroinitializer
   %v = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %splat)
   ret <4 x half> %v
 }
 
; CHECK-NEXT:    ret
   ret <16 x half> %v
 }
 
 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
 
 define <2 x float> @vfmin_v2f32_vv(<2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: vfmin_v2f32_vv:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %v = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
   ret <2 x float> %v
 }
 
 define <2 x float> @vfmin_v2f32_vf(<2 x float> %a, float %b) {
 ; CHECK-LABEL: vfmin_v2f32_vf:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmin.vf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x float> undef, float %b, i32 0
   %splat = shufflevector <2 x float> %head, <2 x float> undef, <2 x i32> zeroinitializer
   %v = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %splat)
   ret <2 x float> %v
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 
 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_or_v1i1(<1 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
 ; CHECK-LABEL: vreduce_xor_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_and_v1i1(<1 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v1i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_xor_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_xor_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_and_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v2i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v0, v0
 ; CHECK-NEXT:    vpopc.m a0, v25
 ; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_or_v4i1(<4 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_xor_v4i1(<4 x i1> %v) {
 ; CHECK-LABEL: vreduce_xor_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_and_v4i1(<4 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v0, v0
 ; CHECK-NEXT:    vpopc.m a0, v25
 ; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_or_v8i1(<8 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_xor_v8i1(<8 x i1> %v) {
 ; CHECK-LABEL: vreduce_xor_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vpopc.m a0, v0
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_and_v8i1(<8 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v8i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmnand.mm v25, v0, v0
 ; CHECK-NEXT:    vpopc.m a0, v25
 ; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)
   ret i1 %red
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vv_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a4, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a2)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v26, v28, v26, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %va = load <8 x i32>, <8 x i32>* %a
   %vb = load <8 x i32>, <8 x i32>* %b
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vx_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a4, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a1)
-; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a2)
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vxm v26, v26, a0, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %vb = load <8 x i32>, <8 x i32>* %b
   %ahead = insertelement <8 x i32> undef, i32 %a, i32 0
   %va = shufflevector <8 x i32> %ahead, <8 x i32> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vi_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a1)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vim v26, v26, -1, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x i32>, <8 x i32>* %b
   %a = insertelement <8 x i32> undef, i32 -1, i32 0
   %va = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a4, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a2)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vvm v26, v28, v26, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %va = load <8 x float>, <8 x float>* %a
   %vb = load <8 x float>, <8 x float>* %b
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
   store <8 x float> %vsel, <8 x float>* %z
   ret void
 }
 
 define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vx_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a1)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmerge.vfm v26, v26, fa0, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x float>, <8 x float>* %b
   %ahead = insertelement <8 x float> undef, float %a, i32 0
   %va = shufflevector <8 x float> %ahead, <8 x float> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
   store <8 x float> %vsel, <8 x float>* %z
   ret void
 }
 
 define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vfpzero_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v0, (a1)
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vmerge.vim v26, v26, 0, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x float>, <8 x float>* %b
   %a = insertelement <8 x float> undef, float 0.0, i32 0
   %va = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

 ; RV32MV-NEXT:    addi a2, zero, 7
 ; RV32MV-NEXT:    mv a0, s2
 ; RV32MV-NEXT:    mv a1, s3
 ; RV32MV-NEXT:    mv a3, zero
 ; RV32MV-NEXT:    call __moddi3@plt
 ; RV32MV-NEXT:    sw a1, 12(sp)
 ; RV32MV-NEXT:    sw a0, 8(sp)
 ; RV32MV-NEXT:    addi a0, zero, 85
-; RV32MV-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32MV-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; RV32MV-NEXT:    vmv.s.x v0, a0
 ; RV32MV-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV32MV-NEXT:    vmv.v.i v26, 1
 ; RV32MV-NEXT:    vle32.v v28, (sp)
 ; RV32MV-NEXT:    lui a0, %hi(.LCPI3_0)
 ; RV32MV-NEXT:    addi a0, a0, %lo(.LCPI3_0)
 ; RV32MV-NEXT:    vle32.v v30, (a0)
 ; RV32MV-NEXT:    vmerge.vim v26, v26, -1, v0

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32MV-NEXT:    andi a2, a2, 2047
 ; RV32MV-NEXT:    sh a2, 10(sp)
 ; RV32MV-NEXT:    lb a2, 4(a0)
 ; RV32MV-NEXT:    slli a2, a2, 10
 ; RV32MV-NEXT:    srli a1, a1, 22
 ; RV32MV-NEXT:    or a1, a1, a2
 ; RV32MV-NEXT:    andi a1, a1, 2047
 ; RV32MV-NEXT:    sh a1, 12(sp)
-; RV32MV-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32MV-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32MV-NEXT:    addi a1, sp, 8
 ; RV32MV-NEXT:    vle16.v v25, (a1)
 ; RV32MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV32MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV32MV-NEXT:    vle16.v v26, (a1)
 ; RV32MV-NEXT:    vid.v v27
 ; RV32MV-NEXT:    vsub.vv v25, v25, v27
 ; RV32MV-NEXT:    vmul.vv v25, v25, v26

 ; RV32MV-NEXT:    lui a2, %hi(.LCPI4_1)
 ; RV32MV-NEXT:    addi a2, a2, %lo(.LCPI4_1)
 ; RV32MV-NEXT:    vle16.v v29, (a2)
 ; RV32MV-NEXT:    vsrl.vv v25, v25, v28
 ; RV32MV-NEXT:    vor.vv v25, v25, v26
 ; RV32MV-NEXT:    vand.vx v25, v25, a1
 ; RV32MV-NEXT:    vmsltu.vv v0, v29, v25
 ; RV32MV-NEXT:    vmerge.vim v25, v27, -1, v0
-; RV32MV-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; RV32MV-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; RV32MV-NEXT:    vslidedown.vi v26, v25, 2
 ; RV32MV-NEXT:    vmv.x.s a1, v26
 ; RV32MV-NEXT:    srli a2, a1, 10
 ; RV32MV-NEXT:    andi a2, a2, 1
 ; RV32MV-NEXT:    sb a2, 4(a0)
 ; RV32MV-NEXT:    vmv.x.s a2, v25
 ; RV32MV-NEXT:    andi a2, a2, 2047
 ; RV32MV-NEXT:    vslidedown.vi v25, v25, 1

 ; RV64MV-NEXT:    or a1, a2, a1
 ; RV64MV-NEXT:    srli a2, a1, 22
 ; RV64MV-NEXT:    sh a2, 12(sp)
 ; RV64MV-NEXT:    andi a2, a1, 2047
 ; RV64MV-NEXT:    sh a2, 8(sp)
 ; RV64MV-NEXT:    srli a1, a1, 11
 ; RV64MV-NEXT:    andi a1, a1, 2047
 ; RV64MV-NEXT:    sh a1, 10(sp)
-; RV64MV-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV64MV-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV64MV-NEXT:    addi a1, sp, 8
 ; RV64MV-NEXT:    vle16.v v25, (a1)
 ; RV64MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV64MV-NEXT:    vle16.v v26, (a1)
 ; RV64MV-NEXT:    vid.v v27
 ; RV64MV-NEXT:    vsub.vv v25, v25, v27
 ; RV64MV-NEXT:    vmul.vv v25, v25, v26

 ; RV64MV-NEXT:    vle16.v v29, (a2)
 ; RV64MV-NEXT:    vsrl.vv v25, v25, v28
 ; RV64MV-NEXT:    vor.vv v25, v25, v26
 ; RV64MV-NEXT:    vand.vx v25, v25, a1
 ; RV64MV-NEXT:    vmsltu.vv v0, v29, v25
 ; RV64MV-NEXT:    vmerge.vim v25, v27, -1, v0
 ; RV64MV-NEXT:    vmv.x.s a1, v25
 ; RV64MV-NEXT:    andi a1, a1, 2047
-; RV64MV-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
+; RV64MV-NEXT:    vsetivli a2, 1, e16,mf2,ta,mu
 ; RV64MV-NEXT:    vslidedown.vi v26, v25, 1
 ; RV64MV-NEXT:    vmv.x.s a2, v26
 ; RV64MV-NEXT:    andi a2, a2, 2047
 ; RV64MV-NEXT:    slli a2, a2, 11
 ; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    vslidedown.vi v25, v25, 2
 ; RV64MV-NEXT:    vmv.x.s a2, v25
 ; RV64MV-NEXT:    slli a2, a2, 22