[RISCV] Make use of DAG.getNeutralElement in lowerVECREDUCE to avoid repeating the same list of constants. NFC

[khchen]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2424

maybe the function name should be changed because it does not get IdentityVal now?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2424

Oops. Thanks!

[craig.topper]

Rename function

[khchen]

LGTM.

[frasercrmck]

LGTM. Good to know that function exists

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 static MVT getLMUL1VT(MVT VT) {
   assert(VT.getVectorElementType().getSizeInBits() <= 64 &&
          "Unexpected vector MVT");
   return MVT::getScalableVectorVT(
       VT.getVectorElementType(),
       RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits());
 }
 
-static std::pair<unsigned, uint64_t>
-getRVVReductionOpAndIdentityVal(unsigned ISDOpcode, unsigned EltSizeBits) {
+static unsigned getRVVReductionOp(unsigned ISDOpcode) {
   switch (ISDOpcode) {
   default:
     llvm_unreachable("Unhandled reduction");
   case ISD::VECREDUCE_ADD:
-    return {RISCVISD::VECREDUCE_ADD, 0};
+    return RISCVISD::VECREDUCE_ADD;
   case ISD::VECREDUCE_UMAX:
-    return {RISCVISD::VECREDUCE_UMAX, 0};
+    return RISCVISD::VECREDUCE_UMAX;
   case ISD::VECREDUCE_SMAX:
-    return {RISCVISD::VECREDUCE_SMAX, minIntN(EltSizeBits)};
+    return RISCVISD::VECREDUCE_SMAX;
   case ISD::VECREDUCE_UMIN:
-    return {RISCVISD::VECREDUCE_UMIN, maxUIntN(EltSizeBits)};
+    return RISCVISD::VECREDUCE_UMIN;
   case ISD::VECREDUCE_SMIN:
-    return {RISCVISD::VECREDUCE_SMIN, maxIntN(EltSizeBits)};
+    return RISCVISD::VECREDUCE_SMIN;
   case ISD::VECREDUCE_AND:
-    return {RISCVISD::VECREDUCE_AND, -1};
+    return RISCVISD::VECREDUCE_AND;
   case ISD::VECREDUCE_OR:
-    return {RISCVISD::VECREDUCE_OR, 0};
+    return RISCVISD::VECREDUCE_OR;
   case ISD::VECREDUCE_XOR:
-    return {RISCVISD::VECREDUCE_XOR, 0};
+    return RISCVISD::VECREDUCE_XOR;
   }
 }
 
 // Take a (supported) standard ISD reduction opcode and transform it to a RISCV
 // reduction opcode. Note that this returns a vector type, which must be
 // further processed to access the scalar result in element 0.
 SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
   assert(Op.getValueType().isSimple() &&
          Op.getOperand(0).getValueType().isSimple() &&
          "Unexpected vector-reduce lowering");
   MVT VecVT = Op.getOperand(0).getSimpleValueType();
   MVT VecEltVT = VecVT.getVectorElementType();
-  unsigned RVVOpcode;
-  uint64_t IdentityVal;
-  std::tie(RVVOpcode, IdentityVal) =
-      getRVVReductionOpAndIdentityVal(Op.getOpcode(), VecEltVT.getSizeInBits());
+  unsigned RVVOpcode = getRVVReductionOp(Op.getOpcode());
   MVT M1VT = getLMUL1VT(VecVT);
-  SDValue IdentitySplat =
-      DAG.getSplatVector(M1VT, DL, DAG.getConstant(IdentityVal, DL, VecEltVT));
+  SDValue NeutralElem = DAG.getNeutralElement(
+      ISD::getVecReduceBaseOpcode(Op.getOpcode()), DL, VecEltVT, SDNodeFlags());
+  SDValue IdentitySplat = DAG.getSplatVector(M1VT, DL, NeutralElem);
   SDValue Reduction =
       DAG.getNode(RVVOpcode, DL, M1VT, Op.getOperand(0), IdentitySplat);
   SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction,
                              DAG.getConstant(0, DL, Subtarget.getXLenVT()));
   return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());
 }
 
 // Given a reduction op, this function returns the matching reduction opcode,