[RISCV] Don't modify the SEW immediate on the V extension pseudo instructions after inserting VSETVLI.

[craig.topper]

Summary

Previously we set the value to -1, but the SEW information could
be useful for scheduling.

[frasercrmck]

I also don't see the need to scrub the SEW value for no reason. Unless the original authors had something in mind? @rogfer01 or @evandro ?

[rogfer01]

Hi. We did this out of an abundance of caution. We wanted to be sure after the vsetvli were emitted, we didn't attempt to use the SEW operand (either by accident or intentionally).

It never occured to me that scheduling could benefit from that, so I think it is a plus to keep it.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   }
 
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth,
                                      /*TailAgnostic*/ TailAgnostic,
                                      /*MaskAgnostic*/ false));
 
   // Remove (now) redundant operands from pseudo
-  MI.getOperand(SEWIndex).setImm(-1);
   if (VLIndex >= 0) {
     MI.getOperand(VLIndex).setReg(RISCV::NoRegister);
     MI.getOperand(VLIndex).setIsKill(false);
   }
 
   return BB;
 }
 

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir

 
 ...
 
 # POST-INSERTER: %0:gpr = COPY $x13
 # POST-INSERTER: %1:gpr = COPY $x12
 # POST-INSERTER: %2:gpr = COPY $x11
 # POST-INSERTER: %3:gpr = COPY $x10
 # POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+# POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
 # POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
+# POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
 # POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, -1, implicit $vl, implicit $vtype
+# POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, 64, implicit $vl, implicit $vtype
 # POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
+# POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
 
 # CODEGEN: vsetvli  a3, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vle64.v v25, (a1)
 # CODEGEN-NEXT: vle64.v v26, (a2)
 # CODEGEN-NEXT: vadd.vv v25, v25, v26
 # CODEGEN-NEXT: vse64.v v25, (a0)
 # CODEGEN-NEXT: ret

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

 ; PRE-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
 ; PRE-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
 ; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype
 ; PRE-INSERTER:  VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)
 
 ; POST-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
 ; POST-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
 ; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
-; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype
+; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, 64, implicit $vl, implicit $vtype
 ; POST-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)

llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll

 
 define i64 @test(<vscale x 1 x i64> %0) nounwind {
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK:   liveins: $v8
   ; CHECK:   [[COPY:%[0-9]+]]:vr = COPY $v8
   ; CHECK:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
   ; CHECK:   dead %3:gpr = PseudoVSETIVLI 1, 88, implicit-def $vl, implicit-def $vtype
-  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, $noreg, -1, implicit $vl, implicit $vtype
+  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, $noreg, 64, implicit $vl, implicit $vtype
   ; CHECK:   [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load 8 from %ir.a)
   ; CHECK:   $x10 = COPY [[LD]]
   ; CHECK:   PseudoRET implicit $x10
 entry:
   %a = alloca i64
   %b = bitcast i64* %a to <vscale x 1 x i64>*
   call void @llvm.riscv.vse.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %b,
     i64 1)
   %c = load i64, i64* %a
   ret i64 %c
 }