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[RISCV] Add scalable vector truncate patterns
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Authored by frasercrmck on Jan 15 2021, 9:14 AM.

Details

Summary

Original patch by @rogfer01.

This patch supports vector truncates, which on RVV must be done in a
series of instructions truncating by one power-of-two at a time. This is
done through custom-lowering and a custom node to avoid LLVM
re-combining the split TRUNCATE nodes.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Diff Detail

Event Timeline

frasercrmck created this revision.Jan 15 2021, 9:14 AM
frasercrmck requested review of this revision.Jan 15 2021, 9:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 9:14 AM
craig.topper added inline comments.Jan 15 2021, 11:35 AM
llvm/lib/Target/RISCV/RISCVISelLowering.h
88

Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?

craig.topper added inline comments.Jan 15 2021, 12:00 PM
llvm/lib/Target/RISCV/RISCVISelLowering.h
88

Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?

88

Though I guess then you have to use splat vector and deal with type legalization there. So maybe its not worth that complexity yet.

This revision is now accepted and ready to land.Jan 15 2021, 12:01 PM
This revision was landed with ongoing or failed builds.Jan 18 2021, 2:25 AM
This revision was automatically updated to reflect the committed changes.