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Differential D94012

[RISCV] Add vector integer min/max ISel patterns
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Authored by frasercrmck on Jan 4 2021, 3:27 AM.

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Reviewers
craig.topper
evandro
rogfer01
HsiangKai
Commits
rG1d4411e9ea0e: [RISCV] Add vector integer min/max ISel patterns

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frasercrmck created this revision.Jan 4 2021, 3:27 AM
Herald added subscribers: NickHung, luismarques, apazos and 24 others. · View Herald TranscriptJan 4 2021, 3:27 AM
frasercrmck requested review of this revision.Jan 4 2021, 3:27 AM
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Harbormaster completed remote builds in B83884: Diff 314352.Jan 4 2021, 4:03 AM
craig.topper accepted this revision.Jan 4 2021, 3:19 PM

LGTM

This revision is now accepted and ready to land.Jan 4 2021, 3:19 PM
Closed by commit rG1d4411e9ea0e: [RISCV] Add vector integer min/max ISel patterns (authored by frasercrmck). · Explain WhyJan 5 2021, 1:22 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rG1d4411e9ea0e: [RISCV] Add vector integer min/max ISel patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines
6 lines
test/
CodeGen/
RISCV/
rvv/
871 lines
843 lines
871 lines
843 lines
871 lines
843 lines
871 lines
843 lines

Diff 314352

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 356 Lines • ▼ Show 20 Lines if (Subtarget.hasStdExtV()) {
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
if (Subtarget.is64Bit()) { if (Subtarget.is64Bit()) {
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
} }
for (auto VT : MVT::integer_scalable_vector_valuetypes()) for (auto VT : MVT::integer_scalable_vector_valuetypes()) {
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ISD::SMIN, VT, Legal);
setOperationAction(ISD::SMAX, VT, Legal);
setOperationAction(ISD::UMIN, VT, Legal);
setOperationAction(ISD::UMAX, VT, Legal);
}
// We must custom-lower SPLAT_VECTOR vXi64 on RV32 // We must custom-lower SPLAT_VECTOR vXi64 on RV32
if (!Subtarget.is64Bit()) if (!Subtarget.is64Bit())
setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom); setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
} }
// Function alignments. // Function alignments.
const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
setMinFunctionAlignment(FunctionAlignment); setMinFunctionAlignment(FunctionAlignment);
▲ Show 20 Lines • Show All 3,561 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">; defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">; defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
// 12.6. Vector Single-Width Bit Shift Instructions // 12.6. Vector Single-Width Bit Shift Instructions
defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
// 12.9. Vector Integer Min/Max Instructions
defm "" : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
defm "" : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
defm "" : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
defm "" : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vector Splats // Vector Splats
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vmax.vv v16, v16, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vmax.vv v16, v16, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vor.vv v28, v8, v28
; CHECK-NEXT: vmax.vv v16, v16, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmax.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp sgt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmax.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp sgt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vmax_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vmaxu.vv v16, v16, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vmaxu.vv v16, v16, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vor.vv v28, v8, v28
; CHECK-NEXT: vmaxu.vv v16, v16, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmax_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmax_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmax_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmax_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmax_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmax_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmax_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmax_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmax_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmaxu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmax_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmaxu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ugt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmax_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmax_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmaxu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmin_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp slt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp slt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmin_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmin_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmin_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vmin.vv v16, v16, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vmin.vv v16, v16, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vor.vv v28, v8, v28
; CHECK-NEXT: vmin.vv v16, v16, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmin_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp slt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp slt <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmin_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp slt <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmin_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp slt <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmin_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp slt <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp slt <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vmin.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp slt <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmin.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp slt <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vmin.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp slt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmin_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ult <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ult <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmin_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmin_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vmin_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmin_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vminu.vv v16, v16, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vminu.vv v16, v16, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vor.vv v28, v8, v28
; CHECK-NEXT: vminu.vv v16, v16, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vmin_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i8> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 1 x i8> @vmin_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i8> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
ret <vscale x 1 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i8> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 2 x i8> @vmin_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i8> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
ret <vscale x 2 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i8> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 4 x i8> @vmin_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i8> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
ret <vscale x 4 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i8> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 8 x i8> @vmin_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i8> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
ret <vscale x 8 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i8> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 16 x i8> @vmin_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i8> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
ret <vscale x 16 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 32 x i8> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 32 x i8> @vmin_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i8> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
ret <vscale x 32 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vmin_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 64 x i8> %va, %vb
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vmin_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ult <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 64 x i8> @vmin_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vmin_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 -3, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%cmp = icmp ult <vscale x 64 x i8> %va, %splat
%vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
ret <vscale x 64 x i8> %vc
}
define <vscale x 1 x i16> @vmin_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i16> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 1 x i16> @vmin_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i16> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
ret <vscale x 1 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i16> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 2 x i16> @vmin_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i16> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
ret <vscale x 2 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i16> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 4 x i16> @vmin_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i16> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
ret <vscale x 4 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i16> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 8 x i16> @vmin_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i16> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
ret <vscale x 8 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i16> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 16 x i16> @vmin_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i16> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
ret <vscale x 16 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vmin_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 32 x i16> %va, %vb
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vmin_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 32 x i16> @vmin_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vmin_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 -3, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%cmp = icmp ult <vscale x 32 x i16> %va, %splat
%vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
ret <vscale x 32 x i16> %vc
}
define <vscale x 1 x i32> @vmin_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i32> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 1 x i32> @vmin_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i32> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
ret <vscale x 1 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i32> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 2 x i32> @vmin_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i32> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
ret <vscale x 2 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i32> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 4 x i32> @vmin_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i32> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
ret <vscale x 4 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i32> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i32> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
ret <vscale x 8 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vmin_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 16 x i32> %va, %vb
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vmin_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 16 x i32> @vmin_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vmin_vi_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 -3, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%cmp = icmp ult <vscale x 16 x i32> %va, %splat
%vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
ret <vscale x 16 x i32> %vc
}
define <vscale x 1 x i64> @vmin_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v17
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 1 x i64> %va, %vb
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vmin_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%cmp = icmp ult <vscale x 1 x i64> %va, %splat
%vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v18
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 2 x i64> %va, %vb
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vmin_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%cmp = icmp ult <vscale x 2 x i64> %va, %splat
%vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vminu.vv v16, v16, v20
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 4 x i64> %va, %vb
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vmin_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%cmp = icmp ult <vscale x 4 x i64> %va, %splat
%vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmin_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vminu.vv v16, v16, v8
; CHECK-NEXT: ret
%cmp = icmp ult <vscale x 8 x i64> %va, %vb
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vmin_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vmin_vi_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -3
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vminu.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc
}