[RISCV] Fix missing def operand when creating VSETVLI pseudos

[frasercrmck]

Summary

The register operand was not being marked as a def when it should be. No tests
for this in the main branch as there are not yet any pseudos without a
non-negative VLIndex.

Also change the type of a virtual register operand from unsigned to Register
and adjust formatting.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   // VL and VTYPE are alive here.
   MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI));
 
   if (VLIndex >= 0) {
     // Set VL (rs1 != X0).
-    unsigned DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     MIB.addReg(DestReg, RegState::Define | RegState::Dead)
         .addReg(MI.getOperand(VLIndex).getReg());
   } else
     // With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
-    MIB.addReg(RISCV::X0, RegState::Dead)
+    MIB.addReg(RISCV::X0, RegState::Define | RegState::Dead)
         .addReg(RISCV::X0, RegState::Kill);
 
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(Multiplier, ElementWidth,
                                      /*TailAgnostic*/ false,
                                      /*MaskAgnostic*/ false));
 
   // Remove (now) redundant operands from pseudo
   MI.getOperand(SEWIndex).setImm(-1);