[FastISel] Flush local value map on every instruction

[probinson]

Summary

Local values are constants or addresses that can't be folded into
the instruction that uses them. FastISel materializes these in a
"local value" area that always dominates the current insertion
point, to try to avoid materializing these values more than once
(per block).

https://reviews.llvm.org/D43093 added code to sink these local
value instructions to their first use, which has two beneficial
effects. One, it is likely to avoid some unnecessary spills and
reloads; two, it allows us to attach the debug location of the
user to the local value instruction. The latter effect can
improve the debugging experience for debuggers with a "set next
statement" feature, such as the Visual Studio debugger and PS4
debugger, because instructions to set up constants for a given
statement will be associated with the appropriate source line.

There are also some constants (primarily addresses) that could be
produced by no-op casts or GEP instructions; the main difference
from "local value" instructions is that these are values from
separate IR instructions, and therefore could have multiple users
across multiple basic blocks. D43093 avoided sinking these, even
though they were emitted to the same "local value" area as the
other instructions. The patch comment for D43093 states:

Local values may also be used by no-op casts, which adds the
register to the RegFixups table. Without reversing the RegFixups
map direction, we don't have enough information to sink these
instructions.

This patch undoes most of D43093, and instead flushes the local
value map after(*) every IR instruction, using that instruction's
debug location. This avoids sometimes incorrect locations used
previously, and emits instructions in a more natural order.

In addition, constants materialized due to PHI instructions are
not assigned a debug location immediately; instead, when th
local value map is flushed, if the first local value instruction
has no debug location, it is given the same location as the
first non-local-value-map instruction. This prevents PHIs
from introducing unattributed instructions, which would either
be implicitly attributed to the location for the preceding IR
instruction, or given line 0 if they are at the beginning of
a machine basic block. Neither of those consequences is good
for debugging.

This does mean materialized values are not re-used across IR
instruction boundaries; however, only about 5% of those values
were reused in an experimental self-build of clang.

(*) Actually, just prior to the next instruction. It seems like
it would be cleaner the other way, but I was having trouble
getting that to work.

There is additional cleanup to be done after the functional
patch; the SinkLocalValues option can go away, as well as
the LastFlushPoint member. I figured the functional patch
is big enough as it is, and these NFC follow-ups would be easy.
be

[probinson]

Dammit. Visual Studio keeps running clang-format on me. I thought I had that turned off and fixed up the formatting but apparently not. I'll make sure those bits aren't in the next round.

[rnk]

Thanks! It looks like the presubmit/Harbormaster testing found some more test failures that need addressing.

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

223

This dead local value removal logic was part of D43093, right? At least, that's what I remember. Anyway, it's pretty simple, so I agree we should keep it.

llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

5–6

Huh. @MatzeB, do you think this test case can be repaired?

llvm/test/DebugInfo/X86/fission-ranges.ll

44–45

Well there's a fragile test. :(

[probinson]

Some sort of pilot error on that first diff. This should be better.

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

223

Yes, this is modeled on that code. It definitely catches things.

I was trying to use removeDeadLocalValueCode but it caught too much, so I went back to this.

[probinson]

FTR, I plan to remove the -fast-isel-sink-local-instructions option. I think there might be some now-unused fields as well, such as LastFlushPoint, that could be removed. These are NFC follow-ups that can be deferred, this patch is big enough as it is.

[probinson]

In D91734#2403719, @rnk wrote:

Thanks! It looks like the presubmit/Harbormaster testing found some more test failures that need addressing.

AArch64/arm64-fast-isel.ll was due to the pilot error in generating the original diff.
lld/debug-removed-fn.ll, sorry I only ran check-llvm! One address changed, I'll fix that shortly.
The HWAsan one... I don't normally run sanitizers, so I'm not clear on how to do that :) might take a little while to repro.

[probinson]

Fix an lld test and two lldb tests.

[probinson]

I don't reproduce the HWASan failure on my Linux.

[rnk]

I think the code looks good, but I don't want to create an orphaned test case for emergency spill slot creation. Please file a bug about it, reference it from the comments, and go ahead and land it.

I filed a bug about the hwasan test failure, and Evgeniy is looking into it:
https://bugs.llvm.org/show_bug.cgi?id=48274

llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

5–6

Given that Matthias hasn't responded, please file a bug about this, assign it to him, reference it here, and we'll commit it like that.

[dblaikie]

This causes several regressions in the gdb test suite we're running internally - the failures are:

FAIL: gdb.base/break.exp: breakpoint at start of multi line while conditional
FAIL: gdb.base/break.exp: breakpoint info
FAIL: gdb.base/foll-exec.exp: step through execlp call
FAIL: gdb.base/foll-exec.exp: step after execlp call
FAIL: gdb.base/foll-exec.exp: print execd-program/global_i (after execlp)
FAIL: gdb.base/foll-exec.exp: print execd-program/local_j (after execlp)
FAIL: gdb.base/foll-exec.exp: print follow-exec/local_k (after execlp)
FAIL: gdb.base/hbreak2.exp: hardware breakpoint at start of multi line while conditional
FAIL: gdb.base/hbreak2.exp: hardware breakpoint info

I looked into the first one in break.exp and reduced it a bit, given code like this:

int main() { }
int f1(int a, int b) {
  return a && b;
}

debugging this binary with gdb and running b f1 results in breaking on an instruction with no line information after this change, eg:
old behavior:

(gdb) b f1
Breakpoint 1 at 0x40112c: file test.c, line 2.

new behavior:

(gdb) b f1
Breakpoint 1 at 0x40112a

The assembly difference:

-       xorl    %eax, %eax
-                                        # kill: def $al killed $al killed $eax
        movl    %edi, -4(%rbp)
        movl    %esi, -8(%rbp)
 .Ltmp2:
-       .loc    1 3 10 prologue_end             # break.c:3:10
+       .loc    1 0 0 prologue_end              # break.c:0:0
+       xorl    %eax, %eax
+                                        # kill: def $al killed $al killed $eax
+       .loc    1 3 10                          # break.c:3:10
        cmpl    $0, -4(%rbp)
        movb    %al, -9(%rbp)                   # 1-byte Spill

So it looks like the && caused a location-less zero constant to be synthesized and that previously floated up into the prologue - but now it's pulled down past the prologue begin, so after the prologue this location-less zero is the first location.

I've reverted this patch (& dependent/follow-on patches) in 615f63e149f31d6a97b5233b4fe634db92e19aa9 - happy to help with further reproductions/validations (if/when you've got a proposed fix, if you can't run the gdb test suite or otherwise reproduce the failures, I can run our internal infrastructure to validate again)

[rnk]

I see. We should give that constant materialization a location. It looks like it is coming from a phi node. The IR looks like this:

  %6 = icmp ne i32 %5, 0, !dbg !11
  br i1 %6, label %7, label %10, !dbg !12

7:                                                ; preds = %2
  %8 = load i32, i32* %4, align 4, !dbg !13
  %9 = icmp ne i32 %8, 0, !dbg !13
  br label %10

10:                                               ; preds = %7, %2
  %11 = phi i1 [ false, %2 ], [ %9, %7 ], !dbg !14   ;;;; Probably where the zero comes from
  %12 = zext i1 %11 to i32, !dbg !11
  ret i32 %12, !dbg !15

The PHI node has location !14, which is a line 0 location. Is there a reason we give this PHI a line 0 location, when it's built by the frontend for the conditional operator? IMO we should use the location of the br instruction, which will be the location of the conditional operator (&& at the source level).

Paul has already shown that flushing the local value map improves debug info quality in general. If we can't fix all the gdb test suite failures, IMO we should consider XFAILing them and moving on.

[probinson]

The constant materialization (xorl) obviously does not belong in the prologue; I think the instruction ordering with the patch is preferable.
But, clearly we'd rather not have it attributed to line 0, but the line it actually belongs to. I'll start looking into this. Offhand the reduced example appears to be not unreasonably large :-)

We do have a gdb suite of some form running on our downstream compiler, but this patch series hasn't made it there yet. When I put a new patch up I'll tag you @dblaikie and you can try it out on your bot.

[probinson]

@rnk is correct that the phi's source location is propagating to the xorl. I modified the .ll file to put a different line number on the phi, and the xorl picked it up. This is clearly on the front-end to get right.

If we want to get down to cases, there are other poor choices of source location in this tiny example. The statement source is

return a && b;

The 'a' is at column 10, the '&&' at 12, the 'b' at 15.
Now consider the load/test of 'a':

  %0 = load i32, i32* %a.addr, align 4, !dbg !19
  %tobool = icmp ne i32 %0, 0, !dbg !19
  br i1 %tobool, label %land.rhs, label %land.end, !dbg !20
...
!19 = !DILocation(line: 3, column: 10, scope: !12)
!20 = !DILocation(line: 3, column: 12, scope: !12)

The load and icmp both use !19, the source location of 'a' in the expression; the br uses !20, the '&&'. All seems good. Now consider the 'b' part:

  %1 = load i32, i32* %b.addr, align 4, !dbg !21
  %tobool1 = icmp ne i32 %1, 0, !dbg !20
  br label %land.end
...
!20 = !DILocation(line: 3, column: 12, scope: !12)
!21 = !DILocation(line: 3, column: 15, scope: !12)

The load uses !21, 'b', but the icmp points to the '&&', and the br points nowhere. This is at least inconsistent with how the LHS of the expression is handled, and I would argue it's actually wrong.

This gets reflected in the generated code:

	.loc	1 0 0 prologue_end              # gdb-fail.c:0:0
	xorl	%eax, %eax                      ;;;; because of the phi's line-0
                                        # kill: def $al killed $al killed $eax
	.loc	1 3 10                          # gdb-fail.c:3:10
	cmpl	$0, -4(%rbp)                    ;;;; load/compare of 'a' at column 10
	movb	%al, -9(%rbp)                   # 1-byte Spill
	.loc	1 3 12 is_stmt 0                # gdb-fail.c:3:12
	je	.LBB1_2                         ;;;; the je attributed to the &&
# %bb.1:                                # %land.rhs
	cmpl	$0, -8(%rbp)                    ;;;; load/compare of 'b' at column 12 (??) not 15
	setne	%al
	movb	%al, -9(%rbp)                   # 1-byte Spill
.LBB1_2:                                # %land.end
	.loc	1 0 12                          # gdb-fail.c:0:12
	movb	-9(%rbp), %al                   # 1-byte Reload

I'd also be happier if the reload was attributed to the same source location as the following instructions, but that's probably a whole 'nother can of worms.

[probinson]

Just for grins, change the && to || and see what happens...
The xorl becomes a movb $1 (no surprise there). But, that instruction no longer has line-0, instead it becomes part of the prologue.
This tells me that the xorl had an explicit line 0, while the 'movb $1' has no location (a subtle but important difference).

There are also curious differences between the CGExprScalar.cpp methods VisitBinLAnd() and VisitBinLOr(); the former is more attentive to line attributions than the latter, which seems likely to be an oversight dating back a decade or so.

Onward into the breach.

[dblaikie]

In D91734#2426897, @rnk wrote:

I see. We should give that constant materialization a location.

Yeah, likely - if this patch makes constant materialization local to the IR instruction - if there's a reasonable location the IR instruction should have, that seems fair to me.

(a more general fix (that would cover cases where the instruction really has no location) might be to propagate locations from the first instruction in a basic block with a location back up to the start of the basic block - I forget if we've considered/tried that before)

It looks like it is coming from a phi node. The IR looks like this:

  %6 = icmp ne i32 %5, 0, !dbg !11
  br i1 %6, label %7, label %10, !dbg !12

7:                                                ; preds = %2
  %8 = load i32, i32* %4, align 4, !dbg !13
  %9 = icmp ne i32 %8, 0, !dbg !13
  br label %10

10:                                               ; preds = %7, %2
  %11 = phi i1 [ false, %2 ], [ %9, %7 ], !dbg !14   ;;;; Probably where the zero comes from
  %12 = zext i1 %11 to i32, !dbg !11
  ret i32 %12, !dbg !15

The PHI node has location !14, which is a line 0 location. Is there a reason we give this PHI a line 0 location, when it's built by the frontend for the conditional operator? IMO we should use the location of the br instruction, which will be the location of the conditional operator (&& at the source level).

Paul has already shown that flushing the local value map improves debug info quality in general. If we can't fix all the gdb test suite failures, IMO we should consider XFAILing them and moving on.

For sure there's tipping points where one bug is worth another - but generally it's best to avoid that if possible. (& a sliding scale of "can be fixed" - matter of code, complexity, etc - yeah, if the alternative is rewriting big parts of LLVM to avoid regressing one thing to progress here - I'm with you, there's some place where we'd tradeoff some bugs for some other bugs)

In D91734#2429144, @probinson wrote:

Just for grins, change the && to || and see what happens...
The xorl becomes a movb $1 (no surprise there). But, that instruction no longer has line-0, instead it becomes part of the prologue.
This tells me that the xorl had an explicit line 0, while the 'movb $1' has no location (a subtle but important difference).

There are also curious differences between the CGExprScalar.cpp methods VisitBinLAnd() and VisitBinLOr(); the former is more attentive to line attributions than the latter, which seems likely to be an oversight dating back a decade or so.

Onward into the breach.

I did some work years back to try to streamline the location of instructions when code generating expressions in clang. Mostly centered around the creation and use of ApplyDebugLocation scoped type. Which you can see used in various places, but for instance, at the start of CodeGenFunction::EmitLValue(const Expr *E) - the idea being that all instructions related to code generating that expression would have a location the same as the preferred location (the same place clang points to in error messages) of the expression - and any subexpression would get a similar treatment, overriding the outer expression's location in turn.

Let's see what's up with VisitBinLAnd and VisitBinLOr... Ah, you're referring to the use of ApplyDebugLocation around the two EmitBlock calls in VisitBinLAnd that are missing in VisitBinLOr? Yeah, looks like an omission on my part back when - I vaguely remember that whole "unconditional branches shouldn't have locations" thing, but hopefully there's enough info in the commit messages to help explain why it's useful as I don't think I have that much context anymore.

Right you are about line 0 V no location - the phi after the && has line 0, but the phi after the || has no line.

Here's where the line 0 for the Phi is coming from: https://github.com/llvm-mirror/clang/blob/master/lib/CodeGen/CGExprScalar.cpp#L4039 - I was going to blame myself, but seems to have come from here: https://reviews.llvm.org/D47720

This patch might be undoing, awkwardly, the point of my original patch of omitting locations on unconditional jumps... Hmm, nope, that's just about the jumps.

Looks like this Phi creation ( https://github.com/llvm-mirror/clang/blob/master/lib/CodeGen/CGExprScalar.cpp#L4012 ) misses the opportunity to get the location from the expression, because it's not created by the IRBuilder - perhaps it should be, rather than being given an artificial location - we know which expression it's coming from, just as much as we know the instruction for the loads, etc. So maybe that code should be ApplyDebugLocation::CreateArtificial and scope, and instead set the location to the current debug location - probably move it up to where the Phi is being constructed too - I wouldn't've thought there was a need to move it away from that point.

[dblaikie]

Sometihng like this seems plausible to me:

$ git diff
diff --git clang/lib/CodeGen/CGExprScalar.cpp clang/lib/CodeGen/CGExprScalar.cpp
index c906af8a4afa..c85ce46508a6 100644
--- clang/lib/CodeGen/CGExprScalar.cpp
+++ clang/lib/CodeGen/CGExprScalar.cpp
@@ -4187,6 +4187,7 @@ Value *ScalarExprEmitter::VisitBinLAnd(const BinaryOperator *E) {
   // setting up the PHI node in the Cont Block for this.
   llvm::PHINode *PN = llvm::PHINode::Create(llvm::Type::getInt1Ty(VMContext), 2,
                                             "", ContBlock);
+  PN->setDebugLoc(Builder.getCurrentDebugLocation());
   for (llvm::pred_iterator PI = pred_begin(ContBlock), PE = pred_end(ContBlock);
        PI != PE; ++PI)
     PN->addIncoming(llvm::ConstantInt::getFalse(VMContext), *PI);
@@ -4209,12 +4210,6 @@ Value *ScalarExprEmitter::VisitBinLAnd(const BinaryOperator *E) {
   // Insert an entry into the phi node for the edge with the value of RHSCond.
   PN->addIncoming(RHSCond, RHSBlock);

-  // Artificial location to preserve the scope information
-  {
-    auto NL = ApplyDebugLocation::CreateArtificial(CGF);
-    PN->setDebugLoc(Builder.getCurrentDebugLocation());
-  }
-
   // ZExt result to int.
   return Builder.CreateZExtOrBitCast(PN, ResTy, "land.ext");
 }
diff --git clang/test/CodeGen/debug-info-inline-for.c clang/test/CodeGen/debug-info-inline-for.c
index 55066b28a1ff..5d1b1e7fc3bd 100644
--- clang/test/CodeGen/debug-info-inline-for.c
+++ clang/test/CodeGen/debug-info-inline-for.c
@@ -10,4 +10,4 @@ int func(int n) {
 // CHECK: land.end:
 // CHECK-NEXT: {{.*}} = phi i1 {{.*}} !dbg ![[DbgLoc:[0-9]+]]

-// CHECK: ![[DbgLoc]] = !DILocation(line: 0
+// CHECK: ![[DbgLoc]] = !DILocation(line: 6, column: 19

Not sure if it addresses all of the regressions though.

[probinson]

Sometihng like this seems plausible to me:

Yes, I was playing with essentially that exact patch last night. It has no effect on the final assembly on its own, but combined with my patch it does.

(a more general fix (that would cover cases where the instruction really has no location) might be to propagate locations from the first instruction in a basic block with a location back up to the start of the basic block - I forget if we've considered/tried that before)

We have, but that without flushing the map on every instruction, so it caught materialization instructions that didn't actually belong to that IR instruction. The tactic would likely be more reasonable in conjunction with my patch.

[dblaikie]

In D91734#2431247, @probinson wrote:

Sometihng like this seems plausible to me:

Yes, I was playing with essentially that exact patch last night. It has no effect on the final assembly on its own, but combined with my patch it does.

It might have effects on assembly in other test cases, though. Could be worth running it through a self-host or something to see what other changes it causes and whether they're desirable.

(a more general fix (that would cover cases where the instruction really has no location) might be to propagate locations from the first instruction in a basic block with a location back up to the start of the basic block - I forget if we've considered/tried that before)

We have, but that without flushing the map on every instruction, so it caught materialization instructions that didn't actually belong to that IR instruction. The tactic would likely be more reasonable in conjunction with my patch.

(oh, when I was saying that I didn't really think - the materialization in this case wasn't necessarily on a BB boundary - so I guess my suggestion amounts to possibly never using line 0 (unless it's the only location in a whole BB), instead back or forward propagating surrounding locations over any line 0 - and that doesn't sound right when I put it that way)

But yeah, maybe some amount of it could be done around the flushing thing.

(FWIW, about this patch in general, I do worry a bit about this being a debug-info motivated optimization decision (even if that decision is applied uniformly/not just when debug info is enabled) - you mention this might have positive performance features due to smaller register live ranges, but also possibly negative ones rematerializing the same constant (" however, only about 5% of those values
were reused in an experimental self-build of clang.") - do you have performance measurements/benchmarks related to this change? I guess it didn't show up in the perf bot profiles upstream at least)

[probinson]

See D92606 for a front-end patch to improve locations in the IR.
That, plus reapplying this patch, should help out GDB. I haven't had a chance to run the suite myself with both patches applied and I'm basically off tomorrow, so if @dblaikie doesn't have a chance, I'll do that on Monday.

[jingham]

Note, lldb has a bunch of special handling for line 0 code. For instance, when we are pushing a breakpoint past the prologue we will keep pushing it forward over line number 0 lines. Those are compiler generated and in general people don't want to stop there. Similarly, if you are stepping through line 3 and the next line entry after 3 is line 0 we keep stepping till we get to a non-zero line.

When the compiler is actually using line 0 to mean "compiler generated code not really associated with a particular line, then I am pretty sure the debugger has to be aware of this or debugging is going to be a bit awkward...

I don't know if that's directly relevant to this bug, I haven't had time to follow the whole discussion. But I'm not convinced all the problems with line 0 emission causing debugging oddities can be solved in the line table generation.

Jim

[dblaikie]

In D91734#2432188, @probinson wrote:

See D92606 for a front-end patch to improve locations in the IR.
That, plus reapplying this patch, should help out GDB. I haven't had a chance to run the suite myself with both patches applied and I'm basically off tomorrow, so if @dblaikie doesn't have a chance, I'll do that on Monday.

Had a go - certainly creates a better debugging experience, but still fails the gdb test in question.

The code in the original test looks something like:

int multi_line_while_conditional (int a, int b, int c)
{
  while (a /* set breakpoint 4 here */
      && b 
      && c) 
    { 
      a--, b--, c--;
    }
  return 0;
}

And with these changes together, breaking on the function breaks on line 5 (presumably because this is creating the constant used by the second '&&' which is on line 5) instead of line 3. Not the worst thing, but I imagine given Sony's interest in less "jumpy" line tables, this might not be super desirable.

Yeah, the gdb experience is less than ideal:

13        multi_line_while_conditional(1, 1, 1);
(gdb) s
multi_line_while_conditional (a=1, b=1, c=1) at test.cpp:5
5             && c) 
(gdb) n
3         while (a /* set breakpoint 4 here */
(gdb) 
4             && b 
(gdb) 
5             && c) 
(gdb) 
4             && b 
(gdb) 
5             && c) 
(gdb) 
3         while (a /* set breakpoint 4 here */
(gdb) 
7             a--, b--, c--;

Compared with (without any of these patches):

13        multi_line_while_conditional(1, 1, 1);
(gdb) s
multi_line_while_conditional (a=1, b=1, c=1) at test.cpp:3
3         while (a /* set breakpoint 4 here */
(gdb) n
4             && b 
(gdb) 
5             && c) 
(gdb) 
3         while (a /* set breakpoint 4 here */
(gdb) 
7             a--, b--, c--;

And because I was curious about /exactly/ which tokens the debugger was stepping to, I split out the tokens onto their own lines:
With patch:

18        multi_line_while_conditional(1, 1, 1);
(gdb) s
multi_line_while_conditional (a=1, b=1, c=1) at test.cpp:8
8             && 
(gdb) n
5               a 
(gdb) 
6             && 
(gdb) 
8             && 
(gdb) 
7             b 
(gdb) 
8             && 
(gdb) 
9             c
(gdb) 
3         while 
(gdb) 
12            a--, b--, c--;

Without patch/with trunk:

18        multi_line_while_conditional(1, 1, 1);
(gdb) s
multi_line_while_conditional (a=1, b=1, c=1) at test.cpp:5
5               a 
(gdb) n
6             && 
(gdb) 
7             b 
(gdb) 
8             && 
(gdb) 
9             c
(gdb) 
3         while 
(gdb) 
12            a--, b--, c--;

Maybe it's OK? But at least it's 'interesting' enough that might deserve some extra scrutiny.

[dblaikie]

Also, FWIW, the other gdb test suite failures we saw were:

FAIL: gdb.base/foll-exec.exp: step through execlp call
FAIL: gdb.base/foll-exec.exp: step after execlp call
FAIL: gdb.base/foll-exec.exp: print execd-program/global_i (after execlp)
FAIL: gdb.base/foll-exec.exp: print execd-program/local_j (after execlp)
FAIL: gdb.base/foll-exec.exp: print follow-exec/local_k (after execlp)
FAIL: gdb.base/hbreak2.exp: hardware breakpoint at start of multi line while conditional 
FAIL: gdb.base/hbreak2.exp: hardware breakpoint info

Those last two are different versions of this original issue seen in break.exp/c with multi-line conditionals.

The foll-exec.exp ones I'm less sure of - Looks like maybe it's a similar line table attribution sort of thing, but it leads the test case not to step across the intended process boundary/exec call and things go weird from there.

Yeah, it boils down to something like this:

void f1(const char*, const char*) { }
int main() {
  char prog[1];

  f1(prog,
     prog);
}

Without the patch, you step to the 'f1' line, and then step into or over the function call (step or next).
But with these patches applied - you step to the 'f1(' line, then the 'prog);' line, then back to the 'f1(' line, then into/over the function call.

Again, could be acceptable - if those arguments had specific non-trivial code in them (like other function calls) you'd certainly get that step forward/backward behavior - but it's notewhorthy that this is change would make more cases like that & it'd be good to understand why/if that's a good thing overall.

[probinson]

And with these changes together, breaking on the function breaks on line 5 (presumably because this is creating the constant used by the second '&&' which is on line 5) instead of line 3. Not the worst thing, but I imagine given Sony's interest in less "jumpy" line tables, this might not be super desirable.

It's breaking on an xorl %eax,%eax which is produced by the PHI at the end of the conditional expression, which now has the source location of the operator at the top of the expression tree, which is the second && operator, yeah. Not the best. (FTR, the jumpiness complaints we get are usually more egregious, hopping between different source statements somewhat arbitrarily; not sure anyone would complain too loudly about hopping around within an expression. We see less of that in any case, because we suppress column info, but still.)

The real bear here is getting that constant to behave reasonably. In all cases the sequence of instructions is the same, but silly things keep happening to the line table. (As an aside, GCC does this entire thing with control-flow, not trying to compute and then test the bool result of the expression. They also handle a-- better. But I digress.)

Current HEAD puts the xor in the prologue (which also puts the while-loop top *before* prologue_end, that can't be right). Adding the PHI change doesn't affect this, because FastISel is still materializing the zero in the local value map, which (in HEAD) has no source locations.

.LBB0_1:                                # %while.cond
	xorl	%eax, %eax
.Ltmp0:
	.loc	1 3 10 prologue_end             # multi-line-while.c:3:10
	cmpl	$0, -4(%rbp)

With just my FastISel change (D91734), prologue_end is better, but the xor has line-0, which makes gdb sad (it decides the entire function has no source locations, which is wrong, but whatever):

.LBB0_1:                                # %while.cond
.Ltmp0:
	.loc	1 0 0 prologue_end              # multi-line-while.c:0:0
	xorl	%eax, %eax
	.loc	1 3 10                          # multi-line-while.c:3:10
	cmpl	$0, -4(%rbp)

With the PHI change from D92606, plus D91734, we see the PHI taking effect, which means we first break on line 5 and then hop backwards:

.LBB0_1:                                # %while.cond
.Ltmp0:
	.loc	1 5 10 prologue_end             # multi-line-while.c:5:10
	xorl	%eax, %eax
	.loc	1 3 10                          # multi-line-while.c:3:10
	cmpl	$0, -4(%rbp)

I think we'd prefer something more like this:

.LBB0_1:                                # %while.cond
.Ltmp0:
	.loc	1 3 10 prologue_end             # multi-line-while.c:3:10
	xorl	%eax, %eax
	cmpl	$0, -4(%rbp)

Getting that to happen means not making the PHI change, and persuading FastISel to do something more intelligent. Flushing on every instruction did seem to help, maybe if we made sure that first instruction also had the source location of the first "real" instruction? I will experiment with this tomorrow.

[probinson]

In D91734#2432988, @dblaikie wrote:

Yeah, it boils down to something like this:

void f1(const char*, const char*) { }
int main() {
  char prog[1];

  f1(prog,
     prog);
}

Without the patch, you step to the 'f1' line, and then step into or over the function call (step or next).
But with these patches applied - you step to the 'f1(' line, then the 'prog);' line, then back to the 'f1(' line, then into/over the function call.

Again, could be acceptable - if those arguments had specific non-trivial code in them (like other function calls) you'd certainly get that step forward/backward behavior - but it's notewhorthy that this is change would make more cases like that & it'd be good to understand why/if that's a good thing overall.

If you dump the IR you should see two GEP instructions, one for each actual parameter expression. Prior to the patch, FastISel found the second one computed the same value as the first one, and reused the value (in this case, the result of lea). This is one of the 5% of cases where a value is being reused across instructions, with the HEAD compiler. After the patch, we flush the local map after each GEP, so the second one gets its own separate lea (with its own source location). So, you're stepping to the first actual, then to the second, then to the call. Hope that answers the "why" question.

Whether it's a "good" thing... that path is fraught with peril. Looking at it somewhat abstractly (as I am sometimes wont to do), Clang is making choices to associate the source location of each parameter with the IR instructions to compute that parameter, and by flushing the map on every IR instruction, LLVM is more faithfully representing that in the final object. This is -O0 after all, where a more faithful representation is more likely to be more debuggable. gcc is making entirely different choices, lumping all parameter-prep instructions in with the function call itself. I'm hard pressed to say one is better than the other; they are different. Coke and Pepsi; people may have preferences, but that's not the same as being higher on a good-ness scale.

[dblaikie]

In D91734#2443231, @probinson wrote:

In D91734#2432988, @dblaikie wrote:

Yeah, it boils down to something like this:

void f1(const char*, const char*) { }
int main() {
  char prog[1];

  f1(prog,
     prog);
}

Without the patch, you step to the 'f1' line, and then step into or over the function call (step or next).
But with these patches applied - you step to the 'f1(' line, then the 'prog);' line, then back to the 'f1(' line, then into/over the function call.

Again, could be acceptable - if those arguments had specific non-trivial code in them (like other function calls) you'd certainly get that step forward/backward behavior - but it's notewhorthy that this is change would make more cases like that & it'd be good to understand why/if that's a good thing overall.

If you dump the IR you should see two GEP instructions, one for each actual parameter expression. Prior to the patch, FastISel found the second one computed the same value as the first one, and reused the value (in this case, the result of lea). This is one of the 5% of cases where a value is being reused across instructions, with the HEAD compiler. After the patch, we flush the local map after each GEP, so the second one gets its own separate lea (with its own source location). So, you're stepping to the first actual, then to the second, then to the call. Hope that answers the "why" question.

Whether it's a "good" thing... that path is fraught with peril. Looking at it somewhat abstractly (as I am sometimes wont to do), Clang is making choices to associate the source location of each parameter with the IR instructions to compute that parameter, and by flushing the map on every IR instruction, LLVM is more faithfully representing that in the final object. This is -O0 after all, where a more faithful representation is more likely to be more debuggable. gcc is making entirely different choices, lumping all parameter-prep instructions in with the function call itself. I'm hard pressed to say one is better than the other; they are different. Coke and Pepsi; people may have preferences, but that's not the same as being higher on a good-ness scale.

Fair enough - if you're satisfied these are reasonable cases of different-but-reasonable DWARF locations for the instructions, I'm OK with it.

If possible, would be good if you could run the gdb test suite and document the "regressions" (and possibly document test case changes you'd make to keep those tests passing) with this change - if you're liable to do that sooner or later anyway for your own test infrastructure. Otherwise I'll just handle it on our end.

[probinson]

Reopening, will upload a new diff in a moment that modifies how PHIs are handled. I intend to run the gdb suite on this, will post findings when I have them.

[probinson]

Rebase and combine cf1cc774d and dc35368c, plus revise handling constants materialized due to PHIs.
I plan to do some build-time and object size measurements, similar to the first time around.
I plan to run this against the gdb test suite, or at least the local copy we have here at Sony, and post my findings.

I'm remembering that in a number of the tests, I had to add improvements to the use of -LABEL so I could track down the issues. Those improvements should probably be factored out into a separate NFC commit as they're not strictly part of this change. I'll get to that later (but obviously before committing this).

[probinson]

This is still showing as approved; I'm going to try "Request Review" to see if that helps.

[probinson]

I've run this through our copy of the GDB suite (8.3, not sure how old that is). There are 10 differences, with and without the patch.

FAIL: gdb.base/foll-exec.exp: step through execlp call
FAIL: gdb.base/foll-exec.exp: step after execlp call
FAIL: gdb.base/foll-exec.exp: print execd-program/global_i (after execlp)
FAIL: gdb.base/foll-exec.exp: print execd-program/local_j (after execlp)
FAIL: gdb.base/foll-exec.exp: print follow-exec/local_k (after execlp)

These 5 are all adjacent test points; what happens is that a "next" ends up stepping through parameter evaluation of a call to execl(), where the test expects it to execute the call. Adding two more "next" commands should fix that.

FAIL: gdb.base/call-ar-st.exp: check args of sum_array_print
FAIL: gdb.base/funcargs.exp: continue to call2i
FAIL: gdb.base/funcargs.exp: backtrace from call7k (pattern 1)

These three are all cases where a function parameter list is long enough to require parameters to be passed on the stack. In that situation, prologue_end is being set *way* too early, and so breaking on the function will stop before the parameters have all been homed. Garbage ensues. Haven't gotten to the bottom of that yet.

The news is not all bad. These two changed to PASS:

UNTESTED: gdb.base/break-caller-line.exp: target arch has an instruction after call as part of the caller line
FAIL: gdb.python/python.exp: test find_pc_line with resume address

[probinson]

Change how PHIs are handled; if the operand has a debug location, use it, otherwise don't set a debug location. Then, flushLocalValueMap() will look at the first local-value instruction; if it doesn't already have a debug location, we copy the location from the first instruction after the local-value instructions (which should have the debug location of the original IR instruction).

[probinson]

This version of the patch avoids the weirdness I was seeing with prolog instructions in certain cases.

The gdb test suite is largely happy with this; it avoids the new failures I mentioned previously, and one test needed to have some "next" commands updated. Here's the gdb test suite patch (against 8.3; I can provide more context if it's not clear how to apply to later versions).

diff --git a/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp b/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
index 3e0653a1..61ee752f 100644
--- a/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
+++ b/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
@@ -115,7 +115,10 @@ proc do_exec_tests {} {
    # We should stop in execd-program, at its first statement.
    #
    set execd_line [gdb_get_line_number "after-exec" $srcfile2]
-   send_gdb "next\n"
+    # Clang will emit source locations for the parameter evaluation.
+    # Ideally we'd "next" until we saw 'execlp' again in the source display,
+    # then do one more.
+   send_gdb "next 3\n"
    gdb_expect {
      -re ".*xecuting new program: .*${testfile2}.*${srcfile2}:${execd_line}.*int  local_j = argc;.*$gdb_prompt $"\
                      {pass "step through execlp call"}
@@ -263,7 +266,7 @@ proc do_exec_tests {} {
    # the newly-exec'd program, not after the remaining step-count
    # reaches zero.
    #
-   send_gdb "next 2\n"
+   send_gdb "next 3\n"
    gdb_expect {
      -re ".*xecuting new program: .*${testfile2}.*${srcfile2}:${execd_line}.*int  local_j = argc;.*$gdb_prompt $"\
                      {pass "step through execl call"}

I think I might want to add one more lit test, because the LLVM suite didn't catch a thinko that was the root cause of that last prolog weirdness. But this version is totally ready for review.

[dblaikie]

In D91734#2480474, @probinson wrote:

This version of the patch avoids the weirdness I was seeing with prolog instructions in certain cases.

The gdb test suite is largely happy with this; it avoids the new failures I mentioned previously, and one test needed to have some "next" commands updated. Here's the gdb test suite patch (against 8.3; I can provide more context if it's not clear how to apply to later versions).

diff --git a/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp b/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
index 3e0653a1..61ee752f 100644
--- a/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
+++ b/gdb-8.3/gdb/testsuite/gdb.base/foll-exec.exp
@@ -115,7 +115,10 @@ proc do_exec_tests {} {
    # We should stop in execd-program, at its first statement.
    #
    set execd_line [gdb_get_line_number "after-exec" $srcfile2]
-   send_gdb "next\n"
+    # Clang will emit source locations for the parameter evaluation.
+    # Ideally we'd "next" until we saw 'execlp' again in the source display,
+    # then do one more.
+   send_gdb "next 3\n"
    gdb_expect {
      -re ".*xecuting new program: .*${testfile2}.*${srcfile2}:${execd_line}.*int  local_j = argc;.*$gdb_prompt $"\
                      {pass "step through execlp call"}
@@ -263,7 +266,7 @@ proc do_exec_tests {} {
    # the newly-exec'd program, not after the remaining step-count
    # reaches zero.
    #
-   send_gdb "next 2\n"
+   send_gdb "next 3\n"
    gdb_expect {
      -re ".*xecuting new program: .*${testfile2}.*${srcfile2}:${execd_line}.*int  local_j = argc;.*$gdb_prompt $"\
                      {pass "step through execl call"}

I think I might want to add one more lit test, because the LLVM suite didn't catch a thinko that was the root cause of that last prolog weirdness. But this version is totally ready for review.

Thanks - that seems to cover Google's internal gdb test execution as well. Appreciate the test patch!

I haven't looked closely, but I take it this one test modification seems reasonable to you? I guess we're stepping into some subexpressions on a function call that we previously didn't? (they didn't have any instructions attributed to them until now, but it's not unreasonable that they have them attributed - for materializing constants to pass to a function call when the function call/constants are split over multiple lines, etc)

[probinson]

In D91734#2480930, @dblaikie wrote:

I haven't looked closely, but I take it this one test modification seems reasonable to you? I guess we're stepping into some subexpressions on a function call that we previously didn't? (they didn't have any instructions attributed to them until now, but it's not unreasonable that they have them attributed - for materializing constants to pass to a function call when the function call/constants are split over multiple lines, etc)

Exactly. In each case, the test is trying to "next" over a function call; gcc attributes all parameter evaluation to the function name, while clang will attribute each parameter to its own location. And when the parameters span multiple source lines, the is_stmt heuristic kicks in, so we stop on each line with actual parameters.

This is not ideal IMO; I'd rather be more principled about (a) stop at every parameter, or (b) stop at no parameters. But without reworking how we do is_stmt, I think fiddling the test to do enough single-steps to actually get past the function call is okay.

[dblaikie]

In D91734#2482280, @probinson wrote:

In D91734#2480930, @dblaikie wrote:

I haven't looked closely, but I take it this one test modification seems reasonable to you? I guess we're stepping into some subexpressions on a function call that we previously didn't? (they didn't have any instructions attributed to them until now, but it's not unreasonable that they have them attributed - for materializing constants to pass to a function call when the function call/constants are split over multiple lines, etc)

Exactly. In each case, the test is trying to "next" over a function call; gcc attributes all parameter evaluation to the function name, while clang will attribute each parameter to its own location. And when the parameters span multiple source lines, the is_stmt heuristic kicks in, so we stop on each line with actual parameters.

This is not ideal IMO; I'd rather be more principled about (a) stop at every parameter, or (b) stop at no parameters. But without reworking how we do is_stmt, I think fiddling the test to do enough single-steps to actually get past the function call is okay.

I get that it's a bit unreliable for the user - though GCC's approach isn't so different. If any of the parameter evaluations are themselves function calls, I think it does still multistep as well.

Actually, it seems it does not. Somewhere back around GCC 6 it did what we're doing, but since about 8 at least, no matter what the expressions (at least I tested for + and function call) it attributes all the instructions to the function call line - even the backtrace is misleading - I don't think it's better, just different.

But, yes, we could possibly do better with more strategic is_stmt, but that's a big/complex piece of work to tackle.

[probinson]

In D91734#2482318, @dblaikie wrote:

But, yes, we could possibly do better with more strategic is_stmt, but that's a big/complex piece of work to tackle.

Oh, absolutely. Didn't mean to imply otherwise. And the behavior now is at least easily explainable in terms of source line.

Thanks for the review, this has been an irritant for our licensees since forever. And especially thanks @rnk for the flush-on-every-instruction suggestion.

lld/test/wasm/debug-removed-fn.ll

 ; RUN: llc -filetype=obj < %s -o %t.o
 ; RUN: wasm-ld %t.o --no-entry --export=foo -o %t.wasm
 ; RUN: llvm-dwarfdump -debug-line -debug-ranges %t.wasm | FileCheck %s
 
 ; CHECK: Address
-; CHECK: 0x0000000000000005
+; CHECK: 0x0000000000000003
 ; CHECK-NEXT: 0x0000000000000006
 ; CHECK-EMPTY:
 
 ; CHECK: .debug_ranges contents:
 ; CHECK: 00000000 {{[0-9]+}} {{[0-9]+}}
 ; CHECK: 00000000 fffffffe fffffffe
 ; CHECK: 00000000 <End of list>
 

lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp

 // CHECK-NEXT: ** 14   int main(int argc, char **argv) {
 // CHECK:      disassembly.cpp.tmp.exe`main:
 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+0>:  sub    rsp, 0x38
 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+4>:  mov    dword ptr [rsp + 0x34], 0x0
 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+12>: mov    qword ptr [rsp + 0x28], rdx
 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+17>: mov    dword ptr [rsp + 0x24], ecx
 // CHECK:      ** 15     foo();
 // CHECK:      disassembly.cpp.tmp.exe[{{.*}}] <+21>: call   {{.*}}               ; foo at disassembly.cpp:12
-// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor    eax, eax
 // CHECK:      ** 16     return 0;
 // CHECK-NEXT:    17   }
 // CHECK-NEXT:    18
-// CHECK:      disassembly.cpp.tmp.exe[{{.*}}] <+28>: add    rsp, 0x38
+// CHECK:      disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor    eax, eax
+// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+28>: add    rsp, 0x38
 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+32>: ret

lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp

 
 int main(int argc, char** argv) {
   return 0;
 }
 
 // CHECK: (lldb) target symbols add {{.*}}bar.pdb
 // CHECK: symbol file '{{.*}}bar.pdb' has been added to '{{.*}}foo.exe'
 // CHECK: (lldb) b main
-// CHECK: Breakpoint 1: where = foo.exe`main + 23 at load-pdb.cpp:19, address = 0x0000000140001017
+// CHECK: Breakpoint 1: where = foo.exe`main + 21 at load-pdb.cpp:19, address = 0x0000000140001015
 // CHECK: (lldb) image dump symfile
 // CHECK: Types:
 // CHECK: {{.*}}: Type{0x00010024} , size = 0, compiler_type = {{.*}} int (int, char **)
 // CHECK: Compile units:
 // CHECK: {{.*}}: CompileUnit{0x00000000}, language = "c++", file = '{{.*}}load-pdb.cpp'
 // CHECK: {{.*}}:   Function{{{.*}}}, demangled = main, type = {{.*}}
 // CHECK: {{.*}}:   Block{{{.*}}}

llvm/include/llvm/CodeGen/FastISel.h

void setLastLocalValue(MachineInstr *I) {
     EmitStartPt = I;
     LastLocalValue = I;
   }
 
   /// Set the current block to which generated machine instructions will
   /// be appended.
   void startNewBlock();
 
-  /// Flush the local value map and sink local values if possible.
+  /// Flush the local value map.
   void finishBasicBlock();
 
   /// Return current debug location information.
   DebugLoc getCurDebugLoc() const { return DbgLoc; }
 
   /// Do "fast" instruction selection for function arguments and append
   /// the machine instructions to the current block. Returns true when
   /// successful.
public:
   /// Reset InsertPt to prepare for inserting instructions into the
   /// current block.
   void recomputeInsertPt();
 
   /// Remove all dead instructions between the I and E.
   void removeDeadCode(MachineBasicBlock::iterator I,
                       MachineBasicBlock::iterator E);
 
-  struct SavePoint {
-    MachineBasicBlock::iterator InsertPt;
-    DebugLoc DL;
-  };
+  using SavePoint = MachineBasicBlock::iterator;
 
   /// Prepare InsertPt to begin inserting instructions into the local
   /// value area and return the old insert position.
   SavePoint enterLocalValueArea();
 
   /// Reset InsertPt to the given old insert position.
   void leaveLocalValueArea(SavePoint Old);
 
private:
   /// Clears LocalValueMap and moves the area for the new local variables
   /// to the beginning of the block. It helps to avoid spilling cached variables
   /// across heavy instructions like calls.
   void flushLocalValueMap();
 
   /// Removes dead local value instructions after SavedLastLocalvalue.
   void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
 
-  struct InstOrderMap {
-    DenseMap<MachineInstr *, unsigned> Orders;
-    MachineInstr *FirstTerminator = nullptr;
-    unsigned FirstTerminatorOrder = std::numeric_limits<unsigned>::max();
-
-    void initialize(MachineBasicBlock *MBB,
-                    MachineBasicBlock::iterator LastFlushPoint);
-  };
-
-  /// Sinks the local value materialization instruction LocalMI to its first use
-  /// in the basic block, or deletes it if it is not used.
-  void sinkLocalValueMaterialization(MachineInstr &LocalMI, Register DefReg,
-                                     InstOrderMap &OrderMap);
-
   /// Insertion point before trying to select the current instruction.
   MachineBasicBlock::iterator SavedInsertPt;
 
   /// Add a stackmap or patchpoint intrinsic call's live variable
   /// operands to a stackmap or patchpoint machine instruction.
   bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
                            const CallInst *CI, unsigned StartIdx);
   bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
                          const Value *Callee, bool ForceRetVoidTy,
                          CallLoweringInfo &CLI);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_FASTISEL_H

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

void FastISel::startNewBlock() {
   // contains labels or copies, use the last instruction as the last local
   // value.
   EmitStartPt = nullptr;
   if (!FuncInfo.MBB->empty())
     EmitStartPt = &FuncInfo.MBB->back();
   LastLocalValue = EmitStartPt;
 }
 
-/// Flush the local CSE map and sink anything we can.
 void FastISel::finishBasicBlock() { flushLocalValueMap(); }
 
 bool FastISel::lowerArguments() {
   if (!FuncInfo.CanLowerReturn)
     // Fallback to SDISel argument lowering code to deal with sret pointer
     // parameter.
     return false;
 
   if (!fastLowerArguments())
     return false;
 
   // Enter arguments into ValueMap for uses in non-entry BBs.
   for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
                                     E = FuncInfo.Fn->arg_end();
        I != E; ++I) {
     DenseMap<const Value *, Register>::iterator VI = LocalValueMap.find(&*I);
     assert(VI != LocalValueMap.end() && "Missed an argument?");
     FuncInfo.ValueMap[&*I] = VI->second;
   }
   return true;
 }
 
 /// Return the defined register if this instruction defines exactly one
 /// virtual register and uses no other virtual registers. Otherwise return 0.
-static Register findSinkableLocalRegDef(MachineInstr &MI) {
+static Register findLocalRegDef(MachineInstr &MI) {
   Register RegDef;
   for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg())
       continue;
     if (MO.isDef()) {
       if (RegDef)
-        return 0;
+        return Register();
       RegDef = MO.getReg();
     } else if (MO.getReg().isVirtual()) {
-      // This is another use of a vreg. Don't try to sink it.
+      // This is another use of a vreg. Don't delete it.
       return Register();
     }
   }
   return RegDef;
 }
 
-void FastISel::flushLocalValueMap() {
-  // Try to sink local values down to their first use so that we can give them a
-  // better debug location. This has the side effect of shrinking local value
-  // live ranges, which helps out fast regalloc.
-  if (SinkLocalValues && LastLocalValue != EmitStartPt) {
-    // Sink local value materialization instructions between EmitStartPt and
-    // LastLocalValue. Visit them bottom-up, starting from LastLocalValue, to
-    // avoid inserting into the range that we're iterating over.
-    MachineBasicBlock::reverse_iterator RE =
-        EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
-                    : FuncInfo.MBB->rend();
-    MachineBasicBlock::reverse_iterator RI(LastLocalValue);
-
-    InstOrderMap OrderMap;
-    for (; RI != RE;) {
-      MachineInstr &LocalMI = *RI;
-      ++RI;
-      bool Store = true;
-      if (!LocalMI.isSafeToMove(nullptr, Store))
-        continue;
-      Register DefReg = findSinkableLocalRegDef(LocalMI);
-      if (DefReg == 0)
-        continue;
-
-      sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap);
-    }
-  }
-
-  LocalValueMap.clear();
-  LastLocalValue = EmitStartPt;
-  recomputeInsertPt();
-  SavedInsertPt = FuncInfo.InsertPt;
-  LastFlushPoint = FuncInfo.InsertPt;
-}
-
 static bool isRegUsedByPhiNodes(Register DefReg,
                                 FunctionLoweringInfo &FuncInfo) {
   for (auto &P : FuncInfo.PHINodesToUpdate)
     if (P.second == DefReg)
       return true;
   return false;
 }
 
-static bool isTerminatingEHLabel(MachineBasicBlock *MBB, MachineInstr &MI) {
-  // Ignore non-EH labels.
-  if (!MI.isEHLabel())
-    return false;
-
-  // Any EH label outside a landing pad must be for an invoke. Consider it a
-  // terminator.
-  if (!MBB->isEHPad())
-    return true;
-
-  // If this is a landingpad, the first non-phi instruction will be an EH_LABEL.
-  // Don't consider that label to be a terminator.
-  return MI.getIterator() != MBB->getFirstNonPHI();
-}
-
-/// Build a map of instruction orders. Return the first terminator and its
-/// order. Consider EH_LABEL instructions to be terminators as well, since local
-/// values for phis after invokes must be materialized before the call.
-void FastISel::InstOrderMap::initialize(
-    MachineBasicBlock *MBB, MachineBasicBlock::iterator LastFlushPoint) {
-  unsigned Order = 0;
-  for (MachineInstr &I : *MBB) {
-    if (!FirstTerminator &&
-        (I.isTerminator() || isTerminatingEHLabel(MBB, I))) {
-      FirstTerminator = &I;
-      FirstTerminatorOrder = Order;
-    }
-    Orders[&I] = Order++;
-
-    // We don't need to order instructions past the last flush point.
-    if (I.getIterator() == LastFlushPoint)
-      break;
-  }
-}
+void FastISel::flushLocalValueMap() {
+  // If FastISel bails out, it could leave local value instructions behind
+  // that aren't used for anything.  Detect and erase those.
+  if (LastLocalValue != EmitStartPt) {
+    // Save the first instruction after local values, for later.
+    MachineBasicBlock::iterator FirstNonValue(LastLocalValue);
+    ++FirstNonValue;
 
-void FastISel::sinkLocalValueMaterialization(MachineInstr &LocalMI,
-                                             Register DefReg,
-                                             InstOrderMap &OrderMap) {
-  // If this register is used by a register fixup, MRI will not contain all
-  // the uses until after register fixups, so don't attempt to sink or DCE
-  // this instruction. Register fixups typically come from no-op cast
-  // instructions, which replace the cast instruction vreg with the local
-  // value vreg.
+    MachineBasicBlock::reverse_iterator RE =
+        EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
+                    : FuncInfo.MBB->rend();
+    MachineBasicBlock::reverse_iterator RI(LastLocalValue);
+    for (; RI != RE;) {
+      MachineInstr &LocalMI = *RI;
+      // Increment before erasing what it points to.
+      ++RI;
+      Register DefReg = findLocalRegDef(LocalMI);
+      if (!DefReg)
+        continue;
       if (FuncInfo.RegsWithFixups.count(DefReg))
-    return;
-
-  // We can DCE this instruction if there are no uses and it wasn't a
-  // materialized for a successor PHI node.
+        continue;
       bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
       if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
         if (EmitStartPt == &LocalMI)
           EmitStartPt = EmitStartPt->getPrevNode();
-    LLVM_DEBUG(dbgs() << "removing dead local value materialization "
+        LLVM_DEBUG(dbgs() << "removing dead local value materialization"
                           << LocalMI);
-    OrderMap.Orders.erase(&LocalMI);
         LocalMI.eraseFromParent();
-    return;
-  }
-
-  // Number the instructions if we haven't yet so we can efficiently find the
-  // earliest use.
-  if (OrderMap.Orders.empty())
-    OrderMap.initialize(FuncInfo.MBB, LastFlushPoint);
-
-  // Find the first user in the BB.
-  MachineInstr *FirstUser = nullptr;
-  unsigned FirstOrder = std::numeric_limits<unsigned>::max();
-  for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) {
-    auto I = OrderMap.Orders.find(&UseInst);
-    assert(I != OrderMap.Orders.end() &&
-           "local value used by instruction outside local region");
-    unsigned UseOrder = I->second;
-    if (UseOrder < FirstOrder) {
-      FirstOrder = UseOrder;
-      FirstUser = &UseInst;
       }
     }
 
-  // The insertion point will be the first terminator or the first user,
-  // whichever came first. If there was no terminator, this must be a
-  // fallthrough block and the insertion point is the end of the block.
-  MachineBasicBlock::instr_iterator SinkPos;
-  if (UsedByPHI && OrderMap.FirstTerminatorOrder < FirstOrder) {
-    FirstOrder = OrderMap.FirstTerminatorOrder;
-    SinkPos = OrderMap.FirstTerminator->getIterator();
-  } else if (FirstUser) {
-    SinkPos = FirstUser->getIterator();
-  } else {
-    assert(UsedByPHI && "must be users if not used by a phi");
-    SinkPos = FuncInfo.MBB->instr_end();
+    if (FirstNonValue != FuncInfo.MBB->end()) {
+      // See if there are any local value instructions left.  If so, we want to
+      // make sure the first one has a debug location; if it doesn't, use the
+      // first non-value instruction's debug location.
+
+      // If EmitStartPt is non-null, this block had copies at the top before
+      // FastISel started doing anything; it points to the last one, so the
+      // first local value instruction is the one after EmitStartPt.
+      // If EmitStartPt is null, the first local value instruction is at the
+      // top of the block.
+      MachineBasicBlock::iterator FirstLocalValue =
+          EmitStartPt ? ++MachineBasicBlock::iterator(EmitStartPt)
+                      : FuncInfo.MBB->begin();
+      if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
+        FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
     }
-
-  // Collect all DBG_VALUEs before the new insertion position so that we can
-  // sink them.
-  SmallVector<MachineInstr *, 1> DbgValues;
-  for (MachineInstr &DbgVal : MRI.use_instructions(DefReg)) {
-    if (!DbgVal.isDebugValue())
-      continue;
-    unsigned UseOrder = OrderMap.Orders[&DbgVal];
-    if (UseOrder < FirstOrder)
-      DbgValues.push_back(&DbgVal);
-  }
-
-  // Sink LocalMI before SinkPos and assign it the same DebugLoc.
-  LLVM_DEBUG(dbgs() << "sinking local value to first use " << LocalMI);
-  FuncInfo.MBB->remove(&LocalMI);
-  FuncInfo.MBB->insert(SinkPos, &LocalMI);
-  if (SinkPos != FuncInfo.MBB->end())
-    LocalMI.setDebugLoc(SinkPos->getDebugLoc());
-
-  // Sink any debug values that we've collected.
-  for (MachineInstr *DI : DbgValues) {
-    FuncInfo.MBB->remove(DI);
-    FuncInfo.MBB->insert(SinkPos, DI);
   }
+
+  LocalValueMap.clear();
+  LastLocalValue = EmitStartPt;
+  recomputeInsertPt();
+  SavedInsertPt = FuncInfo.InsertPt;
+  LastFlushPoint = FuncInfo.InsertPt;
 }
 
 bool FastISel::hasTrivialKill(const Value *V) {
   // Don't consider constants or arguments to have trivial kills.
   const Instruction *I = dyn_cast<Instruction>(V);
   if (!I)
     return false;
 
while (I != E) {
     ++I;
     Dead->eraseFromParent();
     ++NumFastIselDead;
   }
   recomputeInsertPt();
 }
 
 FastISel::SavePoint FastISel::enterLocalValueArea() {
-  MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
-  DebugLoc OldDL = DbgLoc;
+  SavePoint OldInsertPt = FuncInfo.InsertPt;
   recomputeInsertPt();
-  DbgLoc = DebugLoc();
-  SavePoint SP = {OldInsertPt, OldDL};
-  return SP;
+  return OldInsertPt;
 }
 
 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
   if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
     LastLocalValue = &*std::prev(FuncInfo.InsertPt);
 
   // Restore the previous insert position.
-  FuncInfo.InsertPt = OldInsertPt.InsertPt;
-  DbgLoc = OldInsertPt.DL;
+  FuncInfo.InsertPt = OldInsertPt;
 }
 
 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
   EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
   if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
 
if (CurLastLocalValue != SavedLastLocalValue) {
     else
       FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
     setLastLocalValue(SavedLastLocalValue);
     removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
   }
 }
 
 bool FastISel::selectInstruction(const Instruction *I) {
+  // Flush the local value map before starting each instruction.
+  // This improves locality and debugging, and can reduce spills.
+  // Reuse of values across IR instructions is relatively uncommon.
+  flushLocalValueMap();
+
   MachineInstr *SavedLastLocalValue = getLastLocalValue();
   // Just before the terminator instruction, insert instructions to
   // feed PHI nodes in successor blocks.
   if (I->isTerminator()) {
     if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
       // PHI node handling may have generated local value instructions,
       // even though it failed to handle all PHI nodes.
       // We remove these instructions because SelectionDAGISel will generate
for (const PHINode &PN : SuccBB->phis()) {
         if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
           FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
           return false;
         }
       }
 
       const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
 
-      // Set the DebugLoc for the copy. Prefer the location of the operand
-      // if there is one; use the location of the PHI otherwise.
-      DbgLoc = PN.getDebugLoc();
+      // Set the DebugLoc for the copy. Use the location of the operand if
+      // there is one; otherwise no location, flushLocalValueMap will fix it.
+      DbgLoc = DebugLoc();
       if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
         DbgLoc = Inst->getDebugLoc();
 
       Register Reg = getRegForValue(PHIOp);
       if (!Reg) {
         FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
         return false;
       }

llvm/test/CodeGen/AArch64/arm64-abi_align.ll

 ; FAST: stur {{x[0-9]+}}, [x29, #-32]
 ; FAST: stur {{x[0-9]+}}, [x29, #-24]
 ; FAST: stur {{x[0-9]+}}, [x29, #-16]
 ; FAST: stur {{x[0-9]+}}, [x29, #-8]
 ; FAST: str {{x[0-9]+}}, [sp, #32]
 ; FAST: str {{x[0-9]+}}, [sp, #40]
 ; FAST: str {{x[0-9]+}}, [sp, #48]
 ; FAST: str {{x[0-9]+}}, [sp, #56]
-; FAST: str {{w[0-9]+}}, [sp]
 ; Address of s1 is passed on stack at sp+8
 ; FAST: sub x[[A:[0-9]+]], x29, #32
-; FAST: str x[[A]], [sp, #8]
 ; FAST: add x[[B:[0-9]+]], sp, #32
+; FAST: str {{w[0-9]+}}, [sp]
+; FAST: str x[[A]], [sp, #8]
 ; FAST: str x[[B]], [sp, #16]
   %tmp = alloca %struct.s43, align 16
   %tmp1 = alloca %struct.s43, align 16
   %0 = bitcast %struct.s43* %tmp to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %0, i8* align 16 bitcast (%struct.s43* @g43 to i8*), i64 32, i1 false), !tbaa.struct !4
   %1 = bitcast %struct.s43* %tmp1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %1, i8* align 16 bitcast (%struct.s43* @g43_2 to i8*), i64 32, i1 false), !tbaa.struct !4
   %call = call i32 @f43_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,

llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll

 
 ; Test materialization of integers.  Target-independent selector handles this.
 define i32 @t2() {
 entry:
 ; CHECK-LABEL: t2:
 ; CHECK:       mov x0, xzr
 ; CHECK:       mov w1, #-8
 ; CHECK:       mov [[REG2:w[0-9]+]], #1023
-; CHECK:       uxth w2, [[REG2]]
 ; CHECK:       mov [[REG3:w[0-9]+]], #2
-; CHECK:       sxtb w3, [[REG3]]
 ; CHECK:       mov [[REG4:w[0-9]+]], wzr
-; CHECK:       and w4, [[REG4]], #0x1
 ; CHECK:       mov [[REG5:w[0-9]+]], #1
+; CHECK:       uxth w2, [[REG2]]
+; CHECK:       sxtb w3, [[REG3]]
+; CHECK:       and w4, [[REG4]], #0x1
 ; CHECK:       and w5, [[REG5]], #0x1
 ; CHECK:       bl _func2
   %call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
   ret i32 0
 }
 
 declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext, i1 zeroext)
 

llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll

 ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
 ; CHECK: ldr  [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
 ; CHECK: ldr  [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
 ; CHECK: mov  [[REG4:x[0-9]+]], #1309
 ; CHECK: mul  [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
 ; CHECK: mov  [[REG3:x[0-9]+]], #13849
 ; CHECK: add  [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
 ; CHECK: and  [[REG8:x[0-9]+]], [[REG7]], #0xffff
+; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
+; CHECK: ldr  [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
 ; CHECK: str  [[REG8]], {{\[}}[[REG1]]{{\]}}
+; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
+; CHECK: ldr  [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
 ; CHECK: ldr  {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
   %0 = load i64, i64* @seed, align 8
   %mul = mul nsw i64 %0, 1309
   %add = add nsw i64 %mul, 13849
   %and = and i64 %add, 65535
   store i64 %and, i64* @seed, align 8
   %1 = load i64, i64* @seed, align 8
   %conv = trunc i64 %1 to i32
   ret i32 %conv
 }

llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll

 ; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64
 
 @message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16
 @temp = common global [80 x i8] zeroinitializer, align 16
 
 define void @t1() {
 ; ARM64-LABEL: t1
 ; ARM64: adrp x8, _message@PAGE
 ; ARM64: add x0, x8, _message@PAGEOFF
 ; ARM64: mov [[REG:w[0-9]+]], wzr
-; ARM64: uxtb w1, [[REG]]
 ; ARM64: mov x2, #80
+; ARM64: uxtb w1, [[REG]]
 ; ARM64: bl _memset
   call void @llvm.memset.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i1 false)
   ret void
 }
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
 
 define void @t2() {

llvm/test/CodeGen/AArch64/arm64-fast-isel.ll

 ; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void
 }
 
 declare void @llvm.trap() nounwind
 
 define void @ands(i32* %addr) {
-; CHECK-LABEL: ands:
-; CHECK: tst [[COND:w[0-9]+]], #0x1
-; CHECK-NEXT: mov w{{[0-9]+}}, #2
-; CHECK-NEXT: mov w{{[0-9]+}}, #1
-; CHECK-NEXT: csel [[COND]],
+; FIXME: 'select i1 undef' makes this unreliable (ub?).
+; COM: CHECK-LABEL: ands:
+; COM: CHECK: tst [[COND:w[0-9]+]], #0x1
+; COM: CHECK-NEXT: mov w{{[0-9]+}}, #2
+; COM: CHECK-NEXT: mov w{{[0-9]+}}, #1
+; COM: CHECK-NEXT: csel [[COND]],
 entry:
   %cond91 = select i1 undef, i32 1, i32 2
   store i32 %cond91, i32* %addr, align 4
   ret void
 }
 
 define i64 @mul_umul(i64 %arg) {
 ; CHECK-LABEL: mul_umul:

llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll

 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov  x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen2:
 ; FAST:        mov [[REG1:x[0-9]+]], #2
-; FAST-NEXT:   str [[REG1]], [sp]
 ; FAST-NEXT:   mov [[REG2:w[0-9]+]], #4
-; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   mov [[REG3:x[0-9]+]], #6
+; FAST-NEXT:   str [[REG1]], [sp]
+; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov  x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)

 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov   x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen3:
 ; FAST:        mov [[REG1:x[0-9]+]], #2
-; FAST-NEXT:   str [[REG1]], [sp]
 ; FAST-NEXT:   mov [[REG2:w[0-9]+]], #4
-; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   mov [[REG3:x[0-9]+]], #6
-; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST-NEXT:   mov [[REG4:w[0-9]+]], #8
-; FAST-NEXT:   str [[REG4]], [sp, #36]
 ; FAST-NEXT:   mov [[REG5:x[0-9]+]], #10
+; FAST-NEXT:   str [[REG1]], [sp]
+; FAST-NEXT:   str [[REG2]], [sp, #16]
+; FAST-NEXT:   str [[REG3]], [sp, #24]
+; FAST-NEXT:   str [[REG4]], [sp, #36]
 ; FAST-NEXT:   str [[REG5]], [sp, #48]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)

llvm/test/CodeGen/AArch64/cfguard-checks.ll

entry:
   %func_ptr = alloca i32 ()*, align 8
   store i32 ()* @target_func, i32 ()** %func_ptr, align 8
   %0 = load i32 ()*, i32 ()** %func_ptr, align 8
   %1 = call i32 %0()
   ret i32 %1
 
   ; The call to __guard_check_icall_fptr should come immediately before the call to the target function.
   ; CHECK-LABEL: func_optnone_cf
-  ; CHECK:        adrp x8, __guard_check_icall_fptr
-  ; CHECK:        add x9, x8, __guard_check_icall_fptr
   ; CHECK:        adrp x8, target_func
   ; CHECK:        add x8, x8, target_func
+  ; CHECK:        adrp x9, __guard_check_icall_fptr
+  ; CHECK:        add x9, x9, __guard_check_icall_fptr
   ; CHECK:        ldr x9, [x9]
   ; CHECK:        mov x15, x8
   ; CHECK:        blr x9
   ; CHECK-NEXT:   blr x8
 }
 attributes #1 = { noinline optnone }
 
 

llvm/test/CodeGen/AArch64/elf-globals-static.ll

define i8 @test_i8(i8 %new) {
   %val = load i8, i8* @var8, align 1
   store i8 %new, i8* @var8
   ret i8 %val
 ; CHECK-LABEL: test_i8:
 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 
+; CHECK-PIC-LABEL: test_i8:
+; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
+; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
+; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]]
+
 ; CHECK-FAST-LABEL: test_i8:
 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 }
 
 define i16 @test_i16(i16 %new) {
   %val = load i16, i16* @var16, align 2
   store i16 %new, i16* @var16

llvm/test/CodeGen/AArch64/large-stack.ll

 ; CHECK-NEXT:             str x[[SPILL_REG3:[0-9]+]], [sp, #[[SPILL_OFFSET2:[0-9]+]]]
 ; CHECK-NEXT:             mov x[[FRAME:[0-9]+]], sp
 ; CHECK-COUNT-128:        sub sp, sp, #[[STACK1:[0-9]+]], lsl #12
 ; CHECK-NEXT:             sub sp, sp, #[[STACK2:[0-9]+]], lsl #12
 ; CHECK-NEXT:             sub sp, sp, #[[STACK3:[0-9]+]]
 ; CHECK:                  sub x[[INDEX:[0-9]+]], x[[FRAME]], #8
 ; CHECK-NEXT:             str x0, [x[[INDEX]]]
 ; CHECK-NEXT:             ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
-; CHECK-NEXT:             mov x[[VAL2:[0-9]+]], #8
 ; CHECK-NEXT:             add x[[VAL3:[0-9]+]], sp, #8
+; CHECK-NEXT:             mov x[[VAL2:[0-9]+]], #8
 ; CHECK-NEXT:             madd  x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]]
 ; CHECK-NEXT:             mov x[[TMP1:[0-9]+]], #1
 ; CHECK-NEXT:             str x[[TMP1]], [x[[VAL1]]]
 ; CHECK-NEXT:             ldr x[[INDEX]], [x[[INDEX]]]
+; CHECK-NEXT:             add   x[[VAL3:[0-9]+]], sp, #8
 ; CHECK-NEXT:             mov x[[VAL4:[0-9]+]], #8
 ; CHECK-NEXT:             madd  x[[INDEX]], x[[INDEX]], x[[VAL4]], x[[VAL3]]
 ; CHECK-NEXT:             ldr x1, [x[[INDEX]]
 ; CHECK:                  bl  printf
 ; CHECK-COUNT-128:        add sp, sp, #[[STACK1]], lsl #12
 ; CHECK-NEXT:             add sp, sp, #[[STACK2]], lsl #12
 ; CHECK-NEXT:             add sp, sp, #[[STACK3]]
 ; CHECK-NEXT:             ldr x[[SPILL_REG3]], [sp, #[[SPILL_OFFSET2]]]
 ; CHECK-NEXT:             ldp x[[SPILL_REG1]], x[[SPILL_REG2]], [sp], #[[SPILL_OFFSET1]]

llvm/test/CodeGen/ARM/fast-isel-call.ll

 ; ARM-DAG: movw [[R4:l?r[0-9]*]], #40
 ; ARM-DAG: movw [[R5:l?r[0-9]*]], #186
 ; ARM-DAG: and [[R0]], [[R0]], #255
 ; ARM-DAG: and [[R1]], [[R1]], #255
 ; ARM-DAG: and [[R2]], [[R2]], #255
 ; ARM-DAG: and [[R3]], [[R3]], #255
 ; ARM-DAG: and [[R4]], [[R4]], #255
 ; ARM-DAG: str [[R4]], [sp]
-; ARM-DAG: and [[R4]], [[R5]], #255
-; ARM-DAG: str [[R4]], [sp, #4]
+; ARM-DAG: and [[R5]], [[R5]], #255
+; ARM-DAG: str [[R5]], [sp, #4]
 ; ARM: bl {{_?}}bar
 ; ARM-LONG-LABEL: @t10
 
 ; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
 ; ARM-LONG-MACHO: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
 ; ARM-LONG-MACHO: ldr [[R:r[0-9]+]], {{\[}}[[R1]]]
 
 ; ARM-LONG-ELF: movw [[R1:r[0-9]*]], :lower16:bar

 ; THUMB-DAG: movw [[R4:l?r[0-9]*]], #40
 ; THUMB-DAG: movw [[R5:l?r[0-9]*]], #186
 ; THUMB-DAG: and [[R0]], [[R0]], #255
 ; THUMB-DAG: and [[R1]], [[R1]], #255
 ; THUMB-DAG: and [[R2]], [[R2]], #255
 ; THUMB-DAG: and [[R3]], [[R3]], #255
 ; THUMB-DAG: and [[R4]], [[R4]], #255
 ; THUMB-DAG: str.w [[R4]], [sp]
-; THUMB-DAG: and [[R4]], [[R5]], #255
-; THUMB-DAG: str.w [[R4]], [sp, #4]
+; THUMB-DAG: and [[R5]], [[R5]], #255
+; THUMB-DAG: str.w [[R5]], [sp, #4]
 ; THUMB: bl {{_?}}bar
 ; THUMB-LONG-LABEL: @t10
 ; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
 ; THUMB-LONG: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
 ; THUMB-LONG: ldr{{(.w)?}} [[R:r[0-9]+]], {{\[}}[[R1]]{{\]}}
 ; THUMB-LONG: blx [[R]]
   %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
   ret i32 0

llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll

 ; ARM-LONG-ELF: movt r3, :upper16:memset
 
 ; ARM-LONG: blx r3
 ; THUMB-LABEL: t1:
 ; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
 ; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
 ; THUMB: adds r0, #5
 ; THUMB: movs r1, #64
-; THUMB: and r1, r1, #255
 ; THUMB: movs r2, #10
+; THUMB: and r1, r1, #255
 ; THUMB: bl {{_?}}memset
 ; THUMB-LONG-LABEL: t1:
 ; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
 ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
 ; THUMB-LONG: ldr r3, [r3]
 ; THUMB-LONG: blx r3
   call void @llvm.memset.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i1 false)
   ret void

llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll

; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-252]
   ret void
 }
 
 define void @t12(i32* nocapture %ptr) nounwind {
 entry:
 ; THUMB-LABEL: t12:
   %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
   store i32 0, i32* %add.ptr, align 4
+; THUMB: mov [[PTR:r[0-9]+]], r0
+; THUMB: movs [[VAL:r[0-9]+]], #0
 ; THUMB: movw [[REG:r[0-9]+]], #65280
 ; THUMB: movt [[REG]], #65535
-; THUMB: add [[REG]], r0
-; THUMB: str r{{[0-9]}}, {{\[}}[[REG]]]
+; THUMB: add [[PTR]], [[REG]]
+; THUMB: str [[VAL]], {{\[}}[[PTR]]]
   ret void
 }
 
 define void @t13(i16* nocapture %ptr) nounwind {
 entry:
 ; THUMB-LABEL: t13:
   %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
   store i16 0, i16* %add.ptr, align 2
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-254]
   ret void
 }
 
 define void @t15(i16* nocapture %ptr) nounwind {
 entry:
 ; THUMB-LABEL: t15:
   %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
   store i16 0, i16* %add.ptr, align 2
+; THUMB: mov [[PTR:r[0-9]+]], r0
+; THUMB: movs [[VAL:r[0-9]+]], #0
 ; THUMB: movw [[REG:r[0-9]+]], #65280
 ; THUMB: movt [[REG]], #65535
-; THUMB: add [[REG]], r0
-; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]]]
+; THUMB: add [[PTR]], [[REG]]
+; THUMB: strh [[VAL]], {{\[}}[[PTR]]]
   ret void
 }
 
 define void @t16(i8* nocapture %ptr) nounwind {
 entry:
 ; THUMB-LABEL: t16:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
   store i8 0, i8* %add.ptr, align 1
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-255]
   ret void
 }
 
 define void @t18(i8* nocapture %ptr) nounwind {
 entry:
 ; THUMB-LABEL: t18:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
   store i8 0, i8* %add.ptr, align 1
+; THUMB: mov [[PTR:r[0-9]+]], r0
+; THUMB: movs [[VAL]], #0
 ; THUMB: movw [[REG:r[0-9]+]], #65280
 ; THUMB: movt [[REG]], #65535
-; THUMB: add [[REG]], r0
-; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]]]
+; THUMB: add [[PTR]], [[REG]]
+; THUMB: strb [[VAL]], {{\[}}[[PTR]]]
   ret void
 }

llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll

 
 ; mvn r1, #255
 ; strh r2, [r0, r1]
 define void @t10(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM-LABEL: t10:
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
   store i16 0, i16* %add.ptr, align 2
-; ARM: mvn r1, #255
-; ARM: add [[REG0:r[0-9]+]], r0, r1
+; ARM: mov r1, r0
 ; ARM: movw [[REG1:r[0-9]+]], #0
+; ARM: mvn [[REG2:r[0-9]+]], #255
+; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]]
 ; ARM: strh [[REG1]], {{\[}}[[REG0]]]
   ret void
 }
 
 define void @t11(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM-LABEL: t11:
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
   store i16 0, i16* %add.ptr, align 2
 ; ARM: movw [[REG1:r[0-9]+]], #0
 ; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]
   ret void
 }
 
 ; mov r1, #256
 ; strh r2, [r0, r1]
 define void @t12(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM-LABEL: t12:
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
   store i16 0, i16* %add.ptr, align 2
-; ARM: add [[REG0:r[0-9]+]], r0, #256
+; ARM: mov r1, r0
 ; ARM: movw [[REG1:r[0-9]+]], #0
+; ARM: add [[REG0:r[0-9]+]], r1, #256
 ; ARM: strh [[REG1]], {{\[}}[[REG0]]]
   ret void
 }
 
 define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM-LABEL: t13:
   %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8

llvm/test/CodeGen/ARM/fast-isel-select.ll

 ; RUN: llc -fast-isel-sink-local-values < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
 ; RUN: llc -fast-isel-sink-local-values < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc -fast-isel-sink-local-values < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 ; RUN: llc -fast-isel-sink-local-values < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i1 %c) nounwind readnone {
 entry:
 ; ARM-LABEL: t1:
-; ARM: tst r0, #1
+; ARM: mov r1, r0
 ; ARM: movw r0, #10
+; ARM: tst r1, #1
 ; ARM: moveq r0, #20
 ; THUMB-LABEL: t1:
-; THUMB: tst.w r0, #1
-; THUMB: movw r0, #10
+; THUMB: mov r1, r0
+; THUMB: movs r0, #10
+; THUMB: tst.w r1, #1
 ; THUMB: it eq
 ; THUMB: moveq r0, #20
   %0 = select i1 %c, i32 10, i32 20
   ret i32 %0
 }
 
 define i32 @t2(i1 %c, i32 %a) nounwind readnone {
 entry:
; THUMB: adds r0, r2, r1
   %0 = select i1 %c, i32 %a, i32 %b
   %1 = add i32 %0, %a
   ret i32 %1
 }
 
 define i32 @t4(i1 %c) nounwind readnone {
 entry:
 ; ARM-LABEL: t4:
-; ARM: tst r0, #1
+; ARM: mov r1, r0
 ; ARM: mvn r0, #9
+; ARM: tst r1, #1
 ; ARM: mvneq r0, #0
 ; THUMB-LABEL: t4:
-; THUMB: tst.w r0, #1
+; THUMB: mov r1, r0
 ; THUMB: mvn r0, #9
+; THUMB: tst.w r1, #1
 ; THUMB: it eq
 ; THUMB: mvneq r0, #0
   %0 = select i1 %c, i32 -10, i32 -1
   ret i32 %0
 }
 
 define i32 @t5(i1 %c, i32 %a) nounwind readnone {
 entry:

llvm/test/CodeGen/ARM/fast-isel.ll

 ; Note that relocations are either movw/movt or constant pool
 ; loads. Different platforms will select different approaches.
 
 ; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
 ; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
 ; THUMB: ldr [[REG:r[0-9]+]], [r0]
 ; THUMB: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]]
 ; THUMB: adds [[REG1]], #1
-; THUMB: str [[REG1]], {{\[}}[[REG]]]
+; THUMB: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}}
+; THUMB: ldr [[REG2:r[0-9]+]], [r1]
+; THUMB: str [[REG1]], {{\[}}[[REG2]]]
 
 ; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
 ; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
 ; ARM-MACHO: ldr [[REG:r[0-9]+]], [r0]
 
 ; ARM-ELF: movw [[REG:r[0-9]+]], :lower16:test4g
 ; ARM-ELF: movt [[REG]], :upper16:test4g
 
-; ARM: ldr r0, [r1]
-; ARM: add r0, r0, #1
-; ARM: str r0, [r1]
+; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]]
+; ARM: add [[REG2:r[0-9]+]], [[REG1]], #1
+
+; ARM-MACHO: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM-MACHO: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}}
+; ARM-MACHO: ldr [[REG3:r[0-9]+]], [r1]
+
+; ARM-ELF: movw [[REG3:r[0-9]+]], :lower16:test4g
+; ARM-ELF: movt [[REG3]], :upper16:test4g
+
+; ARM: str [[REG2]], {{\[}}[[REG3]]]
 }
 
 ; ARM: @urem_fold
 ; THUMB: @urem_fold
 ; ARM: and r0, r0, #31
 ; THUMB: and r0, r0, #31
 define i32 @urem_fold(i32 %a) nounwind {
   %rem = urem i32 %a, 32

llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll

define void @cxiii() {
   ret void
 }
 
 declare void @xcccc(i8, i8, i8, i8)
 
 define void @cxcccc() {
   ; ALL-LABEL:    cxcccc:
 
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 88
-  ; 32R1:       sll     $[[R:[0-9]+]], $[[R]], 24
-  ; 32R1:       sra     $4, $[[R]], 24
-  ; 32R2:       seb     $4, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 44
-  ; 32R1:       sll     $[[R:[0-9]+]], $[[R]], 24
-  ; 32R1:       sra     $5, $[[R]], 24
-  ; 32R2:       seb     $5, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 11
-  ; 32R1:       sll     $[[R:[0-9]+]], $[[R]], 24
-  ; 32R1:       sra     $6, $[[R]], 24
-  ; 32R2:       seb     $6, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 33
-  ; 32R1:       sll     $[[R:[0-9]+]], $[[R]], 24
-  ; 32R1:       sra     $7, $[[R]], 24
-  ; 32R2:       seb     $7, $[[R]]
+  ; ALL:        addiu   $[[R1:[0-9]+]], $zero, 88
+  ; ALL:        addiu   $[[R2:[0-9]+]], $zero, 44
+  ; ALL:        addiu   $[[R3:[0-9]+]], $zero, 11
+  ; ALL:        addiu   $[[R4:[0-9]+]], $zero, 33
+  ; 32R1:       sll     $[[R1:[0-9]+]], $[[R1]], 24
+  ; 32R1:       sra     $4, $[[R1]], 24
+  ; 32R2:       seb     $4, $[[R1]]
+  ; 32R1:       sll     $[[R2]], $[[R2]], 24
+  ; 32R1:       sra     $5, $[[R2]], 24
+  ; 32R2:       seb     $5, $[[R2]]
+  ; 32R1:       sll     $[[R3]], $[[R3]], 24
+  ; 32R1:       sra     $6, $[[R3]], 24
+  ; 32R2:       seb     $6, $[[R3]]
+  ; 32R1:       sll     $[[R4]], $[[R4]], 24
+  ; 32R1:       sra     $7, $[[R4]], 24
+  ; 32R2:       seb     $7, $[[R4]]
 
   ; ALL:        lw      $25, %got(xcccc)(${{[0-9]+}})
   ; ALL:        jalr    $25
   ; ALL:        jr      $ra
   call void @xcccc(i8 88, i8 44, i8 11, i8 33)
   ret void
 }
 
 declare void @xhhhh(i16, i16, i16, i16)
 
 define void @cxhhhh() {
   ; ALL-LABEL:    cxhhhh:
 
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 88
-  ; 32R1:       sll     $[[R]], $[[R]], 16
-  ; 32R1:       sra     $4, $[[R]], 16
-  ; 32R2:       seh     $4, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 44
-  ; 32R1:       sll     $[[R]], $[[R]], 16
-  ; 32R1:       sra     $5, $[[R]], 16
-  ; 32R2:       seh     $5, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 11
-  ; 32R1:       sll     $[[R]], $[[R]], 16
-  ; 32R1:       sra     $6, $[[R]], 16
-  ; 32R2:       seh     $6, $[[R]]
-  ; ALL:        addiu   $[[R:[0-9]+]], $zero, 33
-  ; 32R1:       sll     $[[R]], $[[R]], 16
-  ; 32R1:       sra     $7, $[[R]], 16
-  ; 32R2:       seh     $7, $[[R]]
+  ; ALL:        addiu   $[[R1:[0-9]+]], $zero, 88
+  ; ALL:        addiu   $[[R2:[0-9]+]], $zero, 44
+  ; ALL:        addiu   $[[R3:[0-9]+]], $zero, 11
+  ; ALL:        addiu   $[[R4:[0-9]+]], $zero, 33
+  ; 32R1:       sll     $[[R1]], $[[R1]], 16
+  ; 32R1:       sra     $4, $[[R1]], 16
+  ; 32R2:       seh     $4, $[[R1]]
+  ; 32R1:       sll     $[[R2]], $[[R2]], 16
+  ; 32R1:       sra     $5, $[[R2]], 16
+  ; 32R2:       seh     $5, $[[R2]]
+  ; 32R1:       sll     $[[R3]], $[[R3]], 16
+  ; 32R1:       sra     $6, $[[R3]], 16
+  ; 32R2:       seh     $6, $[[R3]]
+  ; 32R1:       sll     $[[R4]], $[[R4]], 16
+  ; 32R1:       sra     $7, $[[R4]], 16
+  ; 32R2:       seh     $7, $[[R4]]
 
   ; ALL:        lw      $25, %got(xhhhh)(${{[0-9]+}})
   ; ALL:        jalr    $25
   ; ALL:        jr      $ra
 
   call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
   ret void
 }

 }
 
 declare void @xiff(i32, float, float)
 
 define void @cxiff() {
   ; ALL-LABEL:    cxiff:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 12239
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17526
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 16543
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
-  ; ALL-DAG:        addiu   $4, $zero, 12239
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
   ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
   ; ALL-DAG:        lw      $25, %got(xiff)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
   ret void
 }
 
define void @cxifif() {
   ; ALL-LABEL:    cxifif:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REGI:[0-9]+]], 1
   ; ALL-DAG:        ori     $4, $[[REGI]], 2238
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17527
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
+  ; ALL-DAG:        addiu   $6, $zero, 9991
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17802
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
-  ; ALL-DAG:        addiu   $6, $zero, 9991
   ; ALL-DAG:        mfc1    $7, $f[[REGF1_3]]
   ; ALL-DAG:        lw      $25, %got(xifif)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xifif(i32 67774, float 0x408EE0FBE0000000,
                    i32 9991, float 0x40B15C8CC0000000)
   ret void
 }
 
 declare void @xiffi(i32, float, float, i32)
 
 define void @cxiffi() {
   ; ALL-LABEL:    cxiffi:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 45
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 16307
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17529
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
-  ; ALL-DAG:        addiu   $4, $zero, 45
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
   ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
   ; ALL-DAG:        addiu   $7, $zero, 234
   ; ALL-DAG:        lw      $25, %got(xiffi)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xiffi(i32 45, float 0x3FF6666660000000,
                    float 0x408F333340000000, i32 234)
   ret void

llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll

; CHECK-LABEL: foobar:
   %0 = load i32, i32* %x.addr, align 4
   store i32 %0, i32* %x1, align 4
   store %struct.x* %a, %struct.x** %c, align 4
   %1 = load %struct.x*, %struct.x** %c, align 4
   %x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0
   %2 = load i32, i32* %x2, align 4
   store i32 %2, i32* @i, align 4
   %3 = load i32, i32* %retval
-; CHECK:        lw      $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
 ; CHECK:        addiu   $[[A_ADDR:[0-9]+]], $sp, 8
+; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
 ; CHECK-DAG:    sw      $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
 ; CHECK-DAG:    lw      $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
 ; CHECK-DAG:    lw      $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
 ; CHECK-DAG:    sw      $[[A_X]], 0($[[I_ADDR]])
   ret i32 %3
 }

llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

 
 ; Function Attrs: nounwind
 define void @feq1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp oeq float %0, %1
 ; CHECK-LABEL:  feq1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.eq.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
 
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @fne1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp une float %0, %1
 ; CHECK-LABEL:  fne1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.eq.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @flt1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp olt float %0, %1
 ; CHECK-LABEL:  flt1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.olt.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
 
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @fgt1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp ogt float %0, %1
 ; CHECK-LABEL: fgt1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ule.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @fle1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp ole float %0, %1
 ; CHECK-LABEL:  fle1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ole.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @fge1()  {
 entry:
   %0 = load float, float* @f1, align 4
   %1 = load float, float* @f2, align 4
   %cmp = fcmp oge float %0, %1
 ; CHECK-LABEL:  fge1:
-; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
-; CHECK-DAG:    lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
-; CHECK-DAG:    lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK:        lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK:        lwc1    $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ult.s  $f[[REG_F1]], $f[[REG_F2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @deq1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp oeq double %0, %1
 ; CHECK-LABEL:  deq1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.eq.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @dne1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp une double %0, %1
 ; CHECK-LABEL:  dne1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.eq.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @dlt1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp olt double %0, %1
 ; CHECK-LABEL:  dlt1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
-; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
-; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK:        addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK:        addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.olt.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @dgt1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp ogt double %0, %1
 ; CHECK-LABEL:  dgt1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ule.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @dle1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp ole double %0, %1
 ; CHECK-LABEL:  dle1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ole.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movt  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @dge1()  {
 entry:
   %0 = load double, double* @d1, align 8
   %1 = load double, double* @d2, align 8
   %cmp = fcmp oge double %0, %1
 ; CHECK-LABEL:  dge1:
-; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
-; CHECK-DAG:    lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
-; CHECK-DAG:    ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
-; CHECK-DAG:    ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK:        lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK:        ldc1    $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
 ; CHECK-DAG:    addiu   $[[REG_ZERO:[0-9]+]], $zero, 0
 ; CHECK-DAG:    addiu   $[[REG_ONE:[0-9]+]], $zero, 1
 ; CHECK:        c.ult.d  $f[[REG_D1]], $f[[REG_D2]]
 ; CHECK:        movf  $[[REG_ZERO]], $[[REG_ONE]], $fcc0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 

llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll

 ; Function Attrs: nounwind
 define void @ugt()  {
 entry:
 ; CHECK-LABEL:  .ent  ugt
   %0 = load i32, i32* @uc, align 4
   %1 = load i32, i32* @ud, align 4
   %cmp = icmp ugt i32 %0, %1
   %conv = zext i1 %cmp to i32
-; CHECK-DAG:  lw  $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
-; CHECK-DAG:  lw  $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK:  lw  $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK:  lw  $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
 ; CHECK:  sltu  $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
 ; CHECK:  andi  ${{[0-9]+}}, $[[REG1]], 1
 
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 

 ; Function Attrs: nounwind
 define void @ule()  {
 entry:
 ; CHECK-LABEL:  .ent  ule
   %0 = load i32, i32* @uc, align 4
   %1 = load i32, i32* @ud, align 4
   %cmp = icmp ule i32 %0, %1
   %conv = zext i1 %cmp to i32
-; CHECK-DAG:  lw  $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
-; CHECK-DAG:  lw  $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK:  lw  $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK:  lw  $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
 ; CHECK:  sltu  $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
 ; CHECK:  xori  $[[REG2:[0-9]+]], $[[REG1]], 1
 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
 ; CHECK:  andi  ${{[0-9]+}}, $[[REG2]], 1
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @sgt()  {
 entry:
 ; CHECK-LABEL:  .ent sgt
   %0 = load i32, i32* @c, align 4
   %1 = load i32, i32* @d, align 4
   %cmp = icmp sgt i32 %0, %1
   %conv = zext i1 %cmp to i32
-; CHECK-DAG:  lw  $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
-; CHECK-DAG:  lw  $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK:  lw  $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK:  lw  $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
 ; CHECK:  slt  $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
 ; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
 ; CHECK:  andi  ${{[0-9]+}}, $[[REG1]], 1
   store i32 %conv, i32* @b1, align 4
   ret void
 }
 
 ; Function Attrs: nounwind

 ; Function Attrs: nounwind
 define void @sle()  {
 entry:
 ; CHECK-LABEL:  .ent sle
   %0 = load i32, i32* @c, align 4
   %1 = load i32, i32* @d, align 4
   %cmp = icmp sle i32 %0, %1
   %conv = zext i1 %cmp to i32
-; CHECK-DAG:  lw  $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
-; CHECK-DAG:  lw  $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
-; CHECK-DAG:  lw  $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK:  lw  $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK:  lw  $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK:  lw  $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
 ; CHECK:        slt     $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
 ; CHECK:        xori    $[[REG2:[0-9]+]], $[[REG1]], 1
 ; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
 ; CHECK:        andi    ${{[0-9]+}}, $[[REG2]], 1
   store i32 %conv, i32* @b1, align 4
   ret void
 }

llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll

entry:
   %conv1 = trunc i8 %1 to i1
   %and0 = and i1 %conv1, %conv0
   %conv3 = zext i1 %and0 to i8
   store i8 %conv3, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    andUb
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
 ; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @andUb0() #0 {
 entry:
   %0 = load i8, i8* @ub1, align 1, !tbaa !2
   %conv = trunc i8 %0 to i1
   %and = and i1 %conv, 0
   %conv1 = zext i1 %and to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    andUb0
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB1]], $zero
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    andUb0
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @andUb1() #0 {
 ; clang uses i8 constants for booleans, so we test with an i8 1.
 entry:
   %x = load i8, i8* @ub1, align 1, !tbaa !2
   %and = and i8 %x, 1
   %conv = trunc i8 %and to i1
   %conv1 = zext i1 %conv to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    andUb1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    andUb1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @orUb() #0 {
 entry:
   %0 = load i8, i8* @ub1, align 1
   %1 = load i8, i8* @ub2, align 1
   %conv0 = trunc i8 %0 to i1
   %conv1 = trunc i8 %1 to i1
   %or0 = or i1 %conv1, %conv0
   %conv3 = zext i1 %or0 to i8
   store i8 %conv3, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    orUb
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
 ; CHECK-DAG:    or      $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @orUb0() #0 {
 entry:
   %0 = load i8, i8* @ub1, align 1, !tbaa !2
   %conv = trunc i8 %0 to i1
   %or = or i1 %conv, 0
   %conv1 = zext i1 %or to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    orUb0
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[UB1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    orUb0
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @orUb1() #0 {
 entry:
   %x = load i8, i8* @ub1, align 1, !tbaa !2
   %or = or i8 %x, 1
   %conv = trunc i8 %or to i1
   %conv1 = zext i1 %conv to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    orUb1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    or      $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    orUb1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @xorUb() #0 {
 entry:
   %0 = load i8, i8* @ub1, align 1
   %1 = load i8, i8* @ub2, align 1
   %conv0 = trunc i8 %0 to i1
   %conv1 = trunc i8 %1 to i1
   %xor0 = xor i1 %conv1, %conv0
   %conv3 = zext i1 %xor0 to i8
   store i8 %conv3, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL: .ent    xorUb
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
 ; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @xorUb0() #0 {
 entry:
   %0 = load i8, i8* @ub1, align 1, !tbaa !2
   %conv = trunc i8 %0 to i1
   %xor = xor i1 %conv, 0
   %conv1 = zext i1 %xor to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    xorUb0
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB1]], $zero
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    xorUb0
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @xorUb1() #0 {
 entry:
   %x = load i8, i8* @ub1, align 1, !tbaa !2
   %xor = xor i8 1, %x
   %conv = trunc i8 %xor to i1
   %conv1 = zext i1 %conv to i8
   store i8 %conv1, i8* @ub, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    xorUb1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
 ; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
 ; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
 ; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
 ; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
 ; CHECK:        .end    xorUb1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @andUc() #0 {
 entry:

llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll

 
 ; Function Attrs: nounwind
 define void @foo() {
 entry:
 ; CHECK-LABEL:   .ent  foo
   %0 = load float*, float** @y, align 4
   %arrayidx = getelementptr inbounds float, float* %0, i32 64000
   store float 5.500000e+00, float* %arrayidx, align 4
-; CHECK:        lui     $[[REG_FPCONST_INT:[0-9]+]], 16560
-; CHECK:        mtc1    $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]]
 ; CHECK:        lw      $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
 ; CHECK:        lw      $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]])
+; CHECK:        lui     $[[REG_FPCONST_INT:[0-9]+]], 16560
+; CHECK:        mtc1    $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]]
 ; CHECK:        lui     $[[REG_IDX_UPPER:[0-9]+]], 3
 ; CHECK:        ori     $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392
 ; CHECK:        addu    $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]]
 ; CHECK:        swc1    $f[[REG_FPCONST]], 0($[[REG_Y_IDX]])
   ret void
 ; CHECK-LABEL:   .end  foo
 }
 

llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll

 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
 ; CHECK-DAG:    lhu     $[[S2:[0-9]+]], 0($[[S2_ADDR]])
-; CHECK:        sllv    $[[RES:[0-9]+]], $[[S1]], $[[S2]]
+; CHECK-DAG:    sllv    $[[RES:[0-9]+]], $[[S1]], $[[S2]]
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
   ret void
 }
 
 define void @slli() {
 entry:
   %0 = load i16, i16* @s1, align 2
   %shl = shl i16 %0, 5
   store i16 %shl, i16* @s3, align 2
 ; CHECK-LABEL:  slli:
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
 ; CHECK:        sll     $[[RES:[0-9]+]], $[[S1]],  5
+; CHECK:        lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
   ret void
 }
 
 define void @srl() {
 entry:
   %0 = load i16, i16* @us1, align 2
   %1 = load i16, i16* @us2, align 2
   %shr = lshr i16 %0, %1
   store i16 %shr, i16* @us3, align 2
   ret void
 ; CHECK-LABEL:  srl:
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
 ; CHECK-DAG:    lhu     $[[US2:[0-9]+]], 0($[[US2_ADDR]])
 ; CHECK:        srlv    $[[RES:[0-9]+]], $[[US1]], $[[US2]]
+; CHECK:        lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
 }
 
 define void @srli() {
 entry:
   %0 = load i16, i16* @us1, align 2
   %shr = lshr i16 %0, 4
   store i16 %shr, i16* @us3, align 2
 ; CHECK-LABEL:  srli:
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
 ; CHECK:        srl     $[[RES:[0-9]+]], $[[US1]], 4
+; CHECK:        lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
   ret void
 }
 
 define void @sra() {
 entry:
   %0 = load i16, i16* @s1, align 2
   %1 = load i16, i16* @s2, align 2
   %shr = ashr i16 %0, %1
   store i16 %shr, i16* @s3, align 2
 ; CHECK-LABEL:  sra:
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
 ; CHECK-DAG:    lhu     $[[S2:[0-9]+]], 0($[[S2_ADDR]])
 ; CHECK:        srav    $[[RES:[0-9]+]], $[[S1]], $[[S2]]
+; CHECK:        lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
   ret void
 }
 
 define void @srai() {
 entry:
   %0 = load i16, i16* @s1, align 2
   %shr = ashr i16 %0, 2
   store i16 %shr, i16* @s3, align 2
 ; CHECK-LABEL:  srai:
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
-; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
 ; CHECK:        sra     $[[RES:[0-9]+]], $[[S1]], 2
+; CHECK:        lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
 ; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
   ret void
 }

llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll

 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @abcd = external global i32
 
 ; Function Attrs: nounwind
 define void @foo()  {
 entry:
   store i32 12345, i32* @abcd, align 4
-; CHECK:  lw  $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
 ; CHECK:  addiu $[[REG1:[0-9]+]], $zero, 12345
+; CHECK:  lw  $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
 ; CHECK:  sw  $[[REG1]], 0($[[REG2]])
   ret void
 }
 

llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll

 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @ijk = external global i32
 
 ; Function Attrs: nounwind
 define void @si2_1() #0 {
 entry:
   store i32 32767, i32* @ijk, align 4
 ; CHECK:        .ent    si2_1
-; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        addiu   $[[REG1:[0-9]+]], $zero, 32767
+; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        sw      $[[REG1]], 0($[[REG2]])
 
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @si2_2() #0 {
 entry:
   store i32 -32768, i32* @ijk, align 4
 ; CHECK:        .ent    si2_2
 ; CHECK:        lui     $[[REG1:[0-9]+]], 65535
 ; CHECK:        ori     $[[REG2:[0-9]+]], $[[REG1]], 32768
 ; CHECK:        lw      $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        sw      $[[REG2]], 0($[[REG3]])
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @ui2_1() #0 {
 entry:
   store i32 65535, i32* @ijk, align 4
 ; CHECK:        .ent    ui2_1
-; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        ori     $[[REG1:[0-9]+]], $zero, 65535
+; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        sw      $[[REG1]], 0($[[REG2]])
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @ui4_1() #0 {
 entry:
   store i32 983040, i32* @ijk, align 4
 ; CHECK:        .ent    ui4_1
-; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        lui     $[[REG1:[0-9]+]], 15
+; CHECK:        lw      $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
 ; CHECK:        sw      $[[REG1]], 0($[[REG2]])
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @ui4_2() #0 {
 entry:
   store i32 719566, i32* @ijk, align 4

llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

 ; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
 ; Check that register scavenging spill slot is close to $fp.
 target triple="mipsel--"
 
+; FIXME: After recent rework to FastISel, don't know how to trigger the
+; emergency spill slot.  Filed PR48301.
+; XFAIL: *
 @var = external global i32
 @ptrvar = external global i8*
 
 ; CHECK-LABEL: func:
 define void @func() {
   %space = alloca i32, align 4
   %stackspace = alloca[16384 x i32], align 4
 

llvm/test/CodeGen/PowerPC/elf-common.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O0 < %s \
 ; RUN:    | FileCheck -check-prefix=NOOPT %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 < %s | FileCheck -check-prefix=STATIC %s
 
 ;; Test loading and storing a common symbol for static relocation model.
 
 @comm_glob = common dso_local global i32 0, align 4
 
 define dso_local signext i32 @test_comm() nounwind {
 ; NOOPT-LABEL: test_comm:
 ; NOOPT:       # %bb.0: # %entry
 ; NOOPT-NEXT:    addis 3, 2, comm_glob@toc@ha
-; NOOPT-NEXT:    addi 5, 3, comm_glob@toc@l
-; NOOPT-NEXT:    lwz 3, 0(5)
+; NOOPT-NEXT:    addi 3, 3, comm_glob@toc@l
+; NOOPT-NEXT:    lwz 3, 0(3)
 ; NOOPT-NEXT:    addi 4, 3, 1
+; NOOPT-NEXT:    addis 5, 2, comm_glob@toc@ha
+; NOOPT-NEXT:    addi 5, 5, comm_glob@toc@l
 ; NOOPT-NEXT:    stw 4, 0(5)
 ; NOOPT-NEXT:    extsw 3, 3
 ; NOOPT-NEXT:    blr
 ;
 ; STATIC-LABEL: test_comm:
 ; STATIC:       # %bb.0: # %entry
 ; STATIC-NEXT:    addis 4, 2, comm_glob@toc@ha
 ; STATIC-NEXT:    lwa 3, comm_glob@toc@l(4)

llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll

 }
 
 ; store
 
 define dso_local void @t7(i8 %v) nounwind {
 ; ELF64-LABEL: t7:
   %1 = add nsw i8 %v, 1
   store i8 %1, i8* @a, align 1
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: stb
   ret void
 }
 
 define dso_local void @t8(i16 %v) nounwind {
 ; ELF64-LABEL: t8:
   %1 = add nsw i16 %v, 1
   store i16 %1, i16* @b, align 2
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: sth
   ret void
 }
 
 define dso_local void @t9(i32 %v) nounwind {
 ; ELF64-LABEL: t9:
   %1 = add nsw i32 %v, 1
   store i32 %1, i32* @c, align 4
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: stw
   ret void
 }
 
 define dso_local void @t10(i64 %v) nounwind {
 ; ELF64-LABEL: t10:
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* @d, align 4
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: std
   ret void
 }
 
 define dso_local void @t11(float %v) nounwind {
 ; ELF64-LABEL: t11:
 ; SPE-LABEL: t11:
; ELF64: addi
   ret i64 %2
 }
 
 ;; std requires an offset divisible by 4, so we need stdx here.
 define dso_local void @t15(i64 %v) nounwind {
 ; ELF64-LABEL: t15:
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: li
 ; ELF64: stdx
   ret void
 }
 
 ;; ld requires an offset that fits in 16 bits, so we need ldx here.
 define i64 @t16() nounwind {
 ; ELF64-LABEL: t16:
   %1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: ldx
   %2 = add nsw i64 %1, 1
 ; ELF64: addi
   ret i64 %2
 }
 
 ;; std requires an offset that fits in 16 bits, so we need stdx here.
 define dso_local void @t17(i64 %v) nounwind {
 ; ELF64-LABEL: t17:
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
-; ELF64: addis
 ; ELF64: addi
+; ELF64: addis
 ; ELF64: addi
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: stdx
   ret void
 }
 

llvm/test/CodeGen/PowerPC/mcm-1.ll

entry:
   %2 = add i32 %0, %1
   ret i32 %2
 }
 
 ; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
+; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
+; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
+; CHECK: stw {{[0-9]+}}, 0([[REG4]])
 
 
 ; CHECK:      .section .toc,"aw",@progbits
 ; CHECK-NEXT: .LC0:
 ; CHECK-NEXT:  .tc ei[TC],ei
 ; CHECK-NEXT: .LC1:
-; CHECK-NEXT:  .tc fi[TC],fi
-; CHECK-NEXT: .LC2:
 ; CHECK-NEXT:  .tc gi[TC],gi
+; CHECK-NEXT: .LC2:
+; CHECK-NEXT:  .tc fi[TC],fi

llvm/test/CodeGen/PowerPC/mcm-13.ll

entry:
   store i32 %inc, i32* @wi, align 4
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_weak:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
+; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
+; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
+; CHECK: stw {{[0-9]+}}, 0([[REG4]])
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}

llvm/test/CodeGen/PowerPC/mcm-2.ll

entry:
   store i32 %inc, i32* @test_fn_static.si, align 4
   ret i32 %0
 }
 
 ; MEDIUM-LABEL: test_fn_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
-; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha
+; MEDIUM: addi [[REG4:[0-9]+]], [[REG3]], [[VAR]]@toc@l
+; MEDIUM: stw {{[0-9]+}}, 0([[REG4]])
 ; MEDIUM: .type [[VAR]],@object
 ; MEDIUM: .lcomm [[VAR]],4,4
 
 ; LARGE-LABEL: test_fn_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
-; LARGE: stw {{[0-9]+}}, 0([[REG2]])
+; LARGE: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha
+; LARGE: ld [[REG4:[0-9]+]], [[VAR]]@toc@l([[REG3]])
+; LARGE: stw {{[0-9]+}}, 0([[REG4]])
 ; LARGE:      .type test_fn_static.si,@object
 ; LARGE-NEXT: .lcomm test_fn_static.si,4,4
 
 ; LARGE:      .section .toc,"aw",@progbits
 ; LARGE-NEXT: [[VAR]]:
 ; LARGE-NEXT: .tc test_fn_static.si[TC],test_fn_static.si

llvm/test/CodeGen/PowerPC/mcm-3.ll

entry:
   store i32 %inc, i32* @gi, align 4
   ret i32 %0
 }
 
 ; MEDIUM-LABEL: test_file_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
-; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha
+; MEDIUM: addi [[REG4:[0-9]+]], [[REG3]], [[VAR]]@toc@l
+; MEDIUM: stw {{[0-9]+}}, 0([[REG4]])
 ; MEDIUM: .type [[VAR]],@object
 ; MEDIUM: .data
 ; MEDIUM: .globl [[VAR]]
 ; MEDIUM: [[VAR]]:
 ; MEDIUM: .long 5
 
 ; LARGE-LABEL: test_file_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
-; LARGE: stw {{[0-9]+}}, 0([[REG2]])
+; LARGE: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha
+; LARGE: ld [[REG4:[0-9]+]], [[VAR]]@toc@l([[REG3]])
+; LARGE: stw {{[0-9]+}}, 0([[REG4]])
 ; LARGE:      .type gi,@object
 ; LARGE-NEXT: .data
 ; LARGE-NEXT: .globl gi
 ; LARGE-NEXT: .p2align 2
 ; LARGE-NEXT: gi:
 ; LARGE-NEXT: .long 5
 
 ; LARGE:      .section .toc,"aw",@progbits
 ; LARGE-NEXT: [[VAR]]:
 ; LARGE-NEXT: .tc gi[TC],gi

llvm/test/CodeGen/PowerPC/mcm-6.ll

entry:
   store i32 %inc, i32* @ti, align 4
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_tentative:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
+; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
+; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
+; CHECK: stw {{[0-9]+}}, 0([[REG4]])
 ; CHECK: .comm ti,4,4
 ; CHECK:      .section .toc,"aw",@progbits
 ; CHECK-NEXT: .LC[[TOCNUM]]:
 ; CHECK-NEXT: .tc ti[TC],ti

llvm/test/CodeGen/PowerPC/mcm-9.ll

entry:
   store i32 %inc, i32* @a, align 4
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
+; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
+; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
+; CHECK: stw {{[0-9]+}}, 0([[REG4]])
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}

llvm/test/CodeGen/PowerPC/mcm-default.ll

entry:
   store i32 %inc, i32* @ei, align 4
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
+; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
+; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
+; CHECK: stw {{[0-9]+}}, 0([[REG4]])
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}

llvm/test/CodeGen/X86/atomic-unordered.ll

; CHECK-O3-NEXT:    retq
   ret i256 %v
 }
 
 define void @store_i256(i256* %ptr, i256 %v) {
 ; CHECK-O0-LABEL: store_i256:
 ; CHECK-O0:       # %bb.0:
 ; CHECK-O0-NEXT:    subq $40, %rsp
 ; CHECK-O0-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-O0-NEXT:    movq %rcx, %rax
-; CHECK-O0-NEXT:    movq %rdx, (%rsp) # 8-byte Spill
-; CHECK-O0-NEXT:    movq %rsi, %r9
+; CHECK-O0-NEXT:    movq %rdx, %rax
+; CHECK-O0-NEXT:    movq %rsi, (%rsp) # 8-byte Spill
 ; CHECK-O0-NEXT:    movq %rdi, %rsi
 ; CHECK-O0-NEXT:    movq (%rsp), %rdi # 8-byte Reload
-; CHECK-O0-NEXT:    xorl %ecx, %ecx
 ; CHECK-O0-NEXT:    leaq {{[0-9]+}}(%rsp), %rdx
-; CHECK-O0-NEXT:    movq %r9, {{[0-9]+}}(%rsp)
 ; CHECK-O0-NEXT:    movq %rdi, {{[0-9]+}}(%rsp)
 ; CHECK-O0-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-O0-NEXT:    movq %rcx, {{[0-9]+}}(%rsp)
 ; CHECK-O0-NEXT:    movq %r8, {{[0-9]+}}(%rsp)
 ; CHECK-O0-NEXT:    movl $32, %edi
+; CHECK-O0-NEXT:    xorl %ecx, %ecx
 ; CHECK-O0-NEXT:    callq __atomic_store
 ; CHECK-O0-NEXT:    addq $40, %rsp
 ; CHECK-O0-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-O0-NEXT:    retq
 ;
 ; CHECK-O3-LABEL: store_i256:
 ; CHECK-O3:       # %bb.0:
 ; CHECK-O3-NEXT:    subq $40, %rsp
; CHECK-O3-EX-NEXT:    retq
   ret i64 %ret
 }
 
 ; Legal to fold (TODO)
 define i64 @load_fold_sdiv1(i64* %p) {
 ; CHECK-O0-LABEL: load_fold_sdiv1:
 ; CHECK-O0:       # %bb.0:
 ; CHECK-O0-NEXT:    movq (%rdi), %rax
-; CHECK-O0-NEXT:    cqto
 ; CHECK-O0-NEXT:    movl $15, %ecx
+; CHECK-O0-NEXT:    cqto
 ; CHECK-O0-NEXT:    idivq %rcx
 ; CHECK-O0-NEXT:    retq
 ;
 ; CHECK-O3-LABEL: load_fold_sdiv1:
 ; CHECK-O3:       # %bb.0:
 ; CHECK-O3-NEXT:    movq (%rdi), %rcx
 ; CHECK-O3-NEXT:    movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889
 ; CHECK-O3-NEXT:    movq %rcx, %rax
; CHECK-O3-NEXT:    retq
   ret i64 %ret
 }
 
 ; Legal to fold (TODO)
 define i64 @load_fold_udiv1(i64* %p) {
 ; CHECK-O0-LABEL: load_fold_udiv1:
 ; CHECK-O0:       # %bb.0:
 ; CHECK-O0-NEXT:    movq (%rdi), %rax
-; CHECK-O0-NEXT:    xorl %ecx, %ecx
-; CHECK-O0-NEXT:    movl %ecx, %edx
 ; CHECK-O0-NEXT:    movl $15, %ecx
+; CHECK-O0-NEXT:    xorl %edx, %edx
+; CHECK-O0-NEXT:    # kill: def $rdx killed $edx
 ; CHECK-O0-NEXT:    divq %rcx
 ; CHECK-O0-NEXT:    retq
 ;
 ; CHECK-O3-CUR-LABEL: load_fold_udiv1:
 ; CHECK-O3-CUR:       # %bb.0:
 ; CHECK-O3-CUR-NEXT:    movq (%rdi), %rdx
 ; CHECK-O3-CUR-NEXT:    movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889
 ; CHECK-O3-CUR-NEXT:    mulxq %rax, %rax, %rax
; CHECK-O3-NEXT:    retq
   ret i64 %ret
 }
 
 ; Legal to fold (TODO)
 define i64 @load_fold_srem1(i64* %p) {
 ; CHECK-O0-LABEL: load_fold_srem1:
 ; CHECK-O0:       # %bb.0:
 ; CHECK-O0-NEXT:    movq (%rdi), %rax
-; CHECK-O0-NEXT:    cqto
 ; CHECK-O0-NEXT:    movl $15, %ecx
+; CHECK-O0-NEXT:    cqto
 ; CHECK-O0-NEXT:    idivq %rcx
 ; CHECK-O0-NEXT:    movq %rdx, %rax
 ; CHECK-O0-NEXT:    retq
 ;
 ; CHECK-O3-LABEL: load_fold_srem1:
 ; CHECK-O3:       # %bb.0:
 ; CHECK-O3-NEXT:    movq (%rdi), %rcx
 ; CHECK-O3-NEXT:    movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889
; CHECK-O3-NEXT:    retq
   ret i64 %ret
 }
 
 ; Legal to fold (TODO)
 define i64 @load_fold_urem1(i64* %p) {
 ; CHECK-O0-LABEL: load_fold_urem1:
 ; CHECK-O0:       # %bb.0:
 ; CHECK-O0-NEXT:    movq (%rdi), %rax
-; CHECK-O0-NEXT:    xorl %ecx, %ecx
-; CHECK-O0-NEXT:    movl %ecx, %edx
 ; CHECK-O0-NEXT:    movl $15, %ecx
+; CHECK-O0-NEXT:    xorl %edx, %edx
+; CHECK-O0-NEXT:    # kill: def $rdx killed $edx
 ; CHECK-O0-NEXT:    divq %rcx
 ; CHECK-O0-NEXT:    movq %rdx, %rax
 ; CHECK-O0-NEXT:    retq
 ;
 ; CHECK-O3-LABEL: load_fold_urem1:
 ; CHECK-O3:       # %bb.0:
 ; CHECK-O3-NEXT:    movq (%rdi), %rax
 ; CHECK-O3-NEXT:    movabsq $-8608480567731124087, %rcx # imm = 0x8888888888888889

llvm/test/CodeGen/X86/atomic64.ll

 ; X64-NEXT:    retq
 ;
 ; I486-LABEL: atomic_fetch_cmpxchg64:
 ; I486:       # %bb.0:
 ; I486-NEXT:    pushl %ebp
 ; I486-NEXT:    movl %esp, %ebp
 ; I486-NEXT:    andl $-8, %esp
 ; I486-NEXT:    subl $32, %esp
-; I486-NEXT:    leal sc64, %eax
 ; I486-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; I486-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; I486-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; I486-NEXT:    leal sc64, %eax
 ; I486-NEXT:    movl %esp, %eax
 ; I486-NEXT:    movl %ecx, 4(%eax)
 ; I486-NEXT:    movl $2, 20(%eax)
 ; I486-NEXT:    movl $2, 16(%eax)
 ; I486-NEXT:    movl $0, 12(%eax)
 ; I486-NEXT:    movl $1, 8(%eax)
 ; I486-NEXT:    movl $sc64, (%eax)
 ; I486-NEXT:    calll __atomic_compare_exchange_8

 ;
 ; I486-LABEL: atomic_fetch_swapf64:
 ; I486:       # %bb.0:
 ; I486-NEXT:    pushl %ebp
 ; I486-NEXT:    movl %esp, %ebp
 ; I486-NEXT:    andl $-8, %esp
 ; I486-NEXT:    subl $24, %esp
 ; I486-NEXT:    fldl 8(%ebp)
-; I486-NEXT:    leal fsc64, %eax
 ; I486-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; I486-NEXT:    leal fsc64, %eax
 ; I486-NEXT:    movl %esp, %eax
 ; I486-NEXT:    movl %edx, 8(%eax)
 ; I486-NEXT:    movl %ecx, 4(%eax)
 ; I486-NEXT:    movl $2, 12(%eax)
 ; I486-NEXT:    movl $fsc64, (%eax)
 ; I486-NEXT:    calll __atomic_exchange_8
 ; I486-NEXT:    movl %ebp, %esp
 ; I486-NEXT:    popl %ebp
 ; I486-NEXT:    retl
   %t1 = atomicrmw xchg double* @fsc64, double %x acquire
   ret void
 }

llvm/test/CodeGen/X86/crash-O0.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 -relocation-model=pic -frame-pointer=all < %s | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10"
 
 ; This file contains functions that may crash llc -O0
 
 ; The DIV8 instruction produces results in AH and AL, but we don't want to use
 ; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for
 ; aliased registers (AX and AL) - RegAllocFast does not like that.
 ; PR7312
 define i32 @div8() nounwind {
 ; CHECK-LABEL: div8:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    pushq %rbp
 ; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    ## implicit-def: $rax
+; CHECK-NEXT:    movb %al, %cl
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    ## kill: def $al killed $al killed $eax
-; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
-; CHECK-NEXT:    ## implicit-def: $rcx
-; CHECK-NEXT:    ## kill: def $cl killed $cl killed $rcx
 ; CHECK-NEXT:    movzbw %al, %ax
 ; CHECK-NEXT:    divb %cl
-; CHECK-NEXT:    movb %al, %dl
-; CHECK-NEXT:    movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload
-; CHECK-NEXT:    movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
+; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    ## kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    movzbw %al, %ax
 ; CHECK-NEXT:    divb %cl
 ; CHECK-NEXT:    shrw $8, %ax
 ; CHECK-NEXT:    ## kill: def $al killed $al killed $ax
 ; CHECK-NEXT:    cmpb %cl, %al
 ; CHECK-NEXT:    jae LBB0_2
 ; CHECK-NEXT:  ## %bb.1: ## %"39"
 ; CHECK-NEXT:    movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload
 ; CHECK-NEXT:    movzbl %al, %eax
 ; CHECK-NEXT:    ## implicit-def: $ecx
 ; CHECK-NEXT:    imull %ecx, %eax
+; CHECK-NEXT:    ## implicit-def: $ecx
 ; CHECK-NEXT:    addl %ecx, %eax
+; CHECK-NEXT:    ## implicit-def: $ecx
 ; CHECK-NEXT:    cmpl %ecx, %eax
 ; CHECK-NEXT:    je LBB0_3
 ; CHECK-NEXT:  LBB0_2: ## %"40"
 ; CHECK-NEXT:    ud2
 ; CHECK-NEXT:  LBB0_3: ## %"41"
 ; CHECK-NEXT:    ud2
 entry:
   %0 = trunc i64 undef to i8                      ; <i8> [#uses=3]

llvm/test/CodeGen/X86/fast-isel-constant.ll

-; RUN: llc < %s -mtriple=x86_64-- -O0 | FileCheck %s
-; Make sure fast-isel doesn't reset the materialised constant map
-; across an intrinsic call.
-
-; CHECK: movl $100000
-; CHECK-NOT: movl $100000
-define i1 @test1(i32 %v1, i32 %v2, i32* %X) nounwind {
-entry:
-  %a = shl i32 100000, %v1
-  %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %v2)
-  %ext = extractvalue {i32, i1} %t, 0
-  %sum = shl i32 100000, %ext
-  %obit = extractvalue {i32, i1} %t, 1
-  br i1 %obit, label %overflow, label %normal
-
-normal:
-  store i32 %sum, i32* %X
-  br label %overflow
-
-overflow:
-  ret i1 false
-}
-
-declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)

llvm/test/CodeGen/X86/fast-isel-mem.ll

 ; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin -mcpu=generic | FileCheck %s
 ; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin -mcpu=atom | FileCheck -check-prefix=ATOM %s
 ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64 | FileCheck -check-prefix=ELF64 %s
 
 @src = external dso_preemptable global i32
 
 ; rdar://6653118
 define i32 @loadgv() nounwind {
 entry:
   %0 = load i32, i32* @src, align 4
   %1 = load i32, i32* @src, align 4
         %2 = add i32 %0, %1
         store i32 %2, i32* @src
   ret i32 %2
 ; This should fold one of the loads into the add.
 ; CHECK-LABEL: loadgv:
+; CHECK:  movl  L_src$non_lazy_ptr, %eax
+; CHECK:  movl  (%eax), %eax
 ; CHECK:  movl  L_src$non_lazy_ptr, %ecx
-; CHECK:  movl  (%ecx), %eax
 ; CHECK:  addl  (%ecx), %eax
+; CHECK:  movl  L_src$non_lazy_ptr, %ecx
 ; CHECK:  movl  %eax, (%ecx)
 ; CHECK:  ret
 
 ; ATOM: loadgv:
-; ATOM:   movl    L_src$non_lazy_ptr, %ecx
-; ATOM:         movl    (%ecx), %eax
+; ATOM:         movl    L_src$non_lazy_ptr, %eax
+; ATOM:         movl    (%eax), %eax
+; ATOM:         movl    L_src$non_lazy_ptr, %ecx
 ; ATOM:         addl    (%ecx), %eax
+; ATOM:         movl    L_src$non_lazy_ptr, %ecx
 ; ATOM:         movl    %eax, (%ecx)
 ; ATOM:         ret
 
 ;; dso_preemptable src is loaded via GOT indirection.
 ; ELF64-LABEL: loadgv:
-; ELF64:        movq    src@GOTPCREL(%rip), %rcx
-; ELF64-NEXT:   movl    (%rcx), %eax
+; ELF64:        movq    src@GOTPCREL(%rip), %rax
+; ELF64-NEXT:   movl    (%rax), %eax
+; ELF64-NEXT:   movq    src@GOTPCREL(%rip), %rcx
 ; ELF64-NEXT:   addl    (%rcx), %eax
+; ELF64-NEXT:   movq    src@GOTPCREL(%rip), %rcx
 ; ELF64-NEXT:   movl    %eax, (%rcx)
 ; ELF64-NEXT:   retq
 
 }
 
 %stuff = type { i32 (...)** }
 @LotsStuff = external constant [4 x i32 (...)*]
 

llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll

+;; A parameter list long enough to put one parameter on the stack, plus
+;; at least one float parameter, triggered a corner case that messed up
+;; setting prologue_end.
+;;
+;; Generated using -gmlt from this source:
+;; void call_7i_1f (char c1, float f1, char c2, char c3, char c4, char c5, char c6, short s)
+;; {
+;;   c1 = 'a'; f1 = 0.1; c2 = 5; c3 = 6; c4 = 7;
+;;   c5 = 's'; c6 = 'f'; s = 77;
+;; }
+
+; RUN: llc -mtriple x86_64-- -fast-isel < %s | FileCheck %s
+
+define dso_local void @call_7i_1f(i8 signext %c1, float %f1, i8 signext %c2, i8 signext %c3, i8 signext %c4, i8 signext %c5, i8 signext %c6, i16 signext %s) !dbg !7 {
+entry:
+  %c1.addr = alloca i8, align 1
+  %f1.addr = alloca float, align 4
+  %c2.addr = alloca i8, align 1
+  %c3.addr = alloca i8, align 1
+  %c4.addr = alloca i8, align 1
+  %c5.addr = alloca i8, align 1
+  %c6.addr = alloca i8, align 1
+  %s.addr = alloca i16, align 2
+  store i8 %c1, i8* %c1.addr, align 1
+  store float %f1, float* %f1.addr, align 4
+  store i8 %c2, i8* %c2.addr, align 1
+  store i8 %c3, i8* %c3.addr, align 1
+  store i8 %c4, i8* %c4.addr, align 1
+  store i8 %c5, i8* %c5.addr, align 1
+  store i8 %c6, i8* %c6.addr, align 1
+  store i16 %s, i16* %s.addr, align 2
+  store i8 97, i8* %c1.addr, align 1, !dbg !9
+  store float 0x3FB99999A0000000, float* %f1.addr, align 4, !dbg !10
+  store i8 5, i8* %c2.addr, align 1, !dbg !11
+  store i8 6, i8* %c3.addr, align 1, !dbg !12
+  store i8 7, i8* %c4.addr, align 1, !dbg !13
+  store i8 115, i8* %c5.addr, align 1, !dbg !14
+  store i8 102, i8* %c6.addr, align 1, !dbg !15
+  store i16 77, i16* %s.addr, align 2, !dbg !16
+  ret void, !dbg !17
+}
+
+;; All incoming parameter registers should be homed as part of the prologue.
+; CHECK-DAG: %dil
+; CHECK-DAG: %xmm0
+; CHECK-DAG: %sil
+; CHECK-DAG: %dl
+; CHECK-DAG: %cl
+; CHECK-DAG: %r8b
+; CHECK-DAG: %r9b
+; CHECK:     prologue_end
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "fast-isel-prolog-dbgloc.c", directory: "/home/probinson/projects/scratch")
+!2 = !{}
+!3 = !{i32 7, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{!"clang version 12.0.0"}
+!7 = distinct !DISubprogram(name: "call_7i_1f", scope: !1, file: !1, line: 3, type: !8, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
+!8 = !DISubroutineType(types: !2)
+!9 = !DILocation(line: 5, column: 6, scope: !7)
+!10 = !DILocation(line: 5, column: 16, scope: !7)
+!11 = !DILocation(line: 5, column: 26, scope: !7)
+!12 = !DILocation(line: 5, column: 34, scope: !7)
+!13 = !DILocation(line: 5, column: 42, scope: !7)
+!14 = !DILocation(line: 6, column: 6, scope: !7)
+!15 = !DILocation(line: 6, column: 16, scope: !7)
+!16 = !DILocation(line: 6, column: 25, scope: !7)
+!17 = !DILocation(line: 7, column: 1, scope: !7)

llvm/test/CodeGen/X86/fast-isel-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -O0 | FileCheck %s
 
 ; Make sure we only use the less significant bit of the value that feeds the
 ; select. Otherwise, we may account for a non-zero value whereas the
 ; lsb is zero.
 ; <rdar://problem/15651765>
 
 define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) {
 ; CHECK-LABEL: fastisel_select:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movb %sil, %dl
-; CHECK-NEXT:    movb %dil, %cl
+; CHECK-NEXT:    movb %sil, %al
+; CHECK-NEXT:    movb %dil, %dl
+; CHECK-NEXT:    subb %al, %dl
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    subb %dl, %cl
-; CHECK-NEXT:    testb $1, %cl
 ; CHECK-NEXT:    movl $1204476887, %ecx ## imm = 0x47CADBD7
+; CHECK-NEXT:    testb $1, %dl
 ; CHECK-NEXT:    cmovnel %ecx, %eax
 ; CHECK-NEXT:    retq
   %shuffleInternal15257_8932 = sub i1 %exchSub2211_, %trunc_8766
   %counter_diff1345 = select i1 %shuffleInternal15257_8932, i32 1204476887, i32 0
   ret i32 %counter_diff1345
 }
 

llvm/test/CodeGen/X86/lvi-hardening-loads.ll

 ; X64-NEXT:      andl $-2, %ecx
 ; X64-NEXT:      cmpl %ecx, %eax
 ; X64-NEXT:      jne .LBB0_4
 
 ; X64-NOOPT: # %bb.2: # %for.body
 ; X64-NOOPT-NEXT: # in Loop: Header=BB0_1 Depth=1
 ; X64-NOOPT-NEXT:  lfence
 ; X64-NOOPT-NEXT:      movl -{{[0-9]+}}(%rsp), %eax
-; X64-NOOPT-NEXT:      cltd
 ; X64-NOOPT-NEXT:      movl $2, %ecx
+; X64-NOOPT-NEXT:      cltd
 ; X64-NOOPT-NEXT:      idivl %ecx
 ; X64-NOOPT-NEXT:      cmpl $0, %edx
 ; X64-NOOPT-NEXT:  lfence
 ; X64-NOOPT-NEXT:      jne .LBB0_4
 
 if.then:                                          ; preds = %for.body
   %3 = load i32**, i32*** %secret.addr, align 8
   %4 = load i32, i32* %ret_val, align 4

llvm/test/CodeGen/X86/membarrier.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse -O0 | FileCheck %s
 ; PR9675
 
 define i32 @t() {
 ; CHECK-LABEL: t:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    movl $1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    mfence
 ; CHECK-NEXT:    lock decl -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    mfence
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %i = alloca i32, align 4
   store i32 1, i32* %i, align 4
   fence seq_cst
   %t0 = atomicrmw sub i32* %i, i32 1 monotonic
   fence seq_cst
   ret i32 0
 }

llvm/test/CodeGen/X86/pr32241.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -fast-isel-sink-local-values < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
 
 define i32 @_Z3foov() {
 ; CHECK-LABEL: _Z3foov:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 20
 ; CHECK-NEXT:    movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF
 ; CHECK-NEXT:    movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376
 ; CHECK-NEXT:    movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT:    cmpw $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    cmpw $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    jne .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %lor.rhs
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    jmp .LBB0_2
 ; CHECK-NEXT:  .LBB0_2: # %lor.end
 ; CHECK-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
 ; CHECK-NEXT:    movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload
 ; CHECK-NEXT:    andb $1, %cl
 ; CHECK-NEXT:    movzbl %cl, %ecx
 ; CHECK-NEXT:    cmpl %ecx, %eax
 ; CHECK-NEXT:    setl %al
 ; CHECK-NEXT:    andb $1, %al
-; CHECK-NEXT:    movzbl %al, %eax
-; CHECK-NEXT:    xorl $-1, %eax
-; CHECK-NEXT:    cmpl $0, %eax
+; CHECK-NEXT:    movzbl %al, %ecx
+; CHECK-NEXT:    xorl $-1, %ecx
 ; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    cmpl $0, %ecx
 ; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    jne .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %lor.rhs4
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    jmp .LBB0_4
 ; CHECK-NEXT:  .LBB0_4: # %lor.end5

llvm/test/CodeGen/X86/pr32256.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
 
 @c = external dso_local global i8, align 1
 
 ; Function Attrs: noinline nounwind
 define void @_Z1av() {
 ; CHECK-LABEL: _Z1av:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl $2, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 6
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    movb c, %cl
 ; CHECK-NEXT:    xorb $-1, %cl
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    testb $1, %cl
 ; CHECK-NEXT:    movb %al, (%esp) # 1-byte Spill
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:    jmp .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %land.rhs
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    movb %al, (%esp) # 1-byte Spill

llvm/test/CodeGen/X86/pr32284.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -fast-isel-sink-local-values -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X86-O0
 ; RUN: llc -fast-isel-sink-local-values     -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X64
 ; RUN: llc -fast-isel-sink-local-values -O0 -mtriple=i686-unknown   -mcpu=skx -o - %s | FileCheck %s --check-prefix=686-O0
 ; RUN: llc -fast-isel-sink-local-values     -mtriple=i686-unknown   -mcpu=skx -o - %s | FileCheck %s --check-prefix=686
 
 @c = external dso_local constant i8, align 1
 
 define void @foo() {
 ; X86-O0-LABEL: foo:
 ; X86-O0:       # %bb.0: # %entry
+; X86-O0-NEXT:    movzbl c, %ecx
+; X86-O0-NEXT:    xorl %eax, %eax
+; X86-O0-NEXT:    subl %ecx, %eax
+; X86-O0-NEXT:    movslq %eax, %rcx
 ; X86-O0-NEXT:    xorl %eax, %eax
 ; X86-O0-NEXT:    # kill: def $rax killed $eax
-; X86-O0-NEXT:    xorl %ecx, %ecx
-; X86-O0-NEXT:    movzbl c, %edx
-; X86-O0-NEXT:    subl %edx, %ecx
-; X86-O0-NEXT:    movslq %ecx, %rcx
 ; X86-O0-NEXT:    subq %rcx, %rax
 ; X86-O0-NEXT:    # kill: def $al killed $al killed $rax
 ; X86-O0-NEXT:    cmpb $0, %al
 ; X86-O0-NEXT:    setne %al
 ; X86-O0-NEXT:    andb $1, %al
 ; X86-O0-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; X86-O0-NEXT:    cmpb $0, c
 ; X86-O0-NEXT:    setne %al

llvm/test/CodeGen/X86/pr32340.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -fast-isel-sink-local-values -O0 -mtriple=x86_64-unknown-linux-gnu -fast-isel-abort=1 -o - %s | FileCheck %s -check-prefix=X64
 
 @var_825 = external dso_local global i16, align 2
 @var_32 = external dso_local global i16, align 2
 @var_901 = external dso_local global i16, align 2
 @var_826 = external dso_local global i64, align 8
 @var_57 = external dso_local global i64, align 8
 @var_900 = external dso_local global i16, align 2
 @var_28 = external dso_local constant i64, align 8
 @var_827 = external dso_local global i16, align 2
 
 define void @foo() {
 ; X64-LABEL: foo:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    # kill: def $rax killed $eax
 ; X64-NEXT:    movw $0, var_825
-; X64-NEXT:    movzwl var_32, %edx
-; X64-NEXT:    movzwl var_901, %ecx
-; X64-NEXT:    movl %edx, %esi
-; X64-NEXT:    xorl %ecx, %esi
-; X64-NEXT:    movl %edx, %ecx
-; X64-NEXT:    xorl %esi, %ecx
-; X64-NEXT:    addl %edx, %ecx
-; X64-NEXT:    movslq %ecx, %rcx
-; X64-NEXT:    movq %rcx, var_826
 ; X64-NEXT:    movzwl var_32, %ecx
-; X64-NEXT:    # kill: def $rcx killed $ecx
-; X64-NEXT:    movzwl var_901, %edx
-; X64-NEXT:    xorl $51981, %edx # imm = 0xCB0D
-; X64-NEXT:    movslq %edx, %rsi
-; X64-NEXT:    movabsq $-1142377792914660288, %rdx # imm = 0xF02575732E06E440
-; X64-NEXT:    xorq %rdx, %rsi
-; X64-NEXT:    movq %rcx, %rdx
-; X64-NEXT:    xorq %rsi, %rdx
-; X64-NEXT:    xorq $-1, %rdx
+; X64-NEXT:    movzwl var_901, %eax
+; X64-NEXT:    movl %ecx, %edx
+; X64-NEXT:    xorl %eax, %edx
+; X64-NEXT:    movl %ecx, %eax
+; X64-NEXT:    xorl %edx, %eax
+; X64-NEXT:    addl %ecx, %eax
+; X64-NEXT:    cltq
+; X64-NEXT:    movq %rax, var_826
+; X64-NEXT:    movzwl var_32, %eax
+; X64-NEXT:    # kill: def $rax killed $eax
+; X64-NEXT:    movzwl var_901, %ecx
+; X64-NEXT:    xorl $51981, %ecx # imm = 0xCB0D
+; X64-NEXT:    movslq %ecx, %rdx
+; X64-NEXT:    movabsq $-1142377792914660288, %rcx # imm = 0xF02575732E06E440
+; X64-NEXT:    xorq %rcx, %rdx
+; X64-NEXT:    movq %rax, %rcx
 ; X64-NEXT:    xorq %rdx, %rcx
-; X64-NEXT:    movq %rcx, %rdx
-; X64-NEXT:    orq var_57, %rdx
-; X64-NEXT:    orq %rdx, %rcx
-; X64-NEXT:    # kill: def $cx killed $cx killed $rcx
-; X64-NEXT:    movw %cx, var_900
+; X64-NEXT:    xorq $-1, %rcx
+; X64-NEXT:    xorq %rcx, %rax
+; X64-NEXT:    movq %rax, %rcx
+; X64-NEXT:    orq var_57, %rcx
+; X64-NEXT:    orq %rcx, %rax
+; X64-NEXT:    # kill: def $ax killed $ax killed $rax
+; X64-NEXT:    movw %ax, var_900
+; X64-NEXT:    xorl %eax, %eax
+; X64-NEXT:    # kill: def $rax killed $eax
 ; X64-NEXT:    cmpq var_28, %rax
 ; X64-NEXT:    setne %al
 ; X64-NEXT:    andb $1, %al
 ; X64-NEXT:    movzbl %al, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    movw %ax, var_827
 ; X64-NEXT:    retq
 entry:

llvm/test/CodeGen/X86/pr44749.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.15.0 -O0 | FileCheck %s
 
 define i32 @a() {
 ; CHECK-LABEL: a:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    ## kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    callq _b
 ; CHECK-NEXT:    cvtsi2sd %eax, %xmm0
 ; CHECK-NEXT:    movq _calloc@{{.*}}(%rip), %rax
 ; CHECK-NEXT:    subq $-1, %rax
 ; CHECK-NEXT:    setne %al
 ; CHECK-NEXT:    movzbl %al, %eax

llvm/test/CodeGen/X86/volatile.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s
-; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s --check-prefixes=ALL,OPT
+; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | FileCheck %s --check-prefixes=ALL,NOOPT
 
 @x = external dso_local global double
 
 define void @foo() nounwind  {
-; CHECK-LABEL: foo:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    xorps %xmm0, %xmm0
-; CHECK-NEXT:    movsd %xmm0, x
-; CHECK-NEXT:    movsd %xmm0, x
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    retl
+; OPT-LABEL: foo:
+; OPT:       # %bb.0:
+; OPT-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; OPT-NEXT:    xorps %xmm0, %xmm0
+; OPT-NEXT:    movsd %xmm0, x
+; OPT-NEXT:    movsd %xmm0, x
+; OPT-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; OPT-NEXT:    retl
+;
+; NOOPT-LABEL: foo:
+; NOOPT:       # %bb.0:
+; NOOPT-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; NOOPT-NEXT:    xorps %xmm0, %xmm0
+; NOOPT-NEXT:    movsd %xmm0, x
+; NOOPT-NEXT:    xorps %xmm0, %xmm0
+; NOOPT-NEXT:    movsd %xmm0, x
+; NOOPT-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; NOOPT-NEXT:    retl
   %a = load volatile double, double* @x
   store volatile double 0.0, double* @x
   store volatile double 0.0, double* @x
   %b = load volatile double, double* @x
   ret void
 }
 
 define void @bar() nounwind  {
-; CHECK-LABEL: bar:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    retl
+; ALL-LABEL: bar:
+; ALL:       # %bb.0:
+; ALL-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; ALL-NEXT:    retl
   %c = load volatile double, double* @x
   ret void
 }

llvm/test/DebugInfo/COFF/lines-bb-start.ll

 }
 
 ; CHECK-LABEL: _lea_dbg_value:
 ; CHECK:         .cv_loc {{.*}} # t.c:4:5
 ; CHECK:         jmp     LBB{{.*}}
 ; CHECK: LBB2_{{.*}}:                                 # %if.end
 ; CHECK-NEXT:    .cv_loc {{.*}} # t.c:5:3
 ; CHECK:         leal 4(%esp), %[[reg:[^ ]*]]
-; CHECK:         #DEBUG_VALUE: lea_dbg_value:v <- [DW_OP_deref] $[[reg]]
 ; CHECK:         movl    %[[reg]], (%esp)
 ; CHECK:         calll   _use_i32
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!3, !4, !5, !6}
 !llvm.ident = !{!7}
 
 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 5.0.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)

llvm/test/DebugInfo/Mips/delay-slot.ll

 ; }
 
 ; CHECK: Address            Line   Column File   ISA Discriminator Flags
 ; CHECK: ------------------ ------ ------ ------ --- ------------- -------------
 ; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000004      2      0      1   0             0  is_stmt prologue_end
 ; CHECK: 0x0000000000000020      3      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000030      4      0      1   0             0  is_stmt
+; CHECK: 0x0000000000000040      0      0      1   0             0
 ; CHECK: 0x0000000000000048      5      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000050      5      0      1   0             0  is_stmt end_sequence
 
 
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips--linux-gnu"
 
 ; Function Attrs: nounwind

llvm/test/DebugInfo/X86/fission-ranges.ll

 ; CHECK: DW_AT_location [DW_FORM_sec_offset]   ([[E:0x[0-9a-z]*]]:
 ; CHECK: DW_AT_location [DW_FORM_sec_offset]   ([[B:0x[0-9a-z]*]]:
 ; CHECK: DW_AT_location [DW_FORM_sec_offset]   ([[D:0x[0-9a-z]*]]:
 ; CHECK: DW_AT_ranges [DW_FORM_sec_offset]   (0x00000000
 ; CHECK-NOT: .debug_loc contents:
 ; CHECK-NOT: Beginning address offset
 ; CHECK: .debug_loc.dwo contents:
 
 ; Don't assume these locations are entirely correct - feel free to update them
 ; if they've changed due to a bugfix, change in register allocation, etc.
 
 ; CHECK:      [[A]]:
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000002, 0x0000000f): DW_OP_consts +0, DW_OP_stack_value
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000003, 0x0000000b): DW_OP_reg0 RAX
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000004, 0x00000012): DW_OP_breg7 RSP-4
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000001, 0x00000011): DW_OP_consts +0, DW_OP_stack_value
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000002, 0x0000000b): DW_OP_reg0 RAX
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000003, 0x00000012): DW_OP_breg7 RSP-4
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[E]]:
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000005, 0x0000000b): DW_OP_reg0 RAX
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000006, 0x0000005a): DW_OP_breg7 RSP-48
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000004, 0x0000000b): DW_OP_reg0 RAX
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000005, 0x0000005a): DW_OP_breg7 RSP-48
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[B]]:
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000007, 0x0000000b): DW_OP_reg0 RAX
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000008, 0x00000042): DW_OP_breg7 RSP-24
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000006, 0x0000000b): DW_OP_reg0 RAX
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000007, 0x00000042): DW_OP_breg7 RSP-24
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[D]]:
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000009, 0x0000000b): DW_OP_reg0 RAX
-; CHECK-NEXT:   DW_LLE_startx_length (0x0000000a, 0x0000002a): DW_OP_breg7 RSP-12
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000008, 0x0000000b): DW_OP_reg0 RAX
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000009, 0x0000002a): DW_OP_breg7 RSP-12
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 
 ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo)
 ; HDR-NOT: .rela.{{.*}}.dwo
 
 ; Make sure we have enough stuff in the debug_addr to cover the address indexes
-; (10 is the last index in debug_loc.dwo, making 11 entries of 8 bytes each,
-; 11 * 8 == 88 base 10 == 58 base 16)
+; (9 is the last index in debug_loc.dwo, making 10 entries of 8 bytes each,
+; 10 * 8 == 80 base 10 == 50 base 16)
 
-; HDR: .debug_addr 00000058
+; HDR: .debug_addr 00000050
 ; HDR-NOT: .rela.{{.*}}.dwo
 
 ; Check for the existence of a DWARF v5-style range list table in the .debug_rnglists
 ; section and that the compile unit has a DW_AT_rnglists_base attribute.
 ; The table should contain at least one rangelist with at least 2 individual ranges.
 
 ; V5RNGLISTS:      .debug_info contents:
 ; V5RNGLISTS:      DW_TAG_compile_unit