[X86] __builtin_cpu_supports: support x86-64{,-v2,-v3,-v4}

[MaskRay]

Summary

GCC 12 (https://gcc.gnu.org/PR101696) allows
__builtin_cpu_supports("x86-64") (and -v2 -v3 -v4).
This patch ports the feature.

• Add FEATURE_X86_64_{BASELINE,V2,V3,V4} to enum ProcessorFeatures, but keep CPU_FEATURE_MAX unchanged to make FeatureInfos/FeatureInfos_WithPLUS happy.
• Change validateCpuSupports to allow x86-64{,-v2,-v3,-v4}
• Change getCpuSupportsMask to return std::array<uint32_t, 4> where x86-64{,-v2,-v3,-v4} set bits FEATURE_X86_64_{BASELINE,V2,V3,V4}.
• target("x86-64") and cpu_dispatch(x86_64) are invalid. Tested by commit 9de3b35ac9159d5bae6e6796cb91e4f877a07189

Close https://github.com/llvm/llvm-project/issues/59961

[pengfei]

llvm/include/llvm/TargetParser/X86TargetParser.h

63

Not needed.

llvm/lib/TargetParser/X86TargetParser.cpp

718–719

Should we use vector for future expansion, or add an assert to make sure it won't exceed current limitation?

[MaskRay]

add assert

[pengfei]

LGTM.

[MaskRay]

rebase after precommitting target("x86-64") and cpu_specific(x86_64) attributes tests
add __builtin_cpu_supports x86-64-v5 test

[MaskRay]

llvm/lib/TargetParser/X86TargetParser.cpp

718–719

A resizable vector does not simplify code here. I've added an assert.

clang/lib/Basic/Targets/X86.cpp

 // We can't use a generic validation scheme for the features accepted here
 // versus subtarget features accepted in the target attribute because the
 // bitfield structure that's initialized in the runtime only supports the
 // below currently rather than the full range of subtarget features. (See
 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
   return llvm::StringSwitch<bool>(FeatureStr)
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
+#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true)
 #include "llvm/TargetParser/X86TargetParser.def"
       .Default(false);
 }
 
 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
   return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
   .Case(STR, llvm::X86::FEATURE_##ENUM)

clang/lib/CodeGen/CGBuiltin.cpp

 
 Value *CodeGenFunction::EmitX86CpuSupports(const CallExpr *E) {
   const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
   StringRef FeatureStr = cast<StringLiteral>(FeatureExpr)->getString();
   return EmitX86CpuSupports(FeatureStr);
 }
 
 Value *CodeGenFunction::EmitX86CpuSupports(ArrayRef<StringRef> FeatureStrs) {
-  uint64_t Mask = llvm::X86::getCpuSupportsMask(FeatureStrs);
-  std::array<uint32_t, 4> FeatureMask{Lo_32(Mask), Hi_32(Mask), 0, 0};
-  return EmitX86CpuSupports(FeatureMask);
+  return EmitX86CpuSupports(llvm::X86::getCpuSupportsMask(FeatureStrs));
 }
 
 llvm::Value *
 CodeGenFunction::EmitX86CpuSupports(std::array<uint32_t, 4> FeatureMask) {
   Value *Result = Builder.getTrue();
   if (FeatureMask[0] != 0) {
     // Matching the struct layout from the compiler-rt/libgcc structure that is
     // filled in:

clang/lib/CodeGen/CodeGenFunction.cpp

 }
 
 llvm::Value *CodeGenFunction::FormX86ResolverCondition(
     const MultiVersionResolverOption &RO) {
   llvm::Value *Condition = nullptr;
 
   if (!RO.Conditions.Architecture.empty()) {
     StringRef Arch = RO.Conditions.Architecture;
-    std::array<uint32_t, 4> Mask{};
-    // If arch= specifies an x86-64 micro-architecture level, test a special
-    // feature named FEATURE_X86_64_*, otherwise we use __builtin_cpu_is.
-    if (Arch.consume_front("x86-64")) {
-      if (Arch.empty()) // FEATURE_X86_64_BASELINE 95=2*32+31
-        Mask[2] = 1u << 31;
-      else if (Arch == "-v2") // FEATURE_X86_64_V2 96==3*32+0
-        Mask[3] = 1u << 0;
-      else if (Arch == "-v3") // FEATURE_X86_64_V3 97==3*32+1
-        Mask[3] = 1u << 1;
-      else if (Arch == "-v4") // FEATURE_X86_64_V3 98==3*32+2
-        Mask[3] = 1u << 2;
-      else
-        llvm_unreachable("invalid x86-64 micro-architecture level");
-      Condition = EmitX86CpuSupports(Mask);
-    } else {
+    // If arch= specifies an x86-64 micro-architecture level, test the feature
+    // with __builtin_cpu_supports, otherwise use __builtin_cpu_is.
+    if (Arch.starts_with("x86-64"))
+      Condition = EmitX86CpuSupports({Arch});
       Condition = EmitX86CpuIs(Arch);
-    }
-  }
 
   if (!RO.Conditions.Features.empty()) {
     llvm::Value *FeatureCond = EmitX86CpuSupports(RO.Conditions.Features);
     Condition =
         Condition ? Builder.CreateAnd(Condition, FeatureCond) : FeatureCond;
   }
   return Condition;
 }

clang/lib/CodeGen/CodeGenModule.cpp

llvm::stable_sort(
                llvm::X86::getCpuSupportsMask(RHS.Conditions.Features);
       });
 
   // If the list contains multiple 'default' versions, such as when it contains
   // 'pentium' and 'generic', don't emit the call to the generic one (since we
   // always run on at least a 'pentium'). We do this by deleting the 'least
   // advanced' (read, lowest mangling letter).
   while (Options.size() > 1 &&
-         llvm::X86::getCpuSupportsMask(
-             (Options.end() - 2)->Conditions.Features) == 0) {
+         llvm::all_of(llvm::X86::getCpuSupportsMask(
+                          (Options.end() - 2)->Conditions.Features),
+                      [](auto X) { return X == 0; })) {
     StringRef LHSName = (Options.end() - 2)->Function->getName();
     StringRef RHSName = (Options.end() - 1)->Function->getName();
     if (LHSName.compare(RHSName) < 0)
       Options.erase(Options.end() - 2);
     else
       Options.erase(Options.end() - 1);
   }
 

clang/test/CodeGen/builtin-cpu-supports.c

int main(void) {
   // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
   // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
   // CHECK: = icmp eq i32 [[AND]], 1
 
   return 0;
 }
 
 // CHECK: declare dso_local void @__cpu_indicator_init()
+
+// CHECK-LABEL: define{{.*}} @baseline(
+// CHECK:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
+// CHECK-NEXT:    and i32 [[LOAD]], -2147483648
+int baseline() { return __builtin_cpu_supports("x86-64"); }
+
+// CHECK-LABEL: define{{.*}} @v2(
+// CHECK:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-NEXT:    and i32 [[LOAD]], 1
+int v2() { return __builtin_cpu_supports("x86-64-v2"); }
+
+// CHECK-LABEL: define{{.*}} @v3(
+// CHECK:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-NEXT:    and i32 [[LOAD]], 2
+int v3() { return __builtin_cpu_supports("x86-64-v3"); }
+
+// CHECK-LABEL: define{{.*}} @v4(
+// CHECK:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-NEXT:    and i32 [[LOAD]], 4
+int v4() { return __builtin_cpu_supports("x86-64-v4"); }

clang/test/Sema/attr-cpuspecific.c

 
 int __attribute__((cpu_specific(atom))) good_overload6(void);
 // expected-error@+1 {{attribute 'cpu_specific' multiversioning cannot be combined with attribute 'overloadable'}}
 int __attribute__((__overloadable__)) __attribute__((cpu_specific(ivybridge))) good_overload6(int);
 
 // expected-error@+1 {{attribute 'cpu_specific' multiversioning cannot be combined with attribute 'overloadable'}}
 int __attribute__((__overloadable__)) __attribute__((cpu_specific(atom))) good_overload7(void);
 int __attribute__((cpu_specific(ivybridge))) good_overload7(int);
+
+// expected-error@+1 {{invalid option 'x86_64'}}
+int __attribute__((cpu_specific(x86_64))) baseline(void);
+// expected-error@+1 {{invalid option 'x86_64_v2'}}
+int __attribute__((cpu_specific(x86_64_v2))) baseline(void);

clang/test/Sema/attr-target.c

 int __attribute__((target("arch=hiss,arch=woof"))) pine_tree(void) { return 4; }
 //expected-warning@+1 {{duplicate 'arch=' in the 'target' attribute string; 'target' attribute ignored}}
 int __attribute__((target("arch=ivybridge,arch=haswell"))) oak_tree(void) { return 4; }
 //expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
 int __attribute__((target("branch-protection=none"))) birch_tree(void) { return 5; }
 //expected-warning@+1 {{unknown tune CPU 'hiss' in the 'target' attribute string; 'target' attribute ignored}}
 int __attribute__((target("tune=hiss,tune=woof"))) apple_tree(void) { return 4; }
 
+//expected-warning@+1 {{unsupported 'x86-64' in the 'target' attribute string}}
+void __attribute__((target("x86-64"))) baseline(void) {}
+//expected-warning@+1 {{unsupported 'x86-64-v2' in the 'target' attribute string}}
+void __attribute__((target("x86-64-v2"))) v2(void) {}
+
 #elifdef __aarch64__
 
 int __attribute__((target("sve,arch=armv8-a"))) foo(void) { return 4; }
 //expected-error@+1 {{'target' attribute takes one argument}}
 int __attribute__((target())) bar(void) { return 4; }
 // no warning, tune is supported for aarch64
 int __attribute__((target("tune=cortex-a710"))) baz(void) { return 4; }
 //expected-warning@+1 {{unsupported 'fpmath=' in the 'target' attribute string; 'target' attribute ignored}}

llvm/include/llvm/TargetParser/X86TargetParser.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGETPARSER_X86TARGETPARSER_H
 #define LLVM_TARGETPARSER_X86TARGETPARSER_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringMap.h"
+#include <array>
 
 namespace llvm {
 template <typename T> class SmallVectorImpl;
 class StringRef;
 
 namespace X86 {
 
 // This should be kept in sync with libcc/compiler-rt as its included by clang
#include "llvm/TargetParser/X86TargetParser.def"
   CPU_SUBTYPE_MAX
 };
 
 // This should be kept in sync with libcc/compiler-rt as it should be used
 // by clang as a proxy for what's in libgcc/compiler-rt.
 enum ProcessorFeatures {
 #define X86_FEATURE(ENUM, STRING) FEATURE_##ENUM,
 #include "llvm/TargetParser/X86TargetParser.def"
-  CPU_FEATURE_MAX
+  CPU_FEATURE_MAX,
+
+#define X86_MICROARCH_LEVEL(ENUM, STRING, PRIORITY) FEATURE_##ENUM = PRIORITY,
+#include "llvm/TargetParser/X86TargetParser.def"
 };
 
 enum CPUKind {
   CK_None,
   CK_i386,
   CK_i486,
   CK_WinChipC6,
   CK_WinChip2,

 
 /// Set or clear entries in \p Features that are implied to be enabled/disabled
 /// by the provided \p Feature.
 void updateImpliedFeatures(StringRef Feature, bool Enabled,
                            StringMap<bool> &Features);
 
 char getCPUDispatchMangling(StringRef Name);
 bool validateCPUSpecificCPUDispatch(StringRef Name);
-uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
+std::array<uint32_t, 4> getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
 unsigned getFeaturePriority(ProcessorFeatures Feat);
 
 } // namespace X86
 } // namespace llvm
 
 #endif

llvm/include/llvm/TargetParser/X86TargetParser.def

 #ifndef X86_FEATURE_COMPAT
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) X86_FEATURE(ENUM, STR)
 #endif
 
 #ifndef X86_FEATURE
 #define X86_FEATURE(ENUM, STR)
 #endif
 
+#ifndef X86_MICROARCH_LEVEL
+#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY)
+#endif
+
 X86_FEATURE_COMPAT(CMOV,            "cmov",                  0)
 X86_FEATURE_COMPAT(MMX,             "mmx",                   1)
 X86_FEATURE_COMPAT(POPCNT,          "popcnt",                9)
 X86_FEATURE_COMPAT(SSE,             "sse",                   2)
 X86_FEATURE_COMPAT(SSE2,            "sse2",                  3)
 X86_FEATURE_COMPAT(SSE3,            "sse3",                  4)
 X86_FEATURE_COMPAT(SSSE3,           "ssse3",                 5)
 X86_FEATURE_COMPAT(SSE4_1,          "sse4.1",                7)

 X86_FEATURE       (SM4,             "sm4")
 X86_FEATURE       (AVXVNNIINT16,    "avxvnniint16")
 // These features aren't really CPU features, but the frontend can set them.
 X86_FEATURE       (RETPOLINE_EXTERNAL_THUNK,    "retpoline-external-thunk")
 X86_FEATURE       (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
 X86_FEATURE       (RETPOLINE_INDIRECT_CALLS,    "retpoline-indirect-calls")
 X86_FEATURE       (LVI_CFI,                     "lvi-cfi")
 X86_FEATURE       (LVI_LOAD_HARDENING,          "lvi-load-hardening")
+
+X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",               95)
+X86_MICROARCH_LEVEL(X86_64_V2,      "x86-64-v2",            96)
+X86_MICROARCH_LEVEL(X86_64_V3,      "x86-64-v3",            97)
+X86_MICROARCH_LEVEL(X86_64_V4,      "x86-64-v4",            98)
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE
+#undef X86_MICROARCH_LEVEL

llvm/lib/TargetParser/X86TargetParser.cpp

 }
 
 bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
   auto I = llvm::find_if(Processors,
                          [&](const ProcInfo &P) { return P.Name == Name; });
   return I != std::end(Processors);
 }
 
-uint64_t llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
+std::array<uint32_t, 4>
+llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
   // Processor features and mapping to processor feature value.
-  uint64_t FeaturesMask = 0;
-  for (const StringRef &FeatureStr : FeatureStrs) {
+  std::array<uint32_t, 4> FeatureMask{};
+  for (StringRef FeatureStr : FeatureStrs) {
     unsigned Feature = StringSwitch<unsigned>(FeatureStr)
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
   .Case(STR, llvm::X86::FEATURE_##ENUM)
+#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY)                               \
+  .Case(STR, llvm::X86::FEATURE_##ENUM)
 #include "llvm/TargetParser/X86TargetParser.def"
         ;
-    FeaturesMask |= (1ULL << Feature);
+    assert(Feature / 32 < FeatureMask.size());
+    FeatureMask[Feature / 32] |= 1U << (Feature % 32);
   }
-  return FeaturesMask;
+  return FeatureMask;
 }
 
 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
 #ifndef NDEBUG
   // Check that priorities are set properly in the .def file. We expect that
   // "compat" features are assigned non-duplicate consecutive priorities
   // starting from zero (0, 1, ..., num_features - 1).
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,