[RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[luke]

Summary

These correspond to ROTL/ROTR nodes

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

257

What about rotl by immediate using vror.vi with SEW-rotateamt?

258

vror has a uimm6.

[luke]

Add patterns for rotl using vror.vi with negated immediate
Use uimm6

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3006 ↗

(On Diff #541134)

Don't template this, pass the value as an argument. There show be a form of isUInt that takes an argument.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3006 ↗

(On Diff #541134)

"show" was supposed to be "should"

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3006 ↗

(On Diff #541134)

You can make a remplate version of selectVSplatUimm that takes a template parameter and forwards the argument as a non-template parameter.

See for example

bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);                   
template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {        
  return selectSExtBits(N, Bits, Val);                                         
}

Basically I'm trying to avoid the binary bloat from duplicating a function that barely cares about the number of bits.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

86

I suspect the assembler won't parse this.

[luke]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3006 ↗

(On Diff #541134)

Yeah that's much better, done and will include in the next diff

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

86

Your suspicion is correct. The verifier doesn't seem to like 64 - uimm either:

*** Bad machine code: Invalid immediate ***
- function:    vror_vi_rotl_nxv1i8
- basic block: %bb.0  (0x15b0a5970)
- instruction: %1:vr = PseudoVROR_VI_MF8 %2:vr(tied-def 0), %0:vr, 63, -1, 3, 3

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

204

Need to pass <uimm6> to VPseudoVALU_VV_VX_VI

[luke]

Remove template in selectVSplatUImm and fix immediate being signed

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

455 ↗

(On Diff #541880)

Out of an abundance of paranoia can you mask this with 0x3f. The original match was for a uimm which would allow 0-63. 0 would be a noop roate. I don't trust that the 0 won't show up since we are on target nodes and don't have DAG combines to clean it up if the 0 appears late. 64 - 0 would be 64 which would be an invalid value for the assembly. Masking 64 to 0 would prevent that from being a problem.

[luke]

Mask off immediate

llvm/lib/Target/RISCV/RISCVInstrInfo.td

455 ↗

(On Diff #541880)

Good catch, done

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

for (MVT VT : IntVecVTs) {
 
       // nxvXi64 MULHS/MULHU requires the V extension instead of Zve64*.
       if (VT.getVectorElementType() == MVT::i64 && !Subtarget.hasStdExtV())
         setOperationAction({ISD::MULHU, ISD::MULHS}, VT, Expand);
 
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT,
                          Legal);
 
-      setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
-
       setOperationAction({ISD::VP_FSHL, ISD::VP_FSHR}, VT, Expand);
 
       // Custom-lower extensions and truncations from/to mask types.
       setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
                          VT, Custom);
 
       // RVV has native int->float & float->int conversions where the
       // element type sizes are within one power-of-two of each other. Any
for (MVT VT : IntVecVTs) {
         // Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
         // range of f32.
         EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
         if (isTypeLegal(FloatVT)) {
           setOperationAction(
               {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
               Custom);
         }
+
+        setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
       }
     }
 
     // Expand various CCs to best match the RVV ISA, which natively supports UNE
     // but no other unordered comparisons, and supports all ordered comparisons
     // except ONE. Additionally, we expand GT,OGT,GE,OGE for optimization
     // purposes; they are expanded to their swapped-operand CCs (LT,OLT,LE,OLE),
     // and we pattern-match those back to the "original", swapping operands once

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

 }
 
 defm PseudoVBREV : VPseudoUnaryV_V;
 defm PseudoVREV8 : VPseudoUnaryV_V;
 defm PseudoVCLZ : VPseudoUnaryV_V;
 defm PseudoVCTZ : VPseudoUnaryV_V;
 defm PseudoVCPOP : VPseudoUnaryV_V;
 
+defm PseudoVROL : VPseudoVALU_VV_VX;
+defm PseudoVROR : VPseudoVALU_VV_VX_VI;
+
 //===----------------------------------------------------------------------===//
 // SDNode patterns
 //===----------------------------------------------------------------------===//
 
 multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name> {
   foreach vti = AllIntegerVectors in {
     let Predicates = !listconcat([HasStdExtZvbb],
                                  GetVTypePredicates<vti>.Predicates) in {

 }
 
 defm : VPatUnarySDNode_V<bitreverse, "PseudoVBREV">;
 defm : VPatUnarySDNode_V<bswap, "PseudoVREV8">;
 defm : VPatUnarySDNode_V<ctlz, "PseudoVCLZ">;
 defm : VPatUnarySDNode_V<cttz, "PseudoVCTZ">;
 defm : VPatUnarySDNode_V<ctpop, "PseudoVCPOP">;
 
+defm : VPatBinarySDNode_VV_VX<rotl, "PseudoVROL">;
+defm : VPatBinarySDNode_VV_VX_VI<rotr, "PseudoVROR", uimm5>;
+
 //===----------------------------------------------------------------------===//
 // VL patterns
 //===----------------------------------------------------------------------===//
 
 multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name> {
   foreach vti = AllIntegerVectors in {
     let Predicates = !listconcat([HasStdExtZvbb],
                                  GetVTypePredicates<vti>.Predicates) in {

llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
+
+declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
+
+define <vscale x 1 x i8> @vrol_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv1i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)
+  ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv1i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
+  ret <vscale x 1 x i8> %x
+}
+
+declare <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>)
+
+define <vscale x 2 x i8> @vrol_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv2i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)
+  ret <vscale x 2 x i8> %x
+}
+
+define <vscale x 2 x i8> @vrol_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv2i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)
+  ret <vscale x 2 x i8> %x
+}
+
+declare <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>)
+
+define <vscale x 4 x i8> @vrol_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv4i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)
+  ret <vscale x 4 x i8> %x
+}
+
+define <vscale x 4 x i8> @vrol_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv4i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)
+  ret <vscale x 4 x i8> %x
+}
+
+declare <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>)
+
+define <vscale x 8 x i8> @vrol_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv8i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
+  ret <vscale x 8 x i8> %x
+}
+
+define <vscale x 8 x i8> @vrol_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv8i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)
+  ret <vscale x 8 x i8> %x
+}
+
+declare <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+
+define <vscale x 16 x i8> @vrol_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vand.vi v12, v10, 7
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv16i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+  ret <vscale x 16 x i8> %x
+}
+
+define <vscale x 16 x i8> @vrol_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vi v12, v10, 7
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv16i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)
+  ret <vscale x 16 x i8> %x
+}
+
+declare <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>)
+
+define <vscale x 32 x i8> @vrol_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vand.vi v16, v12, 7
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv32i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)
+  ret <vscale x 32 x i8> %x
+}
+
+define <vscale x 32 x i8> @vrol_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vand.vi v16, v12, 7
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv32i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
+  %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)
+  ret <vscale x 32 x i8> %x
+}
+
+declare <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>)
+
+define <vscale x 64 x i8> @vrol_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
+; CHECK-LABEL: vrol_vv_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vand.vi v24, v16, 7
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv64i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
+  ret <vscale x 64 x i8> %x
+}
+
+define <vscale x 64 x i8> @vrol_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vand.vi v24, v16, 7
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 7
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv64i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
+  %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)
+  ret <vscale x 64 x i8> %x
+}
+
+declare <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>)
+
+define <vscale x 1 x i16> @vrol_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv1i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)
+  ret <vscale x 1 x i16> %x
+}
+
+define <vscale x 1 x i16> @vrol_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv1i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)
+  ret <vscale x 1 x i16> %x
+}
+
+declare <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
+
+define <vscale x 2 x i16> @vrol_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv2i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)
+  ret <vscale x 2 x i16> %x
+}
+
+define <vscale x 2 x i16> @vrol_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv2i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)
+  ret <vscale x 2 x i16> %x
+}
+
+declare <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>)
+
+define <vscale x 4 x i16> @vrol_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv4i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
+  ret <vscale x 4 x i16> %x
+}
+
+define <vscale x 4 x i16> @vrol_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv4i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)
+  ret <vscale x 4 x i16> %x
+}
+
+declare <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
+
+define <vscale x 8 x i16> @vrol_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vand.vi v12, v10, 15
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+  ret <vscale x 8 x i16> %x
+}
+
+define <vscale x 8 x i16> @vrol_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vi v12, v10, 15
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)
+  ret <vscale x 8 x i16> %x
+}
+
+declare <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>)
+
+define <vscale x 16 x i16> @vrol_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vand.vi v16, v12, 15
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv16i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
+  ret <vscale x 16 x i16> %x
+}
+
+define <vscale x 16 x i16> @vrol_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vand.vi v16, v12, 15
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv16i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)
+  ret <vscale x 16 x i16> %x
+}
+
+declare <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>)
+
+define <vscale x 32 x i16> @vrol_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
+; CHECK-LABEL: vrol_vv_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT:    vand.vi v24, v16, 15
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv32i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
+  ret <vscale x 32 x i16> %x
+}
+
+define <vscale x 32 x i16> @vrol_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {
+; CHECK-LABEL: vrol_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vand.vi v24, v16, 15
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 15
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv32i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
+  %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)
+  ret <vscale x 32 x i16> %x
+}
+
+declare <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>)
+
+define <vscale x 1 x i32> @vrol_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
+; CHECK-LABEL: vrol_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv1i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)
+  ret <vscale x 1 x i32> %x
+}
+
+define <vscale x 1 x i32> @vrol_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv1i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT:    vsll.vx v9, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv1i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v9, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV64-NEXT:    vsll.vv v10, v8, v10
+; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv1i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)
+  ret <vscale x 1 x i32> %x
+}
+
+declare <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @vrol_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+; CHECK-LABEL: vrol_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv2i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  ret <vscale x 2 x i32> %x
+}
+
+define <vscale x 2 x i32> @vrol_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT:    vsll.vx v9, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v9, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV64-NEXT:    vsll.vv v10, v8, v10
+; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv2i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)
+  ret <vscale x 2 x i32> %x
+}
+
+declare <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+
+define <vscale x 4 x i32> @vrol_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: vrol_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vand.vx v12, v10, a0
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vx v10, v10, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+  ret <vscale x 4 x i32> %x
+}
+
+define <vscale x 4 x i32> @vrol_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT:    vsll.vx v10, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v10, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v12, v10, a0
+; CHECK-RV64-NEXT:    vsll.vv v12, v8, v12
+; CHECK-RV64-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-RV64-NEXT:    vand.vx v10, v10, a0
+; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)
+  ret <vscale x 4 x i32> %x
+}
+
+declare <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>)
+
+define <vscale x 8 x i32> @vrol_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
+; CHECK-LABEL: vrol_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vand.vx v16, v12, a0
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
+  ret <vscale x 8 x i32> %x
+}
+
+define <vscale x 8 x i32> @vrol_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
+; CHECK-RV32-NEXT:    vsll.vx v12, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v12, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v16, v12, a0
+; CHECK-RV64-NEXT:    vsll.vv v16, v8, v16
+; CHECK-RV64-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-RV64-NEXT:    vand.vx v12, v12, a0
+; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)
+  ret <vscale x 8 x i32> %x
+}
+
+declare <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>)
+
+define <vscale x 16 x i32> @vrol_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
+; CHECK-LABEL: vrol_vv_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vand.vx v24, v16, a0
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv16i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
+  ret <vscale x 16 x i32> %x
+}
+
+define <vscale x 16 x i32> @vrol_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv16i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-RV32-NEXT:    vsll.vx v16, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv16i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v16, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v24, v16, a0
+; CHECK-RV64-NEXT:    vsll.vv v24, v8, v24
+; CHECK-RV64-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-RV64-NEXT:    vand.vx v16, v16, a0
+; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-RV64-NEXT:    vor.vv v8, v24, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vx_nxv16i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)
+  ret <vscale x 16 x i32> %x
+}
+
+declare <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>)
+
+define <vscale x 1 x i64> @vrol_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
+; CHECK-LABEL: vrol_vv_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv1i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)
+  ret <vscale x 1 x i64> %x
+}
+
+define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv1i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
+; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv1i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v9, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vrol_vx_nxv1i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-ZVBB32-NEXT:    vrol.vv v8, v8, v9
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vrol_vx_nxv1i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-ZVBB64-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
+  ret <vscale x 1 x i64> %x
+}
+
+declare <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
+
+define <vscale x 2 x i64> @vrol_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: vrol_vv_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT:    vand.vx v12, v10, a0
+; CHECK-NEXT:    vsll.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vx v10, v10, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv2i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+  ret <vscale x 2 x i64> %x
+}
+
+define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v12, v10, a0
+; CHECK-RV32-NEXT:    vsll.vv v12, v8, v12
+; CHECK-RV32-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
+; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
+; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v10, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vrol_vx_nxv2i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-ZVBB32-NEXT:    vrol.vv v8, v8, v10
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vrol_vx_nxv2i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-ZVBB64-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
+  ret <vscale x 2 x i64> %x
+}
+
+declare <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
+
+define <vscale x 4 x i64> @vrol_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
+; CHECK-LABEL: vrol_vv_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vand.vx v16, v12, a0
+; CHECK-NEXT:    vsll.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv4i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
+  ret <vscale x 4 x i64> %x
+}
+
+define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v16, v12, a0
+; CHECK-RV32-NEXT:    vsll.vv v16, v8, v16
+; CHECK-RV32-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
+; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v12
+; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v12, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vrol_vx_nxv4i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-ZVBB32-NEXT:    vrol.vv v8, v8, v12
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vrol_vx_nxv4i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-ZVBB64-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
+  ret <vscale x 4 x i64> %x
+}
+
+declare <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>)
+
+define <vscale x 8 x i64> @vrol_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
+; CHECK-LABEL: vrol_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vand.vx v24, v16, a0
+; CHECK-NEXT:    vsll.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vrol_vv_nxv8i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
+  ret <vscale x 8 x i64> %x
+}
+
+define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vrol_vx_nxv8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v24, v16, a0
+; CHECK-RV32-NEXT:    vsll.vv v24, v8, v24
+; CHECK-RV32-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
+; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v16
+; CHECK-RV32-NEXT:    vor.vv v8, v24, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vrol_vx_nxv8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v16, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vrol_vx_nxv8i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-ZVBB32-NEXT:    vrol.vv v8, v8, v16
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vrol_vx_nxv8i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-ZVBB64-NEXT:    vrol.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
+  ret <vscale x 8 x i64> %x
+}
+

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
+
+declare <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
+
+define <vscale x 1 x i8> @vror_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv1i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)
+  ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv1i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
+  ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vror_vi_nxv1i8(<vscale x 1 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv1i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> shufflevector(<vscale x 1 x i8> insertelement(<vscale x 1 x i8> poison, i8 1, i32 0), <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer))
+  ret <vscale x 1 x i8> %x
+}
+
+
+declare <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>)
+
+define <vscale x 2 x i8> @vror_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv2i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)
+  ret <vscale x 2 x i8> %x
+}
+
+define <vscale x 2 x i8> @vror_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv2i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)
+  ret <vscale x 2 x i8> %x
+}
+
+define <vscale x 2 x i8> @vror_vi_nxv2i8(<vscale x 2 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv2i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> shufflevector(<vscale x 2 x i8> insertelement(<vscale x 2 x i8> poison, i8 1, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer))
+  ret <vscale x 2 x i8> %x
+}
+
+
+declare <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>)
+
+define <vscale x 4 x i8> @vror_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv4i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)
+  ret <vscale x 4 x i8> %x
+}
+
+define <vscale x 4 x i8> @vror_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv4i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)
+  ret <vscale x 4 x i8> %x
+}
+
+define <vscale x 4 x i8> @vror_vi_nxv4i8(<vscale x 4 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv4i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> shufflevector(<vscale x 4 x i8> insertelement(<vscale x 4 x i8> poison, i8 1, i32 0), <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer))
+  ret <vscale x 4 x i8> %x
+}
+
+
+declare <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>)
+
+define <vscale x 8 x i8> @vror_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv8i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
+  ret <vscale x 8 x i8> %x
+}
+
+define <vscale x 8 x i8> @vror_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 7
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv8i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)
+  ret <vscale x 8 x i8> %x
+}
+
+define <vscale x 8 x i8> @vror_vi_nxv8i8(<vscale x 8 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv8i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> shufflevector(<vscale x 8 x i8> insertelement(<vscale x 8 x i8> poison, i8 1, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer))
+  ret <vscale x 8 x i8> %x
+}
+
+
+declare <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+
+define <vscale x 16 x i8> @vror_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vand.vi v12, v10, 7
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv16i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+  ret <vscale x 16 x i8> %x
+}
+
+define <vscale x 16 x i8> @vror_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vi v12, v10, 7
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv16i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)
+  ret <vscale x 16 x i8> %x
+}
+
+define <vscale x 16 x i8> @vror_vi_nxv16i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vsll.vi v10, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v10
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv16i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> shufflevector(<vscale x 16 x i8> insertelement(<vscale x 16 x i8> poison, i8 1, i32 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer))
+  ret <vscale x 16 x i8> %x
+}
+
+
+declare <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>)
+
+define <vscale x 32 x i8> @vror_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vand.vi v16, v12, 7
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv32i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)
+  ret <vscale x 32 x i8> %x
+}
+
+define <vscale x 32 x i8> @vror_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vand.vi v16, v12, 7
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv32i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
+  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)
+  ret <vscale x 32 x i8> %x
+}
+
+define <vscale x 32 x i8> @vror_vi_nxv32i8(<vscale x 32 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vsll.vi v12, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v12
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv32i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> shufflevector(<vscale x 32 x i8> insertelement(<vscale x 32 x i8> poison, i8 1, i32 0), <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer))
+  ret <vscale x 32 x i8> %x
+}
+
+
+declare <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>)
+
+define <vscale x 64 x i8> @vror_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
+; CHECK-LABEL: vror_vv_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vand.vi v24, v16, 7
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv64i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
+  ret <vscale x 64 x i8> %x
+}
+
+define <vscale x 64 x i8> @vror_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vand.vi v24, v16, 7
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 7
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv64i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
+  %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
+  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)
+  ret <vscale x 64 x i8> %x
+}
+
+define <vscale x 64 x i8> @vror_vi_nxv64i8(<vscale x 64 x i8> %a) {
+; CHECK-LABEL: vror_vi_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vsll.vi v16, v8, 7
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v16
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv64i8:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> shufflevector(<vscale x 64 x i8> insertelement(<vscale x 64 x i8> poison, i8 1, i32 0), <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer))
+  ret <vscale x 64 x i8> %x
+}
+
+
+declare <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>)
+
+define <vscale x 1 x i16> @vror_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv1i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)
+  ret <vscale x 1 x i16> %x
+}
+
+define <vscale x 1 x i16> @vror_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv1i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)
+  ret <vscale x 1 x i16> %x
+}
+
+define <vscale x 1 x i16> @vror_vi_nxv1i16(<vscale x 1 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv1i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> shufflevector(<vscale x 1 x i16> insertelement(<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer))
+  ret <vscale x 1 x i16> %x
+}
+
+
+declare <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
+
+define <vscale x 2 x i16> @vror_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv2i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)
+  ret <vscale x 2 x i16> %x
+}
+
+define <vscale x 2 x i16> @vror_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv2i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)
+  ret <vscale x 2 x i16> %x
+}
+
+define <vscale x 2 x i16> @vror_vi_nxv2i16(<vscale x 2 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv2i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> shufflevector(<vscale x 2 x i16> insertelement(<vscale x 2 x i16> poison, i16 1, i32 0), <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer))
+  ret <vscale x 2 x i16> %x
+}
+
+
+declare <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>)
+
+define <vscale x 4 x i16> @vror_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv4i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
+  ret <vscale x 4 x i16> %x
+}
+
+define <vscale x 4 x i16> @vror_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vand.vi v10, v9, 15
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vi v9, v9, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv4i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)
+  ret <vscale x 4 x i16> %x
+}
+
+define <vscale x 4 x i16> @vror_vi_nxv4i16(<vscale x 4 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv4i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> shufflevector(<vscale x 4 x i16> insertelement(<vscale x 4 x i16> poison, i16 1, i32 0), <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer))
+  ret <vscale x 4 x i16> %x
+}
+
+
+declare <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
+
+define <vscale x 8 x i16> @vror_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vand.vi v12, v10, 15
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+  ret <vscale x 8 x i16> %x
+}
+
+define <vscale x 8 x i16> @vror_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vi v12, v10, 15
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vi v10, v10, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)
+  ret <vscale x 8 x i16> %x
+}
+
+define <vscale x 8 x i16> @vror_vi_nxv8i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vsll.vi v10, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v10
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> shufflevector(<vscale x 8 x i16> insertelement(<vscale x 8 x i16> poison, i16 1, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer))
+  ret <vscale x 8 x i16> %x
+}
+
+
+declare <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>)
+
+define <vscale x 16 x i16> @vror_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vand.vi v16, v12, 15
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv16i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
+  ret <vscale x 16 x i16> %x
+}
+
+define <vscale x 16 x i16> @vror_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vand.vi v16, v12, 15
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vi v12, v12, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv16i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)
+  ret <vscale x 16 x i16> %x
+}
+
+define <vscale x 16 x i16> @vror_vi_nxv16i16(<vscale x 16 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vsll.vi v12, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v12
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv16i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> shufflevector(<vscale x 16 x i16> insertelement(<vscale x 16 x i16> poison, i16 1, i32 0), <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer))
+  ret <vscale x 16 x i16> %x
+}
+
+
+declare <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>)
+
+define <vscale x 32 x i16> @vror_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
+; CHECK-LABEL: vror_vv_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT:    vand.vi v24, v16, 15
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv32i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
+  ret <vscale x 32 x i16> %x
+}
+
+define <vscale x 32 x i16> @vror_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {
+; CHECK-LABEL: vror_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vand.vi v24, v16, 15
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vi v16, v16, 15
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv32i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
+  %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
+  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)
+  ret <vscale x 32 x i16> %x
+}
+
+define <vscale x 32 x i16> @vror_vi_nxv32i16(<vscale x 32 x i16> %a) {
+; CHECK-LABEL: vror_vi_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT:    vsll.vi v16, v8, 15
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v16
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv32i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> shufflevector(<vscale x 32 x i16> insertelement(<vscale x 32 x i16> poison, i16 1, i32 0), <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer))
+  ret <vscale x 32 x i16> %x
+}
+
+
+declare <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>)
+
+define <vscale x 1 x i32> @vror_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
+; CHECK-LABEL: vror_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv1i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)
+  ret <vscale x 1 x i32> %x
+}
+
+define <vscale x 1 x i32> @vror_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv1i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT:    vsrl.vx v9, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv1i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v9, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv1i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)
+  ret <vscale x 1 x i32> %x
+}
+
+define <vscale x 1 x i32> @vror_vi_nxv1i32(<vscale x 1 x i32> %a) {
+; CHECK-LABEL: vror_vi_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 31
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv1i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> shufflevector(<vscale x 1 x i32> insertelement(<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer))
+  ret <vscale x 1 x i32> %x
+}
+
+
+declare <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @vror_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+; CHECK-LABEL: vror_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv2i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  ret <vscale x 2 x i32> %x
+}
+
+define <vscale x 2 x i32> @vror_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv2i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT:    vsrl.vx v9, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv2i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v9, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv2i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)
+  ret <vscale x 2 x i32> %x
+}
+
+define <vscale x 2 x i32> @vror_vi_nxv2i32(<vscale x 2 x i32> %a) {
+; CHECK-LABEL: vror_vi_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vsll.vi v9, v8, 31
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv2i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> shufflevector(<vscale x 2 x i32> insertelement(<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer))
+  ret <vscale x 2 x i32> %x
+}
+
+
+declare <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+
+define <vscale x 4 x i32> @vror_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: vror_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vand.vx v12, v10, a0
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vx v10, v10, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+  ret <vscale x 4 x i32> %x
+}
+
+define <vscale x 4 x i32> @vror_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv4i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT:    vsrl.vx v10, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv4i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v10, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v12, v10, a0
+; CHECK-RV64-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-RV64-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-RV64-NEXT:    vand.vx v10, v10, a0
+; CHECK-RV64-NEXT:    vsll.vv v8, v8, v10
+; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)
+  ret <vscale x 4 x i32> %x
+}
+
+define <vscale x 4 x i32> @vror_vi_nxv4i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: vror_vi_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vsll.vi v10, v8, 31
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v10
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector(<vscale x 4 x i32> insertelement(<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
+  ret <vscale x 4 x i32> %x
+}
+
+
+declare <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>)
+
+define <vscale x 8 x i32> @vror_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
+; CHECK-LABEL: vror_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vand.vx v16, v12, a0
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vx v12, v12, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
+  ret <vscale x 8 x i32> %x
+}
+
+define <vscale x 8 x i32> @vror_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv8i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
+; CHECK-RV32-NEXT:    vsrl.vx v12, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv8i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v12, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v16, v12, a0
+; CHECK-RV64-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-RV64-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-RV64-NEXT:    vand.vx v12, v12, a0
+; CHECK-RV64-NEXT:    vsll.vv v8, v8, v12
+; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)
+  ret <vscale x 8 x i32> %x
+}
+
+define <vscale x 8 x i32> @vror_vi_nxv8i32(<vscale x 8 x i32> %a) {
+; CHECK-LABEL: vror_vi_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vsll.vi v12, v8, 31
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v12
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> shufflevector(<vscale x 8 x i32> insertelement(<vscale x 8 x i32> poison, i32 1, i32 0), <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer))
+  ret <vscale x 8 x i32> %x
+}
+
+
+declare <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>)
+
+define <vscale x 16 x i32> @vror_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
+; CHECK-LABEL: vror_vv_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 31
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vand.vx v24, v16, a0
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vx v16, v16, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv16i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
+  ret <vscale x 16 x i32> %x
+}
+
+define <vscale x 16 x i32> @vror_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv16i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    andi a1, a0, 31
+; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-RV32-NEXT:    vsrl.vx v16, v8, a1
+; CHECK-RV32-NEXT:    neg a0, a0
+; CHECK-RV32-NEXT:    andi a0, a0, 31
+; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv16i32:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-RV64-NEXT:    vmv.v.x v16, a0
+; CHECK-RV64-NEXT:    li a0, 31
+; CHECK-RV64-NEXT:    vand.vx v24, v16, a0
+; CHECK-RV64-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-RV64-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-RV64-NEXT:    vand.vx v16, v16, a0
+; CHECK-RV64-NEXT:    vsll.vv v8, v8, v16
+; CHECK-RV64-NEXT:    vor.vv v8, v24, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vx_nxv16i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB-NEXT:    ret
+  %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
+  %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
+  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)
+  ret <vscale x 16 x i32> %x
+}
+
+define <vscale x 16 x i32> @vror_vi_nxv16i32(<vscale x 16 x i32> %a) {
+; CHECK-LABEL: vror_vi_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vsll.vi v16, v8, 31
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v16
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv16i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> shufflevector(<vscale x 16 x i32> insertelement(<vscale x 16 x i32> poison, i32 1, i32 0), <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer))
+  ret <vscale x 16 x i32> %x
+}
+
+
+declare <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>)
+
+define <vscale x 1 x i64> @vror_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
+; CHECK-LABEL: vror_vv_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv1i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)
+  ret <vscale x 1 x i64> %x
+}
+
+define <vscale x 1 x i64> @vror_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv1i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v10, v9, a0
+; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v9
+; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv1i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-RV64-NEXT:    vsrl.vx v9, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vror_vx_nxv1i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-ZVBB32-NEXT:    vror.vv v8, v8, v9
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vror_vx_nxv1i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-ZVBB64-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
+  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
+  ret <vscale x 1 x i64> %x
+}
+
+define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) {
+; CHECK-RV32-LABEL: vror_vi_nxv1i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v9, a0
+; CHECK-RV32-NEXT:    vand.vi v9, v9, 1
+; CHECK-RV32-NEXT:    vsrl.vv v9, v8, v9
+; CHECK-RV32-NEXT:    vmv.v.i v10, 1
+; CHECK-RV32-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
+; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vi_nxv1i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    li a0, 63
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v9, v8, a0
+; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv1i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer))
+  ret <vscale x 1 x i64> %x
+}
+
+
+declare <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
+
+define <vscale x 2 x i64> @vror_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: vror_vv_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT:    vand.vx v12, v10, a0
+; CHECK-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-NEXT:    vand.vx v10, v10, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v12, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv2i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v10
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+  ret <vscale x 2 x i64> %x
+}
+
+define <vscale x 2 x i64> @vror_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v12, v10, a0
+; CHECK-RV32-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-RV32-NEXT:    vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
+; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
+; CHECK-RV64-NEXT:    vsrl.vx v10, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vror_vx_nxv2i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-ZVBB32-NEXT:    vror.vv v8, v8, v10
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vror_vx_nxv2i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-ZVBB64-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
+  ret <vscale x 2 x i64> %x
+}
+
+define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) {
+; CHECK-RV32-LABEL: vror_vi_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v10, a0
+; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
+; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-RV32-NEXT:    vmv.v.i v12, 1
+; CHECK-RV32-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v12
+; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vi_nxv2i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    li a0, 63
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v10, v8, a0
+; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-RV64-NEXT:    vor.vv v8, v8, v10
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv2i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
+  ret <vscale x 2 x i64> %x
+}
+
+
+declare <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
+
+define <vscale x 4 x i64> @vror_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
+; CHECK-LABEL: vror_vv_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vand.vx v16, v12, a0
+; CHECK-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-NEXT:    vand.vx v12, v12, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v12
+; CHECK-NEXT:    vor.vv v8, v16, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv4i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v12
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
+  ret <vscale x 4 x i64> %x
+}
+
+define <vscale x 4 x i64> @vror_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v16, v12, a0
+; CHECK-RV32-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-RV32-NEXT:    vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v12
+; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
+; CHECK-RV64-NEXT:    vsrl.vx v12, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vror_vx_nxv4i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-ZVBB32-NEXT:    vror.vv v8, v8, v12
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vror_vx_nxv4i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-ZVBB64-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
+  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
+  ret <vscale x 4 x i64> %x
+}
+
+define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) {
+; CHECK-RV32-LABEL: vror_vi_nxv4i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v12, a0
+; CHECK-RV32-NEXT:    vand.vi v12, v12, 1
+; CHECK-RV32-NEXT:    vsrl.vv v12, v8, v12
+; CHECK-RV32-NEXT:    vmv.v.i v16, 1
+; CHECK-RV32-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v16
+; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vi_nxv4i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    li a0, 63
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v12, v8, a0
+; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-RV64-NEXT:    vor.vv v8, v8, v12
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv4i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> shufflevector(<vscale x 4 x i64> insertelement(<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer))
+  ret <vscale x 4 x i64> %x
+}
+
+
+declare <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>)
+
+define <vscale x 8 x i64> @vror_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
+; CHECK-LABEL: vror_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vand.vx v24, v16, a0
+; CHECK-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-NEXT:    vand.vx v16, v16, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v16
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vv_nxv8i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v16
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
+  ret <vscale x 8 x i64> %x
+}
+
+define <vscale x 8 x i64> @vror_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
+; CHECK-RV32-LABEL: vror_vx_nxv8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-RV32-NEXT:    sw a1, 12(sp)
+; CHECK-RV32-NEXT:    sw a0, 8(sp)
+; CHECK-RV32-NEXT:    addi a0, sp, 8
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vand.vx v24, v16, a0
+; CHECK-RV32-NEXT:    vsrl.vv v24, v8, v24
+; CHECK-RV32-NEXT:    vrsub.vi v16, v16, 0
+; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v16
+; CHECK-RV32-NEXT:    vor.vv v8, v24, v8
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vx_nxv8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    andi a1, a0, 63
+; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; CHECK-RV64-NEXT:    vsrl.vx v16, v8, a1
+; CHECK-RV64-NEXT:    negw a0, a0
+; CHECK-RV64-NEXT:    andi a0, a0, 63
+; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
+; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB32-LABEL: vror_vx_nxv8i64:
+; CHECK-ZVBB32:       # %bb.0:
+; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
+; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
+; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
+; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
+; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-ZVBB32-NEXT:    vror.vv v8, v8, v16
+; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    ret
+;
+; CHECK-ZVBB64-LABEL: vror_vx_nxv8i64:
+; CHECK-ZVBB64:       # %bb.0:
+; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-ZVBB64-NEXT:    vror.vx v8, v8, a0
+; CHECK-ZVBB64-NEXT:    ret
+  %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+  %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
+  ret <vscale x 8 x i64> %x
+}
+
+define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) {
+; CHECK-RV32-LABEL: vror_vi_nxv8i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    li a0, 63
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v16, a0
+; CHECK-RV32-NEXT:    vand.vi v16, v16, 1
+; CHECK-RV32-NEXT:    vsrl.vv v16, v8, v16
+; CHECK-RV32-NEXT:    vmv.v.i v24, 1
+; CHECK-RV32-NEXT:    vrsub.vi v24, v24, 0
+; CHECK-RV32-NEXT:    vand.vx v24, v24, a0
+; CHECK-RV32-NEXT:    vsll.vv v8, v8, v24
+; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
+; CHECK-RV32-NEXT:    ret
+;
+; CHECK-RV64-LABEL: vror_vi_nxv8i64:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    li a0, 63
+; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV64-NEXT:    vsll.vx v16, v8, a0
+; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-RV64-NEXT:    vor.vv v8, v8, v16
+; CHECK-RV64-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vror_vi_nxv8i64:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
+; CHECK-ZVBB-NEXT:    ret
+  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer))
+  ret <vscale x 8 x i64> %x
+}
+
+