[RISCV] Cleanups in CORE-V (xcv) extensions

[simoncook]

Summary

This is a mostly NFC change cleaning up and clarifying components of the
in-tree CORE-V (xcv*) extensions following discussions on the remaining
extensions.

This makes the following changes to the xcbitmanip and xcvmac support:

1. Add missing extensions from RISCVISAInfo, such that they can be supported in clang's -march option.
2. Clarify the extension version number is 1.0.0 in documentation.
3. Clarify the extensions are by OpenHW Group, and the capitilization of the CORE-V extension family.
4. Add CORE-V to extension name in RISCVFeatures, both to be consistent with other vendors, and also better distinguish e.g. CORE-V bit manipulation vs RISC-V's standard Zb extensions.

[asb]

The fact this slipped through without an entry in RISCVISAInfo suggests we were missing test coverage in attribute-arch.s and/or attributes.ll for the emitted extension version. Your changes so far all LGTM, but please take a look at those tests. Thanks!

[simoncook]

Add missing extension version tests

[craig.topper]

LGTM

[asb]

LGTM too, thanks.

llvm/docs/RISCVUsage.rst

 
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XCVbitmanip``
-  LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
+  LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
 ``XCVmac``
-  LLVM implements `version 1.3.1 of the Core-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.mac.` as described in the specification. These instructions are only available for riscv32 at this time.
+  LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XSfcie``
   LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.  All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
 
     {"svinval", RISCVExtensionVersion{1, 0}},
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svpbmt", RISCVExtensionVersion{1, 0}},
 
     {"v", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
+    {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
+    {"xcvmac", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},
     {"xtheadcmo", RISCVExtensionVersion{1, 0}},
     {"xtheadcondmov", RISCVExtensionVersion{1, 0}},
     {"xtheadfmemidx", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/RISCVFeatures.td

def FeatureVendorXSfcie
     : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
                        "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
                         AssemblerPredicate<(all_of FeatureVendorXSfcie),
                         "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 
 def FeatureVendorXCVbitmanip
     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
-                       "'XCVbitmanip' (Bit Manipulation)">;
+                       "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
-                                "'XCVbitmanip' (Bit Manipulation)">;
+                                "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 
 def FeatureVendorXCVmac
     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
-                       "'XCVmac' (Multiply-Accumulate)">;
+                       "'XCVmac' (CORE-V Multiply-Accumulate)">;
 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
-                                "'XCVmac' (Multiply-Accumulate)">;
+                                "'XCVmac' (CORE-V Multiply-Accumulate)">;
 
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s

 ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
+; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
+; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
 
 .attribute arch, "rv64i_xsfcie"
 # CHECK: attribute      5, "rv64i2p1_xsfcie1p0"
 
 .attribute arch, "rv32izacas1p0"
 # CHECK: attribute      5, "rv32i2p1_a2p1_zacas1p0"
+
+.attribute arch, "rv32i_xcvbitmanip"
+# CHECK: attribute      5, "rv32i2p1_xcvbitmanip1p0"
+
+.attribute arch, "rv32i_xcvmac"
+# CHECK: attribute      5, "rv32i2p1_xcvmac1p0"

llvm/test/MC/RISCV/corev/XCVbitmanip.s

 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvbitmanip -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvbitmanip < %s \
 # RUN:     | llvm-objdump --mattr=+xcvbitmanip -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
 # RUN: not llvm-mc -triple riscv32 %s 2>&1 \
 # RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
 
 cv.extract t0, t1, 0, 1
 # CHECK-INSTR: cv.extract t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x02,0x13,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extract a0, a1, 17, 18
 # CHECK-INSTR: cv.extract a0, a1, 17, 18
 # CHECK-ENCODING: [0x5b,0x85,0x25,0x23]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extract s0, s1, 30, 31
 # CHECK-INSTR: cv.extract s0, s1, 30, 31
 # CHECK-ENCODING: [0x5b,0x84,0xf4,0x3d]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractu t0, t1, 0, 1
 # CHECK-INSTR: cv.extractu t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x02,0x13,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractu a0, a1, 17, 18
 # CHECK-INSTR: cv.extractu a0, a1, 17, 18
 # CHECK-ENCODING: [0x5b,0x85,0x25,0x63]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractu s0, s1, 30, 31
 # CHECK-INSTR: cv.extractu s0, s1, 30, 31
 # CHECK-ENCODING: [0x5b,0x84,0xf4,0x7d]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insert t0, t1, 0, 1
 # CHECK-INSTR: cv.insert t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x02,0x13,0x80]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insert a0, a1, 17, 18
 # CHECK-INSTR: cv.insert a0, a1, 17, 18
 # CHECK-ENCODING: [0x5b,0x85,0x25,0xa3]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insert s0, s1, 30, 31
 # CHECK-INSTR: cv.insert s0, s1, 30, 31
 # CHECK-ENCODING: [0x5b,0x84,0xf4,0xbd]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclr t0, t1, 0, 1
 # CHECK-INSTR: cv.bclr t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x12,0x13,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclr a0, a1, 17, 18
 # CHECK-INSTR: cv.bclr a0, a1, 17, 18
 # CHECK-ENCODING: [0x5b,0x95,0x25,0x23]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclr s0, s1, 30, 31
 # CHECK-INSTR: cv.bclr s0, s1, 30, 31
 # CHECK-ENCODING: [0x5b,0x94,0xf4,0x3d]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bset t0, t1, 0, 1
 # CHECK-INSTR: cv.bset t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x12,0x13,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bset a0, a1, 17, 18
 # CHECK-INSTR: cv.bset a0, a1, 17, 18
 # CHECK-ENCODING: [0x5b,0x95,0x25,0x63]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bset s0, s1, 30, 31
 # CHECK-INSTR: cv.bset s0, s1, 30, 31
 # CHECK-ENCODING: [0x5b,0x94,0xf4,0x7d]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bitrev t0, t1, 0, 1
 # CHECK-INSTR: cv.bitrev t0, t1, 0, 1
 # CHECK-ENCODING: [0xdb,0x12,0x13,0xc0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bitrev a0, a1, 1, 18
 # CHECK-INSTR: cv.bitrev a0, a1, 1, 18
 # CHECK-ENCODING: [0x5b,0x95,0x25,0xc3]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bitrev s0, s1, 2, 31
 # CHECK-INSTR: cv.bitrev s0, s1, 2, 31
 # CHECK-ENCODING: [0x5b,0x94,0xf4,0xc5]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractr t0, t1, t2
 # CHECK-INSTR: cv.extractr t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x30]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractr a0, a1, a2
 # CHECK-INSTR: cv.extractr a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x30]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractr s0, s1, s2
 # CHECK-INSTR: cv.extractr s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x31]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractur t0, t1, t2
 # CHECK-INSTR: cv.extractur t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x32]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractur a0, a1, a2
 # CHECK-INSTR: cv.extractur a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x32]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.extractur s0, s1, s2
 # CHECK-INSTR: cv.extractur s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x33]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insertr t0, t1, t2
 # CHECK-INSTR: cv.insertr t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x34]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insertr a0, a1, a2
 # CHECK-INSTR: cv.insertr a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x34]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.insertr s0, s1, s2
 # CHECK-INSTR: cv.insertr s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x35]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclrr t0, t1, t2
 # CHECK-INSTR: cv.bclrr t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x38]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclrr a0, a1, a2
 # CHECK-INSTR: cv.bclrr a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x38]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bclrr s0, s1, s2
 # CHECK-INSTR: cv.bclrr s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x39]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bsetr t0, t1, t2
 # CHECK-INSTR: cv.bsetr t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x3a]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bsetr a0, a1, a2
 # CHECK-INSTR: cv.bsetr a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x3a]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.bsetr s0, s1, s2
 # CHECK-INSTR: cv.bsetr s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x3b]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ror t0, t1, t2
 # CHECK-INSTR: cv.ror t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ror a0, a1, a2
 # CHECK-INSTR: cv.ror a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ror s0, s1, s2
 # CHECK-INSTR: cv.ror s0, s1, s2
 # CHECK-ENCODING: [0x2b,0xb4,0x24,0x41]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ff1 t0, t1
 # CHECK-INSTR: cv.ff1 t0, t1
 # CHECK-ENCODING: [0xab,0x32,0x03,0x42]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ff1 a0, a1
 # CHECK-INSTR: cv.ff1 a0, a1
 # CHECK-ENCODING: [0x2b,0xb5,0x05,0x42]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.ff1 s0, s1
 # CHECK-INSTR: cv.ff1 s0, s1
 # CHECK-ENCODING: [0x2b,0xb4,0x04,0x42]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.fl1 t0, t1
 # CHECK-INSTR: cv.fl1 t0, t1
 # CHECK-ENCODING: [0xab,0x32,0x03,0x44]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.fl1 a0, a1
 # CHECK-INSTR: cv.fl1 a0, a1
 # CHECK-ENCODING: [0x2b,0xb5,0x05,0x44]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.fl1 s0, s1
 # CHECK-INSTR: cv.fl1 s0, s1
 # CHECK-ENCODING: [0x2b,0xb4,0x04,0x44]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.clb t0, t1
 # CHECK-INSTR: cv.clb t0, t1
 # CHECK-ENCODING: [0xab,0x32,0x03,0x46]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.clb a0, a1
 # CHECK-INSTR: cv.clb a0, a1
 # CHECK-ENCODING: [0x2b,0xb5,0x05,0x46]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.clb s0, s1
 # CHECK-INSTR: cv.clb s0, s1
 # CHECK-ENCODING: [0x2b,0xb4,0x04,0x46]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.cnt t0, t1
 # CHECK-INSTR: cv.cnt t0, t1
 # CHECK-ENCODING: [0xab,0x32,0x03,0x48]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.cnt a0, a1
 # CHECK-INSTR: cv.cnt a0, a1
 # CHECK-ENCODING: [0x2b,0xb5,0x05,0x48]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 
 cv.cnt s0, s1
 # CHECK-INSTR: cv.cnt s0, s1
 # CHECK-ENCODING: [0x2b,0xb4,0x04,0x48]
-# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (CORE-V Bit Manipulation){{$}}
 

llvm/test/MC/RISCV/corev/XCVmac-valid.s

 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvmac -riscv-no-aliases -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmac < %s \
 # RUN:     | llvm-objdump --mattr=+xcvmac -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
 # RUN: not llvm-mc -triple riscv32 %s 2>&1 \
 # RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
 
 cv.mac t0, t1, t2
 # CHECK-INSTR: cv.mac t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x90]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mac t0, t1, zero
 # CHECK-INSTR: cv.mac t0, t1, zero
 # CHECK-ENCODING: [0xab,0x32,0x03,0x90]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsn t0, t1, t2, 0
 # CHECK-INSTR: cv.machhsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x62,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsn t0, t1, zero, 16
 # CHECK-INSTR: cv.machhsn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x62,0x03,0x60]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsn t0, t1, zero, 31
 # CHECK-INSTR: cv.machhsn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x62,0x03,0x7e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsrn t0, t1, t2, 0
 # CHECK-INSTR: cv.machhsrn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x62,0x73,0xc0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsrn t0, t1, zero, 16
 # CHECK-INSTR: cv.machhsrn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x62,0x03,0xe0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhsrn t0, t1, zero, 31
 # CHECK-INSTR: cv.machhsrn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x62,0x03,0xfe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhun t0, t1, t2, 0
 # CHECK-INSTR: cv.machhun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x72,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhun t0, t1, zero, 16
 # CHECK-INSTR: cv.machhun t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x72,0x03,0x60]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhun t0, t1, zero, 31
 # CHECK-INSTR: cv.machhun t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x72,0x03,0x7e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhurn t0, t1, t2, 0
 # CHECK-INSTR: cv.machhurn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x72,0x73,0xc0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhurn t0, t1, zero, 16
 # CHECK-INSTR: cv.machhurn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x72,0x03,0xe0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.machhurn t0, t1, zero, 31
 # CHECK-INSTR: cv.machhurn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x72,0x03,0xfe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsn t0, t1, t2, 0
 # CHECK-INSTR: cv.macsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x62,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsn t0, t1, zero, 16
 # CHECK-INSTR: cv.macsn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x62,0x03,0x20]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsn t0, t1, zero, 31
 # CHECK-INSTR: cv.macsn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x62,0x03,0x3e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsrn t0, t1, t2, 0
 # CHECK-INSTR: cv.macsrn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x62,0x73,0x80]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsrn t0, t1, zero, 16
 # CHECK-INSTR: cv.macsrn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x62,0x03,0xa0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macsrn t0, t1, zero, 31
 # CHECK-INSTR: cv.macsrn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x62,0x03,0xbe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macun t0, t1, t2, 0
 # CHECK-INSTR: cv.macun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x72,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macun t0, t1, zero, 16
 # CHECK-INSTR: cv.macun t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x72,0x03,0x20]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macun t0, t1, zero, 31
 # CHECK-INSTR: cv.macun t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x72,0x03,0x3e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macurn t0, t1, t2, 0
 # CHECK-INSTR: cv.macurn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x72,0x73,0x80]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macurn t0, t1, zero, 16
 # CHECK-INSTR: cv.macurn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x72,0x03,0xa0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.macurn t0, t1, zero, 31
 # CHECK-INSTR: cv.macurn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x72,0x03,0xbe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.msu t0, t1, t2
 # CHECK-INSTR: cv.msu t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x92]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.msu t0, t1, zero
 # CHECK-INSTR: cv.msu t0, t1, zero
 # CHECK-ENCODING: [0xab,0x32,0x03,0x92]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhs t0, t1, t2
 # CHECK-INSTR: cv.mulhhsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhs t0, t1, zero
 # CHECK-INSTR: cv.mulhhsn t0, t1, zero, 0
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulhhsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulhhsn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x60]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulhhsn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x7e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsrn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulhhsrn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0xc0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsrn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulhhsrn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x42,0x03,0xe0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhsrn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulhhsrn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x42,0x03,0xfe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhu t0, t1, t2
 # CHECK-INSTR: cv.mulhhun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhu t0, t1, zero
 # CHECK-INSTR: cv.mulhhun t0, t1, zero, 0
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhun t0, t1, t2, 0
 # CHECK-INSTR: cv.mulhhun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0x40]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 
 cv.mulhhun t0, t1, zero, 16
 # CHECK-INSTR: cv.mulhhun t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x60]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhun t0, t1, zero, 31
 # CHECK-INSTR: cv.mulhhun t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x7e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhurn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulhhurn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0xc0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhurn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulhhurn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x52,0x03,0xe0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulhhurn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulhhurn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x52,0x03,0xfe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.muls t0, t1, t2
 # CHECK-INSTR: cv.mulsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.muls t0, t1, zero
 # CHECK-INSTR: cv.mulsn t0, t1, zero, 0
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulsn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulsn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x20]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulsn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x42,0x03,0x3e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsrn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulsrn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x42,0x73,0x80]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsrn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulsrn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x42,0x03,0xa0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulsrn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulsrn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x42,0x03,0xbe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulu t0, t1, t2
 # CHECK-INSTR: cv.mulun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulu t0, t1, zero
 # CHECK-INSTR: cv.mulun t0, t1, zero, 0
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulun t0, t1, t2, 0
 # CHECK-INSTR: cv.mulun t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0x00]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulun t0, t1, zero, 16
 # CHECK-INSTR: cv.mulun t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x20]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulun t0, t1, zero, 31
 # CHECK-INSTR: cv.mulun t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x52,0x03,0x3e]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulurn t0, t1, t2, 0
 # CHECK-INSTR: cv.mulurn t0, t1, t2, 0
 # CHECK-ENCODING: [0xdb,0x52,0x73,0x80]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulurn t0, t1, zero, 16
 # CHECK-INSTR: cv.mulurn t0, t1, zero, 16
 # CHECK-ENCODING: [0xdb,0x52,0x03,0xa0]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}
 
 cv.mulurn t0, t1, zero, 31
 # CHECK-INSTR: cv.mulurn t0, t1, zero, 31
 # CHECK-ENCODING: [0xdb,0x52,0x03,0xbe]
-# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (CORE-V Multiply-Accumulate){{$}}