[RISCV] Lower inline asm constraints vi, vj and vk.

[fakepaper56]

Summary

This validate and lower arguments to inline asm nodes which have the constraints vi, vi and vk, with the following semantics (equivalent to GCC):
vi: vector 5-bit signed immediate.
vj: vector negated 5-bit signed immediate.
vk: vector 5-bit unsigned immediate.

[craig.topper]

Don't we need to update clang too?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

16095

Can we merge this if into the previous else so we have

if (Constraint.length() == 1) {
   ...
} else if (Constraint == "vi") {
  ...
} else if (Constraint == "vk") {
 ...
} else if (Constraint == "vj") {
 ...
}

[kito-cheng]

Ooops, hold on, GCC actually is accepting immediate vector value instead of immediate scalar value.

(define_constraint "vi"
  "A vector 5-bit signed immediate."
  (and (match_code "const_vector")
       (match_test "riscv_vector::const_vec_all_same_in_range_p (op, -16, 15)")))

(define_constraint "vj"
  "A vector negated 5-bit signed immediate."
  (and (match_code "const_vector")
       (match_test "riscv_vector::const_vec_all_same_in_range_p (op, -15, 16)")))

(define_constraint "vk"
  "A vector 5-bit unsigned immediate."
  (and (match_code "const_vector")
       (match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))

I mean GCC can't really accept immediate value with either vi, vk or vj:

$ cat x.c
int foo() {
    asm volatile("## %0" :/*write*/ :/*read*/ "vi"(10): /* clobber */);
    return 0;
}

$ riscv64-unknown-linux-gnu-gcc x.c -o - -S -O3
        .file   "x.c"
        .option nopic
        .attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
        .attribute unaligned_access, 0
        .attribute stack_align, 16
        .text
x.c: In function 'foo':
x.c:2:5: warning: 'asm' operand 0 probably does not match constraints
    2 |     asm volatile("## %0" :/*write*/ :/*read*/ "vi"(10): /* clobber */);
      |     ^~~
x.c:2:5: error: impossible constraint in 'asm'
        .align  1
        .globl  foo
        .type   foo, @function
foo:
.LFB0:
        .cfi_startproc
        li      a0,0
        ret
        .cfi_endproc
.LFE0:
        .size   foo, .-foo

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Constraint.size() == 1) {
     case 'A':
       return C_Memory;
     case 'S': // A symbolic address
       return C_Other;
     }
   } else {
     if (Constraint == "vr" || Constraint == "vm")
       return C_RegisterClass;
+    if (Constraint == "vi" || Constraint == "vj" || Constraint == "vk")
+      return C_Immediate;
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass *>
 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,
                                                   MVT VT) const {
case 'S':
       } else if (const auto *BA = dyn_cast<BlockAddressSDNode>(Op)) {
         Ops.push_back(DAG.getTargetBlockAddress(BA->getBlockAddress(),
                                                 BA->getValueType(0)));
       }
       return;
     default:
       break;
     }
+  } else {
+    if (Constraint == "vi") {
+      if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
+        int64_t CVal = C->getSExtValue();
+        if (isInt<5>(CVal))
+          Ops.push_back(
+              DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
+      }
+    } else if (Constraint == "vj") {
+      if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
+        int64_t CVal = C->getSExtValue();
+        if (isInt<5>(-CVal))
+          Ops.push_back(
+              DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
+      }
+    } else if (Constraint == "vk") {
+      if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
+        uint64_t CVal = C->getZExtValue();
+        if (isUInt<5>(CVal))
+          Ops.push_back(
+              DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
+      }
+    }
   }
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
                                                    Instruction *Inst,
                                                    AtomicOrdering Ord) const {
   if (Subtarget.hasStdExtZtso()) {

llvm/test/CodeGen/RISCV/rvv/inline-asm-invalid.ll

+; RUN: not llc -mtriple=riscv64 -mattr=+v < %s 2>&1 | FileCheck %s
+
+define <vscale x 1 x i32> @test_vi(<vscale x 1 x i32> %in) nounwind {
+entry:
+; CHECK: error: value out of range for constraint 'vi'
+  %0 = tail call <vscale x 1 x i32> asm "vadd.vi $0, $1, $2", "=^vr,^vr,^vi"(<vscale x 1 x i32> %in, i32 -17)
+; CHECK: error: value out of range for constraint 'vi'
+  %1 = tail call <vscale x 1 x i32> asm "vadd.vi $0, $1, $2", "=^vr,^vr,^vi"(<vscale x 1 x i32> %0, i32 16)
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i1> @test_vj(<vscale x 1 x i32> %in) nounwind {
+entry:
+; CHECK: error: value out of range for constraint 'vj'
+  %0 = tail call <vscale x 1 x i1> asm "vmslt.vi $0, $1, $2", "=^vr,^vr,^vj"(<vscale x 1 x i32> %in, i32 -16)
+; CHECK: error: value out of range for constraint 'vj'
+  %1 = tail call <vscale x 1 x i1> asm "vmslt.vi $0, $1, $2", "=^vr,^vr,^vj"(<vscale x 1 x i32> %in, i32 17)
+  %2 = and <vscale x 1 x i1> %0, %1
+  ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i32> @test_vk(<vscale x 1 x i32> %in) nounwind {
+entry:
+; CHECK: error: value out of range for constraint 'vk'
+  %0 = tail call <vscale x 1 x i32> asm "vsll.vi $0, $1, $2", "=^vr,^vr,^vk"(<vscale x 1 x i32> %in, i32 -1)
+; CHECK: error: value out of range for constraint 'vk'
+  %1 = tail call <vscale x 1 x i32> asm "vsll.vi $0, $1, $2", "=^vr,^vr,^vk"(<vscale x 1 x i32> %0, i32 32)
+  ret <vscale x 1 x i32> %1
+}

llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    vmand.mm v0, v1, v2
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call <vscale x 1 x i1> asm "vmand.mm $0, $1, $2", "={v0},{v1},{v2}"(<vscale x 1 x i1> %in, <vscale x 1 x i1> %in2)
   ret <vscale x 1 x i1> %0
 }
+
+define <vscale x 1 x i32> @test_vi(<vscale x 1 x i32> %in) nounwind {
+; CHECK-LABEL: test_vi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vadd.vi v8, v8, -16
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vadd.vi v8, v8, 15
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 1 x i32> asm "vadd.vi $0, $1, $2", "=^vr,^vr,^vi"(<vscale x 1 x i32> %in, i32 -16)
+  %1 = tail call <vscale x 1 x i32> asm "vadd.vi $0, $1, $2", "=^vr,^vr,^vi"(<vscale x 1 x i32> %0, i32 15)
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i1> @test_vj(<vscale x 1 x i32> %in) nounwind {
+; CHECK-LABEL: test_vj:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vmsle.vi v9, v8, -16
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vmsle.vi v8, v8, 15
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vmand.mm v0, v9, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 1 x i1> asm "vmslt.vi $0, $1, $2", "=^vr,^vr,^vj"(<vscale x 1 x i32> %in, i32 -15)
+  %1 = tail call <vscale x 1 x i1> asm "vmslt.vi $0, $1, $2", "=^vr,^vr,^vj"(<vscale x 1 x i32> %in, i32 16)
+  %2 = and <vscale x 1 x i1> %0, %1
+  ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i32> @test_vk(<vscale x 1 x i32> %in) nounwind {
+; CHECK-LABEL: test_vk:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vsll.vi v8, v8, 0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vsll.vi v8, v8, 31
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 1 x i32> asm "vsll.vi $0, $1, $2", "=^vr,^vr,^vk"(<vscale x 1 x i32> %in, i32 0)
+  %1 = tail call <vscale x 1 x i32> asm "vsll.vi $0, $1, $2", "=^vr,^vr,^vk"(<vscale x 1 x i32> %0, i32 31)
+  ret <vscale x 1 x i32> %1
+}