[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Summary

CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)

This first patch handles integer types.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns as follows: ` CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C) CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C) ` This first patch handles integer types.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[foad]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

52–53

• RISCV was already doing this optimization - where?
• Your result is different - it uses maxu instead of minu. One of them must be wrong.

311–312

The point of this test is that it should not be optimized because the comparisons are different: c< vs c>. Yet you have optimized it.

[foad]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6076

I don't understand why you handle constants differently from non-constants. Are you worried about two different constant nodes having the same constant value?

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

52–53

@ilya Andreev: How is this optimization done in RISCV?

I fixed the bug.

[craig.topper]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

52–53

The RISC-V code in combineCmpOp in RISCVISelLowering.cpp

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6050

What is LHS0 == RHS1 or LHS1 == RHS0 and CCL is the opposite of condition CCR?

6078

Capitalize variable name

6088

Could we invert the condition code so that the common value is always on the "left"? Then we don't need a bool and could simplify the next if.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6050

Let's take the following test case from zbb-cmp-combine.ll:
define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: no_same_ops:
; CHECK: # %bb.0:
; CHECK-NEXT: sltu a1, a0, a1
; CHECK-NEXT: sltu a0, a2, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret

%l0 = icmp ult i64 %c, %a
%l1 = icmp ugt i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res

Here, the predicate of the second compare instruction(ugt) is replaced with ult and the operands are swapped and we have

icmp ult i64 %c, %a
icmp ult i64 %b, %c

If we apply the proposed optimization, then we will have correctness issues.

6078

I removed it.

[kmitropoulou]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6050

I am sorry I misunderstood it earlier. I will add this case.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6050

What is LHS0 == RHS1 or LHS1 == RHS0 and CCL is the opposite of condition CCR?

I added this case.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[foad]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6037

It is weird to pass in LHS and RHS as arguments to this function, but then examine their operands LHS0 etc by capture from the enclosing scope. I suggest changing this function to take no arguments.

6040

Don't add comments that just say *what* the code does. If there is nothing interesting to say about *why* you are checking for one use, just remove the comment.

6068

I would suggest writing these on a single line, like most of the other comments in this file, e.g.:

(lhs0 < lhs1) | (rhs0 < rhs2) -> min(lhs0, rhs0) < lhs1

6082

It seems wrong to check TargetPreference here. TargetPreference currently only controls the desired combine behaviour for a combination of eq or ne comparisons. Your new combine does not overlap with this, since it only works for non-eq/ne comparisons. So why would you only do it if the target does *not* want to combine eq/ne comparisons?

6088

AreSameCMPsAndHaveCommonOperand already checks the various different cases of CCL==CCR etc and LHS0==RHS0 etc, and now you have to check them again here. To avoid the duplication why not just inline AreSameCMPsAndHaveCommonOperand here? You could set CC=SETCC_INVALID at the start, then go through the cases, then test CC==SETCC_INVALID to see if any of them matched.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6082

Thank you :)

[kmitropoulou]

ping

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6037

Is this just using LHS/RHS? Use explicit arguments and drop the default capture all?

[kmitropoulou]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6037

No, it also uses the operands of LHS/RHS (LHS0, LHS1, RHS0, RHS1) and their condition code (CCL, CCR). If I drop '&', then I should pass 8 arguments or I should pass LHS and RHS and recalculate the other 6 values. So, I did not do it.

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[kmitropoulou]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6088

I am sorry I missed this comment. I addressed it in the latest patch.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6036

Remove comma after "Replace"

6038

sequence8

6053

comparisons*

6054

Drop curly braces around (CCL == ISD::getSetCCSwappedOperands(CCR))

6056

!ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEquality(CCR)

6058

Is this the same as CCL == CCR?

6097

Can NewOpcode ever be unassigned here?

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6058

You are right! This condition should be CCL == CCR and the condition at line 6071 should be CCL == ISD::getSetCCSwappedOperands(CCR) .

6097

You are right! It is not needed here.

[craig.topper]

LGTM

[kmitropoulou]

Updating D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
   SDValue RHS = LogicOp->getOperand(1);
   if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC)
     return SDValue();
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   AndOrSETCCFoldKind TargetPreference = TLI.isDesirableToCombineLogicOpOfSETCC(
       LogicOp, LHS.getNode(), RHS.getNode());
 
-  if (TargetPreference == AndOrSETCCFoldKind::None)
-    return SDValue();
-
-  ISD::CondCode CCL = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
-  ISD::CondCode CCR = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
-
   SDValue LHS0 = LHS->getOperand(0);
   SDValue RHS0 = RHS->getOperand(0);
   SDValue LHS1 = LHS->getOperand(1);
   SDValue RHS1 = RHS->getOperand(1);
-
   // TODO: We don't actually need a splat here, for vectors we just need the
   // invariants to hold for each element.
   auto *LHS1C = isConstOrConstSplat(LHS1);
   auto *RHS1C = isConstOrConstSplat(RHS1);
-
+  ISD::CondCode CCL = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
+  ISD::CondCode CCR = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
   EVT VT = LogicOp->getValueType(0);
   EVT OpVT = LHS0.getValueType();
   SDLoc DL(LogicOp);
 
+  // Returns true if both arguments are compare instructions with the same
+  // predicate and have a common operand.
+  auto AreSameCMPsAndHaveCommonOperand = [&]() {
+    if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC)
+      return false;
+    if (!LHS->hasOneUse() || !RHS->hasOneUse())
+      return false;
+    // Check if the predicates are the same.
+    if (CCL != CCR) {
+      // If one predicate is the opposite of the other and they have a common
+      // operand, then we can still apply the optimization:
+      // a < c    a < c
+      //       =>       => min(a, b) < c
+      // c > b    b < c
+      if (CCL == ISD::getSetCCSwappedOperands(CCR))
+        if (LHS0 == RHS1 || RHS0 == LHS1)
+          return true;
+      return false;
+    }
+    // The optimization does not work for `==` or `!=`.
+    if (CCL == ISD::SETEQ || CCL == ISD::SETNE)
+      return false;
+    // Check if the two compare instructions have a common operand.
+    return LHS0 == RHS0 || LHS1 == RHS1;
+  };
+
+  // Check if the operands of an and/or operation are comparisons and if they
+  // compare against the same value. Replace, the and/or-cmp-cmp sequence with
+  // min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp
+  // sequrence will be replaced with min-cmp sequence:
+  // (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1
+  // and and-cmp-cmp will be replaced with max-cmp sequence:
+  // (LHS0 < LHS1) & (RHS0 < RHS1) -> max(LHS0, RHS0) < LHS1
+  if (OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
+      TLI.isOperationLegal(ISD::SMAX, OpVT) &&
+      AreSameCMPsAndHaveCommonOperand()) {
+    SDValue CommonValue;
+    SDValue Operand1;
+    SDValue Operand2;
+    ISD::CondCode CC = CCL;
+    if (LHS0 == RHS0) {
+      CommonValue = LHS0;
+      Operand1 = LHS1;
+      Operand2 = RHS1;
+      CC = ISD::getSetCCSwappedOperands(CCL);
+    } else if (LHS1 == RHS1) {
+      CommonValue = LHS1;
+      Operand1 = LHS0;
+      Operand2 = RHS0;
+    } else if (CCL == ISD::getSetCCSwappedOperands(CCR)) {
+      if (LHS0 == RHS1) {
+        CommonValue = LHS0;
+        Operand1 = LHS1;
+        Operand2 = RHS0;
+        CC = ISD::getSetCCSwappedOperands(CCL);
+      } else if (LHS1 == RHS0) {
+        CommonValue = LHS1;
+        Operand1 = LHS0;
+        Operand2 = RHS1;
+      }
+    }
+    bool IsSigned = isSignedIntSetCC(CC);
+    unsigned NewOpcode;
+    if (((CC == ISD::SETLE || CC == ISD::SETULE || CC == ISD::SETLT ||
+          CC == ISD::SETULT) &&
+         (LogicOp->getOpcode() == ISD::OR)) ||
+        ((CC == ISD::SETGE || CC == ISD::SETUGE || CC == ISD::SETGT ||
+          CC == ISD::SETUGT) &&
+         (LogicOp->getOpcode() == ISD::AND))) {
+      NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
+    } else {
+      NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
+    }
+    SDValue MinMaxValue = DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
+    return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
+  }
+
+  if (TargetPreference == AndOrSETCCFoldKind::None)
+    return SDValue();
+
   if (CCL == CCR &&
       CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) &&
       LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger() && LHS.hasOneUse() &&
       RHS.hasOneUse()) {
     const APInt &APLhs = LHS1C->getAPIntValue();
     const APInt &APRhs = RHS1C->getAPIntValue();
 
     // Preference is to use ISD::ABS or we already have an ISD::ABS (in which

llvm/test/CodeGen/AArch64/vecreduce-bool.ll

; CHECK-NEXT:    ret
   %y = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }
 
 define i32 @reduce_and_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-LABEL: reduce_and_v32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    smax v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    uminv b0, v0.16b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    tst w8, #0x1
 ; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <32 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %x)
; CHECK-NEXT:    ret
   %y = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }
 
 define i32 @reduce_or_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-LABEL: reduce_or_v32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    smin v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    umaxv b0, v0.16b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    tst w8, #0x1
 ; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <32 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }

llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll

bb:
   %add = add i32 %v, %ext
   store i32 %add, ptr addrspace(1) %gep, align 4
   ret void
 }
 
 define amdgpu_kernel void @add_and(ptr addrspace(1) nocapture %arg) {
 ; GCN-LABEL: add_and:
 ; GCN:       ; %bb.0: ; %bb
-; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, 0
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, 0
 ; GCN-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    buffer_load_dword v4, v[2:3], s[4:7], 0 addr64
-; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, v0, v1
-; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 1, v0
-; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
+; GCN-NEXT:    buffer_load_dword v4, v[2:3], s[0:3], 0 addr64
+; GCN-NEXT:    v_max_u32_e32 v1, 1, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, v1, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v4, vcc
-; GCN-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
+; GCN-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; GCN-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: add_and:
 ; GFX9:       ; %bb.0: ; %bb
-; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
-; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, v0, v1
-; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], 1, v0
-; GFX9-NEXT:    s_and_b64 vcc, vcc, s[0:1]
+; GFX9-NEXT:    v_max_u32_e32 v1, 1, v1
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, v1, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dword v3, v2, s[2:3]
+; GFX9-NEXT:    global_load_dword v3, v2, s[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
-; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
+; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 bb:
   %x = tail call i32 @llvm.amdgcn.workitem.id.x()
   %y = tail call i32 @llvm.amdgcn.workitem.id.y()
   %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %x
   %v = load i32, ptr addrspace(1) %gep, align 4
   %cmp1 = icmp ugt i32 %x, %y
   %cmp2 = icmp ugt i32 %x, 1

llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s
 
 ; The tests check the following optimization of DAGCombiner:
 ; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
 ; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)
 
 define i1 @test1(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, 1000
   %cmp2 = icmp slt i32 %arg2, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test2(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, 1000
   %cmp2 = icmp ult i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test3(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e9, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test4(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e9, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test5(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test5:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test6(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test6:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, 1000
   %cmp2 = icmp ugt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test7(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test7:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, 0x3e7, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test8(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, 0x3e7, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, 1000
   %cmp2 = icmp uge i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test9:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test10:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test11:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test12:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, %arg3
   %cmp2 = icmp ule i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test13:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test14:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, %arg3
   %cmp2 = icmp ugt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test15:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test16:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test17(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test17:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, 1000
   %cmp2 = icmp slt i32 %arg2, 1000
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test18(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test18:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, 1000
   %cmp2 = icmp ult i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test19(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test19:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e9, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test20(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test20:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e9, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test21(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test21:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test22(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test22:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, 1000
   %cmp2 = icmp ugt i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test23(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test23:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, 0x3e7, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test24(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test24:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, 0x3e7, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, 1000
   %cmp2 = icmp uge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test25:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test26:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test27:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test28:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, %arg3
   %cmp2 = icmp ule i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test29:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test30:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, %arg3
   %cmp2 = icmp ugt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test31:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test32:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test33(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: test33:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e8, v0
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_max_i32_e32 v1, 0x3e8, v1
+; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v1, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg2
   %cmp2 = icmp slt i32 %arg1, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test34(i32 %arg1, i64 %arg2) {
; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2) {
 ; CHECK-LABEL: test37:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmpk_lt_i32 s4, 0x3e9
+; CHECK-NEXT:    s_min_i32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmpk_lt_i32 s5, 0x3e9
+; CHECK-NEXT:    s_cmpk_lt_i32 s0, 0x3e9
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) {
 ; CHECK-LABEL: test38:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmpk_gt_i32 s4, 0x3e8
+; CHECK-NEXT:    s_max_i32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmpk_gt_i32 s5, 0x3e8
+; CHECK-NEXT:    s_cmpk_gt_i32 s0, 0x3e8
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
 ; CHECK-LABEL: test39:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmp_lt_u32 s4, s6
+; CHECK-NEXT:    s_min_u32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmp_lt_u32 s5, s6
+; CHECK-NEXT:    s_cmp_lt_u32 s0, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
 ; CHECK-LABEL: test40:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmp_ge_i32 s4, s6
+; CHECK-NEXT:    s_max_i32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmp_ge_i32 s5, s6
+; CHECK-NEXT:    s_cmp_ge_i32 s0, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2) {
 ; CHECK-LABEL: test41:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmpk_lt_u32 s4, 0x3e9
+; CHECK-NEXT:    s_max_u32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmpk_lt_u32 s5, 0x3e9
+; CHECK-NEXT:    s_cmpk_lt_u32 s0, 0x3e9
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test42(i32 inreg %arg1, i32 inreg %arg2) {
 ; CHECK-LABEL: test42:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmpk_gt_i32 s4, 0x3e7
+; CHECK-NEXT:    s_min_i32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmpk_gt_i32 s5, 0x3e7
+; CHECK-NEXT:    s_cmpk_gt_i32 s0, 0x3e7
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test43(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
 ; CHECK-LABEL: test43:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmp_le_i32 s4, s6
+; CHECK-NEXT:    s_max_i32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmp_le_i32 s5, s6
+; CHECK-NEXT:    s_cmp_le_i32 s0, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test44(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
 ; CHECK-LABEL: test44:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_cmp_ge_u32 s4, s6
+; CHECK-NEXT:    s_min_u32 s0, s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    s_cmp_ge_u32 s5, s6
+; CHECK-NEXT:    s_cmp_ge_u32 s0, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s1, -1, 0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
 ; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
 ; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test45:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg3, %arg1
   %cmp2 = icmp ult i32 %arg3, %arg2
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test46:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg3, %arg1
   %cmp2 = icmp ult i32 %arg3, %arg2
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 
+
 define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test47:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg3, %arg1
   %cmp2 = icmp ugt i32 %arg3, %arg2
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test48:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg3, %arg1
   %cmp2 = icmp ugt i32 %arg3, %arg2
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test49(i64 %arg1, i64 %arg2, i64 %arg3) {
; CHECK-NEXT:    s_setpc_b64 s[30:31]
    %or = or i1 %cmp1, %cmp2
    ret i1 %or
 }
 
 define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test50:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg3, %arg1
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test51:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg3, %arg2
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test52:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg3, %arg2
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test53:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg3, %arg1
   %cmp2 = icmp slt i32 %arg2, %arg3
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test54(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test54:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg3, %arg1
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test55(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test55:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg3, %arg2
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test56(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test56:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg3, %arg2
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test57(i32 %arg1, i32 %arg2, i32 %arg3) {
 ; CHECK-LABEL: test57:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_lt_i32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg3, %arg1
   %cmp2 = icmp slt i32 %arg2, %arg3
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 ; The optimization does not apply to the following tests.

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %b = icmp eq <4 x i32> %Q, zeroinitializer
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxleqv 36, 36, 36
-; CHECK-NEXT:    xxlor 34, 34, 35
-; CHECK-NEXT:    vcmpgtsw 2, 2, 4
+; CHECK-NEXT:    vminsw 2, 2, 3
+; CHECK-NEXT:    xxleqv 35, 35, 35
+; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_bits_set_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_set_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxlxor 36, 36, 36
-; CHECK-NEXT:    xxland 34, 34, 35
-; CHECK-NEXT:    vcmpgtsw 2, 4, 2
+; CHECK-NEXT:    vmaxsw 2, 2, 3
+; CHECK-NEXT:    xxlxor 35, 35, 35
+; CHECK-NEXT:    vcmpgtsw 2, 3, 2
 ; CHECK-NEXT:    blr
   %a = icmp slt <4 x i32> %P, zeroinitializer
   %b = icmp slt <4 x i32> %Q, zeroinitializer
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_set_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlxor 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    xxlnor 34, 34, 34
 ; CHECK-NEXT:    blr
   %a = icmp ne <4 x i32> %P, zeroinitializer
   %b = icmp ne <4 x i32> %Q, zeroinitializer
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_set_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxlxor 36, 36, 36
-; CHECK-NEXT:    xxlor 34, 34, 35
-; CHECK-NEXT:    vcmpgtsw 2, 4, 2
+; CHECK-NEXT:    vminsw 2, 2, 3
+; CHECK-NEXT:    xxlxor 35, 35, 35
+; CHECK-NEXT:    vcmpgtsw 2, 3, 2
 ; CHECK-NEXT:    blr
   %a = icmp slt <4 x i32> %P, zeroinitializer
   %b = icmp slt <4 x i32> %Q, zeroinitializer
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_clear_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    xxlnor 34, 34, 34
 ; CHECK-NEXT:    blr
   %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxleqv 36, 36, 36
-; CHECK-NEXT:    xxland 34, 34, 35
-; CHECK-NEXT:    vcmpgtsw 2, 2, 4
+; CHECK-NEXT:    vmaxsw 2, 2, 3
+; CHECK-NEXT:    xxleqv 35, 35, 35
+; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

; CHECK-NEXT:    ret
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ulo_swap12(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ulo_swap12:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    minu a1, a1, a2
 ; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ugt i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 ; 4 patterns below will be converted to umax+less.
 define i1 @ula(i64 %c, i64 %a, i64 %b) {

 ; CHECK-RV64I-NEXT:    mv s1, a0
 ; CHECK-RV64I-NEXT:    mv a0, a1
 ; CHECK-RV64I-NEXT:    mv a1, s1
 ; CHECK-RV64I-NEXT:    call __gesf2@plt
 ; CHECK-RV64I-NEXT:    mv s2, a0
 ; CHECK-RV64I-NEXT:    mv a0, s0
 ; CHECK-RV64I-NEXT:    mv a1, s1
 ; CHECK-RV64I-NEXT:    call __gesf2@plt
-; CHECK-RV64I-NEXT:    or a0, s2, a0
+; CHECK-RV64I-NEXT:    min a0, s2, a0
 ; CHECK-RV64I-NEXT:    slti a0, a0, 0
 ; CHECK-RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    addi sp, sp, 32
 ; CHECK-RV64I-NEXT:    ret
 ;

 ; CHECK-NEXT:    mv s1, a0
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    mv a1, s1
 ; CHECK-NEXT:    call __gedf2@plt
 ; CHECK-NEXT:    mv s2, a0
 ; CHECK-NEXT:    mv a0, s0
 ; CHECK-NEXT:    mv a1, s1
 ; CHECK-NEXT:    call __gedf2@plt
-; CHECK-NEXT:    or a0, s2, a0
+; CHECK-NEXT:    min a0, s2, a0
 ; CHECK-NEXT:    slti a0, a0, 0
 ; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %l0 = fcmp ult double %a, %c

 
 ; Negative test
 ; No same comparations
 define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: no_same_ops:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sltu a1, a0, a1
 ; CHECK-NEXT:    sltu a0, a2, a0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %c, %a
   %l1 = icmp ugt i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }