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[RISCV] Add codegen for Zfbfmin instructions

Authored by joshua-arch1 on Jun 18 2023, 6:40 PM.



The implementation in is done for the circumstance without Zfbfmin. This patch adds codegen support for the 6 instructions provided in Zfbfmin extension.

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joshua-arch1 created this revision.Jun 18 2023, 6:40 PM
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joshua-arch1 requested review of this revision.Jun 18 2023, 6:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 18 2023, 6:40 PM

To avoid crash in AArch64, ConstantFP nodes default to expand only in RISCV.

Rebase, as well as change the operand type in riscv_fpround_bf16/riscv_fpextend_bf16 from f16 to bf16.

craig.topper added inline comments.Jun 25 2023, 12:12 AM

Is this change tested?


These patterns duplicate patterns from HasStdExtZfhOrZfhmin, can we share them by using a new predicate?

245 ↗(On Diff #532776)

Can we just add bf16 to the type list for FPR16? If the only reason to have a separate register class is for tablegen type inference, I don't thinks that a good reason.

asb added a comment.Jul 12 2023, 8:18 AM

@joshua-arch1 are you still planning to work through the review feedback from Craig? Happy to help if useful.

joshua-arch1 added a comment.EditedJul 16 2023, 7:12 PM

@joshua-arch1 are you still planning to work through the review feedback from Craig? Happy to help if useful.

@craig.topper Ping.
@asb Sorry for the delay! I have replied to Craig, but there is no feedback again.


define bfloat @bfloat_imm() nounwind {
; CHECKIZFBFMIN-NEXT: lui a0, %hi(.LCPI6_0)
; CHECKIZFBFMIN-NEXT: flh fa0, %lo(.LCPI6_0)(a0)

ret bfloat 3.0


In this case, we need this change to address bf16 constant.

245 ↗(On Diff #532776)

I have tried to add bf16 to the type list for FPR16, but that needs to modify almost all the patterns with f16 for type inference, which will be heavy work. Also, bf16 is used only in some special cases. I think addressing this type in an individual part will be better. Mixing bf16 and f16 together will make fp16 instructions hard to maintain. I'm wondering why you don't think this is a good reason.

craig.topper added inline comments.Jul 16 2023, 7:59 PM

I thought this function is supposed to return true for constants that don't need a constant pool. Your test for 3.0 is using a constant pool, which I think means this function is returning false for 3.0. Wouldn't that be the behavior you got without this change?

245 ↗(On Diff #532776)

This ends up creating two register classes that are circularly subclasses of each other. I think RISCVInstrInfo::loadRegFromStackSlot for BFPR16 only works because RISCV::FPR16RegClass.hasSubClassEq(RISCV::BFPR16) returns true?

I'm not sure RISCVInstrInfo::copyPhysReg works at all unless Zfh or Zfhmin is also enabled? Is that tested?

Use predicate HasScalarHalfFPLoadStoreMove for patterns that f16 and bf16 share

Use the FPR16 register class for bf16 instructions

craig.topper added inline comments.Jul 19 2023, 9:37 PM

The patterns need to be duplicated for bf16. I think it accidentally works now because the type type profile says they only take f16 types so tablegen optimized out the checks.

We need to relax the types in the type constraints and add new patterns.

def SDT_RISCVFMV_H_X                                                             
    : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;              
def SDT_RISCVFMV_X_EXTH                                                          
    : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
craig.topper added inline comments.Jul 19 2023, 9:39 PM

Can we put these patterns in the If the include order doesn't work, I hope we can just fix the include order so that Zfh is included first.

Move bf16 patterns into

craig.topper added inline comments.Jul 20 2023, 9:34 PM

There's only supposed to be one SDNode declaration per RISCVISD opcode name. The SDTypeProfile for the existing version needs to be changed to SDTCisFP instead of SDTCisVT<1, f16>. The semantics of the opcode changed, so the type description needs to change accordingly.

joshua-arch1 marked 5 inline comments as done.

Relax the types in the type constraints for SDT_RISCVFMV_H_X and SDT_RISCV_FMV_X_EXTH

craig.topper accepted this revision.Jul 21 2023, 9:47 AM



space after f16

This revision is now accepted and ready to land.Jul 21 2023, 9:47 AM
This revision was landed with ongoing or failed builds.Jul 23 2023, 7:38 PM
This revision was automatically updated to reflect the committed changes.
joshua-arch1 marked an inline comment as done.