[RISCV] Add support for XCVmac extension in CV32E40P

[realqhc]

Summary

Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td

1 ↗

(On Diff #530924)

This line is 1 character longer than 80 characters

126 ↗

(On Diff #530924)

Please fix the missing newline

llvm/test/MC/RISCV/corev/mac/invalid.s

5 ↗

(On Diff #530924)

Please add {{$}} to the end of these lines so it checks to the end of the line.

llvm/test/MC/RISCV/corev/mac/mac.s

1 ↗

(On Diff #530924)

Can we merge the per instruction tests into a single file? I think that's what's done for most extensions.

[realqhc]

address reviewer's concerns, fixed format on RISCVInstrInfoXCvmac.td, reorganized the tests, and added checks for newline in error messages.

[craig.topper]

Is this extension RV32 only? I notice the shift amounts are only uimm5. Should we restrict with Predicates = [IsRV32]?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td

119 ↗

(On Diff #531074)

Why Emit = 0 here?

[realqhc]

llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td

119 ↗

(On Diff #531074)

This is the current design for Core-V's GAS implementation. Also, setting it to non-zero may cause issue with cv.mulsn ..., ..., 0 but that may not exist apart from some test cases.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td

119 ↗

(On Diff #531074)

Why are implementation details in gas at all relevant? This is LLVM not GNU binutils.

[realqhc]

restrict the instruction to rv32 only, edit the documentations

[realqhc]

address reviewers' concerns, restrict the instructions to RV32, remove unnecessary emit=0 and add -riscv-no-aliases for tests instead.

[lewis-revill]

I would say that this looks good to me, I only have nitpicks rather than any real issues.

I wonder whether we should write the human-readable version (and thus filenames for tests) of the extension as XCVmac rather than XCvmac. The argument would be that currently I read this almost as an extension called vmac for a vendor with the initial C. Though given we are writing XSfvcp maybe keeping it as it is would match that better. If no other reviewers have a preference I would say it's up to you. Either way the predicate text "'Xcvmac' (Multiply-Accumulate)" should be changed to match whatever you decide.

The final thing that also doesn't matter too much is that maybe the test filename for valid MC output should end in -valid.s.

[realqhc]

implement naming change XCvmac->XCVmac, make error message consistent with naming.

[realqhc]

make disassembler decoder table description more consistent.

[realqhc]

re-name the file to RISCVInstrInfoXCV so that future Core-V extensions can be added in the same file.

[realqhc]

fix header

[craig.topper]

llvm/test/MC/RISCV/corev/XCVmac-valid.s

3

Can we check disassembler too?

[realqhc]

add test for objdump

[craig.topper]

LGTM

[realqhc]

rebase

llvm/docs/RISCVUsage.rst

 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XCVbitmanip``
   LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
+
+``XCVmac``
+  LLVM implements `version 1.3.1 of the Core-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.mac.` as described in the specification. These instructions are only available for riscv32 at this time.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
                           "XTHeadSync custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableTHeadV32,
                           "XTHeadVdot custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
+                          "CORE-V MAC custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
     return MCDisassembler::Fail;
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXCVbitmanip
     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
                        "'XCVbitmanip' (Bit Manipulation)">;
 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
                                 "'XCVbitmanip' (Bit Manipulation)">;
 
+def FeatureVendorXCVmac
+    : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
+                       "'XCVmac' (Multiply-Accumulate)">;
+def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
+                                AssemblerPredicate<(all_of FeatureVendorXCVmac),
+                                "'XCVmac' (Multiply-Accumulate)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

let DecoderNamespace = "XCVbitmanip" in {
   class RVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
       : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
     bits<5> is3;
     bits<5> is2;
     let imm12 = {funct2, is3, is2};
   }
 
-  class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr, 
+  class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
                       Operand i3type = uimm5>
-      : RVInstBitManipRII<funct2, funct3, (outs GPR:$rd), 
+      : RVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
                           (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
                           opcodestr, "$rd, $rs1, $is3, $is2">;
 
   class CVBitManipRR<bits<7> funct7, string opcodestr>
-      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 
+      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
                 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVBitManipR<bits<7> funct7, string opcodestr>
-      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 
+      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
                 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1"> {
     let rs2 = 0b00000;
   }
 }
 
-let Predicates = [HasVendorXCVbitmanip, IsRV32], 
+let Predicates = [HasVendorXCVbitmanip, IsRV32],
     hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
   def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
 
   def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
   def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
   def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
 
   def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
   def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
 
   let Constraints = "$rd = $rd_wb" in {
     def CV_INSERT : RVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
                              (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
                              "cv.insert", "$rd, $rs1, $is3, $is2">;
-    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb), 
-                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2), 
+    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
+                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                              "cv.insertr", "$rd, $rs1, $rs2">;
   }
 
   def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
   def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
 
   def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
   def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
   def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
   def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
   def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
 }
+
+class CVInstMac<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_CUSTOM_1.Value;
+  let DecoderNamespace = "XCVmac";
+}
+
+class CVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
+                   string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> imm5;
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-30} = funct2;
+  let Inst{29-25} = imm5;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_CUSTOM_2.Value;
+  let DecoderNamespace = "XCVmac";
+}
+
+let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$rd = $rd_wb" in {
+  // 32x32 bit macs
+  def CV_MAC      : CVInstMac<0b1001000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                              "cv.mac", "$rd, $rs1, $rs2", []>,
+                    Sched<[]>;
+  def CV_MSU      : CVInstMac<0b1001001, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                              "cv.msu", "$rd, $rs1, $rs2", []>,
+                    Sched<[]>;
+
+  // Signed 16x16 bit macs with imm
+  def CV_MACSN    : CVInstMac16I<0b00, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.macsn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACHHSN  : CVInstMac16I<0b01, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.machhsn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACSRN   : CVInstMac16I<0b10, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.macsrn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACHHSRN : CVInstMac16I<0b11, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.machhsrn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+
+  // Unsigned 16x16 bit macs with imm
+  def CV_MACUN    : CVInstMac16I<0b00, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.macun", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACHHUN  : CVInstMac16I<0b01, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.machhun", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACURN   : CVInstMac16I<0b10, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.macurn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MACHHURN : CVInstMac16I<0b11, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.machhurn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$rd = $rd_wb"
+
+let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  // Signed 16x16 bit muls with imm
+  def CV_MULSN    : CVInstMac16I<0b00, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulsn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULHHSN  : CVInstMac16I<0b01, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulhhsn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULSRN   : CVInstMac16I<0b10, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulsrn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULHHSRN : CVInstMac16I<0b11, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulhhsrn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+
+
+  // Unsigned 16x16 bit muls with imm
+  def CV_MULUN    : CVInstMac16I<0b00, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulun", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULHHUN  : CVInstMac16I<0b01, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulhhun", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULURN   : CVInstMac16I<0b10, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulurn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+  def CV_MULHHURN : CVInstMac16I<0b11, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                 "cv.mulhhurn", "$rd, $rs1, $rs2, $imm5", []>,
+                    Sched<[]>;
+} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Predicates = [HasVendorXCVmac, IsRV32] in {
+  // Xcvmac Pseudo Instructions
+  // Signed 16x16 bit muls
+  def : InstAlias<"cv.muls $rd1, $rs1, $rs2",   (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
+  def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2", (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
+
+  // Unsigned 16x16 bit muls
+  def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
+  def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2", (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
+} // Predicates = [HasVendorXCVmac, IsRV32]

llvm/test/MC/RISCV/corev/XCVmac-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmac %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.mac t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mac t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mac 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mac t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.mac t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.machhsn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhsrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhsrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.machhsrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.machhun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.machhurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.machhurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.machhurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.macsn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macsrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macsrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.macsrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.macun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.macurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.macurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.macurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.msu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.msu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.msu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.msu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.msu t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhs t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhs t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhs 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhs t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhs t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhsn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhsrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhsrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhsrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhu t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulhhurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulhhurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulhhurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.muls t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.muls t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.muls 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.muls t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.muls t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulsn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulsrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulsrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulsrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulu t0, t1, t2, t4
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.mulurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.mulurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.mulurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction

llvm/test/MC/RISCV/corev/XCVmac-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmac -riscv-no-aliases -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmac < %s \
+# RUN:     | llvm-objdump --mattr=+xcvmac -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.mac t0, t1, t2
+# CHECK-INSTR: cv.mac t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x90]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mac t0, t1, zero
+# CHECK-INSTR: cv.mac t0, t1, zero
+# CHECK-ENCODING: [0xab,0x32,0x03,0x90]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsn t0, t1, t2, 0
+# CHECK-INSTR: cv.machhsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x62,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsn t0, t1, zero, 16
+# CHECK-INSTR: cv.machhsn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x62,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsn t0, t1, zero, 31
+# CHECK-INSTR: cv.machhsn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x62,0x03,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsrn t0, t1, t2, 0
+# CHECK-INSTR: cv.machhsrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x62,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsrn t0, t1, zero, 16
+# CHECK-INSTR: cv.machhsrn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x62,0x03,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhsrn t0, t1, zero, 31
+# CHECK-INSTR: cv.machhsrn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x62,0x03,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhun t0, t1, t2, 0
+# CHECK-INSTR: cv.machhun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x72,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhun t0, t1, zero, 16
+# CHECK-INSTR: cv.machhun t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x72,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhun t0, t1, zero, 31
+# CHECK-INSTR: cv.machhun t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x72,0x03,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhurn t0, t1, t2, 0
+# CHECK-INSTR: cv.machhurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x72,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhurn t0, t1, zero, 16
+# CHECK-INSTR: cv.machhurn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x72,0x03,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.machhurn t0, t1, zero, 31
+# CHECK-INSTR: cv.machhurn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x72,0x03,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsn t0, t1, t2, 0
+# CHECK-INSTR: cv.macsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x62,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsn t0, t1, zero, 16
+# CHECK-INSTR: cv.macsn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x62,0x03,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsn t0, t1, zero, 31
+# CHECK-INSTR: cv.macsn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x62,0x03,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsrn t0, t1, t2, 0
+# CHECK-INSTR: cv.macsrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x62,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsrn t0, t1, zero, 16
+# CHECK-INSTR: cv.macsrn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x62,0x03,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macsrn t0, t1, zero, 31
+# CHECK-INSTR: cv.macsrn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x62,0x03,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macun t0, t1, t2, 0
+# CHECK-INSTR: cv.macun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x72,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macun t0, t1, zero, 16
+# CHECK-INSTR: cv.macun t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x72,0x03,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macun t0, t1, zero, 31
+# CHECK-INSTR: cv.macun t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x72,0x03,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macurn t0, t1, t2, 0
+# CHECK-INSTR: cv.macurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x72,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macurn t0, t1, zero, 16
+# CHECK-INSTR: cv.macurn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x72,0x03,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.macurn t0, t1, zero, 31
+# CHECK-INSTR: cv.macurn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x72,0x03,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.msu t0, t1, t2
+# CHECK-INSTR: cv.msu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x92]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.msu t0, t1, zero
+# CHECK-INSTR: cv.msu t0, t1, zero
+# CHECK-ENCODING: [0xab,0x32,0x03,0x92]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhs t0, t1, t2
+# CHECK-INSTR: cv.mulhhsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhs t0, t1, zero
+# CHECK-INSTR: cv.mulhhsn t0, t1, zero, 0
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulhhsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulhhsn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulhhsn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsrn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulhhsrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsrn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulhhsrn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x42,0x03,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhsrn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulhhsrn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x42,0x03,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhu t0, t1, t2
+# CHECK-INSTR: cv.mulhhun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhu t0, t1, zero
+# CHECK-INSTR: cv.mulhhun t0, t1, zero, 0
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhun t0, t1, t2, 0
+# CHECK-INSTR: cv.mulhhun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+
+cv.mulhhun t0, t1, zero, 16
+# CHECK-INSTR: cv.mulhhun t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhun t0, t1, zero, 31
+# CHECK-INSTR: cv.mulhhun t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhurn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulhhurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhurn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulhhurn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x52,0x03,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulhhurn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulhhurn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x52,0x03,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.muls t0, t1, t2
+# CHECK-INSTR: cv.mulsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.muls t0, t1, zero
+# CHECK-INSTR: cv.mulsn t0, t1, zero, 0
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulsn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulsn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulsn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x42,0x03,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsrn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulsrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x42,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsrn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulsrn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x42,0x03,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulsrn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulsrn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x42,0x03,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulu t0, t1, t2
+# CHECK-INSTR: cv.mulun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulu t0, t1, zero
+# CHECK-INSTR: cv.mulun t0, t1, zero, 0
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulun t0, t1, t2, 0
+# CHECK-INSTR: cv.mulun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulun t0, t1, zero, 16
+# CHECK-INSTR: cv.mulun t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulun t0, t1, zero, 31
+# CHECK-INSTR: cv.mulun t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x52,0x03,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulurn t0, t1, t2, 0
+# CHECK-INSTR: cv.mulurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x52,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulurn t0, t1, zero, 16
+# CHECK-INSTR: cv.mulurn t0, t1, zero, 16
+# CHECK-ENCODING: [0xdb,0x52,0x03,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}
+
+cv.mulurn t0, t1, zero, 31
+# CHECK-INSTR: cv.mulurn t0, t1, zero, 31
+# CHECK-ENCODING: [0xdb,0x52,0x03,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmac' (Multiply-Accumulate){{$}}