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[RISCV] Add RISCVISD nodes for vfwadd/vfwsub.
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Authored by craig.topper on Jun 1 2023, 10:26 PM.

Details

Summary

Add a DAG combine to form these from FADD_VL/FSUB_VL and FP_EXTEND_VL.

This makes it similar to other widening ops and allows us to handle
using the same FP_EXTEND_VL for both operands.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 1 2023, 10:26 PM
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craig.topper requested review of this revision.Jun 1 2023, 10:26 PM
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reames accepted this revision.Jun 5 2023, 9:34 AM

LGTM w/minor comment.

Note, I'm mostly trusting you have the tablegen bits right. My review is really only meaningful for the C++ bits.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
417

Could you precommit the naming change so that this drops out of the diff?

This revision is now accepted and ready to land.Jun 5 2023, 9:34 AM
This revision was landed with ongoing or failed builds.Jun 5 2023, 2:15 PM
This revision was automatically updated to reflect the committed changes.
rogfer01 added inline comments.Jun 8 2023, 2:19 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1403

I think we may need a VPatBinaryVL_V here (similar to the one in PseudoVWADD for integers).

I'm seeing a crash in our downstream while building the llvm-testsuite in column 11 of https://github.com/llvm/llvm-test-suite/blob/main/MultiSource/Benchmarks/McCat/18-imp/L_canny.c#L238

fatal error: error in backend: Cannot select: t329: nxv2f64 = RISCVISD::VFWADD_W_VL t363, t313, undef:nxv2f64, t319, t11

The compiler is computing y + EPS but y is a nxv2f32 and EPS is a double that has been splatted into nxv2f64 (and we have a mask around due to the control flow) so the compiler chooses VFWADD_W_VL here (I understand the vfwadd.wf version expects a f32 as the scalar operand so it can't be selected) where the first operand is the splatted EPS and the second one is y.

craig.topper added inline comments.Jun 8 2023, 8:32 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1403