[RISCV] Set Fast flag for unaligned memory accesses

[luke]

Summary

The +unaligned-scalar-mem and +unaligned-vector-mem features were added in
D126085 and D149375 respectively to allow subtargets to indicate that
they supported misaligned loads/stores with "sufficient" performance.
This is separate from whether or not the target actually supports
misaligned accesses, which could be determined from Zicclsm.

This patch enables the Fast flag under the assumption that any subtarget
that declares support for +unaligned-*-mem will want to opt into
optimisations that take advantage of misaligned scalar accesses, such as
store merging.

[luke]

Returning for revision as this affects codegen in benchmarks quite significantly and I would like to evaluate the changes first

[reames]

Reverse ping.

I spent some time looking at this over the last few days, and I think this makes sense to get landed. I do want to request that you also enabled the Fast flag for the vector analogy flag. From what I can tell, it causes no additional test diff, but doing them together is likely safer for two reasons. First, it corresponds to the tested downstream config. Second, a number of the merge transforms are in terms of comparisons of "how fast" operations are. Thus having one set and not the other can result in odd results.

[craig.topper]

In D150771#4520282, @reames wrote:

Reverse ping.

I spent some time looking at this over the last few days, and I think this makes sense to get landed. I do want to request that you also enabled the Fast flag for the vector analogy flag. From what I can tell, it causes no additional test diff, but doing them together is likely safer for two reasons. First, it corresponds to the tested downstream config. Second, a number of the merge transforms are in terms of comparisons of "how fast" operations are. Thus having one set and not the other can result in odd results.

If I remember right setting fast for vector has some effect on memcpy and memset expansion.

[reames]

In D150771#4520362, @craig.topper wrote:

In D150771#4520282, @reames wrote:

Reverse ping.

I spent some time looking at this over the last few days, and I think this makes sense to get landed. I do want to request that you also enabled the Fast flag for the vector analogy flag. From what I can tell, it causes no additional test diff, but doing them together is likely safer for two reasons. First, it corresponds to the tested downstream config. Second, a number of the merge transforms are in terms of comparisons of "how fast" operations are. Thus having one set and not the other can result in odd results.

If I remember right setting fast for vector has some effect on memcpy and memset expansion.

It does, but it's currently pretty indirect. Our maximum size uses for memset/memcpy lowering is currently i64. The store merging code then kicks in to form broader loads and stores. As a result, the impact on mem* lowering is the impact on store merging and load combining. This change does enable merging for unaligned cases, and thus does impact the mem* lowering.

See test/CodeGen/RISCV/rvv/memset-inline.ll (once this patch is rebased)

[luke]

Rebase and enable fast flag for vector accesses too

[reames]

LGTM

p.s. I have a patch to implement getOptimalMemOpType which I'm drafting, and will post once this lands.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::isMulAddWithConstProfitable(SDValue AddNode,
   return true;
 }
 
 bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
     EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
     unsigned *Fast) const {
   if (!VT.isVector()) {
     if (Fast)
-      *Fast = 0;
+      *Fast = Subtarget.enableUnalignedScalarMem();
     return Subtarget.enableUnalignedScalarMem();
   }
 
   // All vector implementations must support element alignment
   EVT ElemVT = VT.getVectorElementType();
   if (Alignment >= ElemVT.getStoreSize()) {
     if (Fast)
       *Fast = 1;

llvm/test/CodeGen/RISCV/memcpy-inline.ll

 @.str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1
 @.str3 = private unnamed_addr constant [24 x i8] c"DHRYSTONE PROGRAM, SOME\00", align 1
 @.str4 = private unnamed_addr constant [18 x i8] c"DHRYSTONE PROGR  \00", align 1
 @.str5 = private unnamed_addr constant [7 x i8] c"DHRYST\00", align 1
 @.str6 = private unnamed_addr constant [14 x i8] c"/tmp/rmXXXXXX\00", align 1
 @spool.splbuf = internal global [512 x i8] zeroinitializer, align 16
 
 define i32 @t0() {
-; RV32-LABEL: t0:
-; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    lui a0, %hi(src)
-; RV32-NEXT:    lw a1, %lo(src)(a0)
-; RV32-NEXT:    lui a2, %hi(dst)
-; RV32-NEXT:    sw a1, %lo(dst)(a2)
-; RV32-NEXT:    addi a0, a0, %lo(src)
-; RV32-NEXT:    lbu a1, 10(a0)
-; RV32-NEXT:    lh a3, 8(a0)
-; RV32-NEXT:    lw a0, 4(a0)
-; RV32-NEXT:    addi a2, a2, %lo(dst)
-; RV32-NEXT:    sb a1, 10(a2)
-; RV32-NEXT:    sh a3, 8(a2)
-; RV32-NEXT:    sw a0, 4(a2)
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    ret
+; RV32ALIGNED-LABEL: t0:
+; RV32ALIGNED:       # %bb.0: # %entry
+; RV32ALIGNED-NEXT:    lui a0, %hi(src)
+; RV32ALIGNED-NEXT:    lw a1, %lo(src)(a0)
+; RV32ALIGNED-NEXT:    lui a2, %hi(dst)
+; RV32ALIGNED-NEXT:    sw a1, %lo(dst)(a2)
+; RV32ALIGNED-NEXT:    addi a0, a0, %lo(src)
+; RV32ALIGNED-NEXT:    lbu a1, 10(a0)
+; RV32ALIGNED-NEXT:    lh a3, 8(a0)
+; RV32ALIGNED-NEXT:    lw a0, 4(a0)
+; RV32ALIGNED-NEXT:    addi a2, a2, %lo(dst)
+; RV32ALIGNED-NEXT:    sb a1, 10(a2)
+; RV32ALIGNED-NEXT:    sh a3, 8(a2)
+; RV32ALIGNED-NEXT:    sw a0, 4(a2)
+; RV32ALIGNED-NEXT:    li a0, 0
+; RV32ALIGNED-NEXT:    ret
 ;
-; RV64-LABEL: t0:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    lui a0, %hi(src)
-; RV64-NEXT:    ld a1, %lo(src)(a0)
-; RV64-NEXT:    lui a2, %hi(dst)
-; RV64-NEXT:    addi a0, a0, %lo(src)
-; RV64-NEXT:    lbu a3, 10(a0)
-; RV64-NEXT:    lh a0, 8(a0)
-; RV64-NEXT:    sd a1, %lo(dst)(a2)
-; RV64-NEXT:    addi a1, a2, %lo(dst)
-; RV64-NEXT:    sb a3, 10(a1)
-; RV64-NEXT:    sh a0, 8(a1)
-; RV64-NEXT:    li a0, 0
-; RV64-NEXT:    ret
+; RV64ALIGNED-LABEL: t0:
+; RV64ALIGNED:       # %bb.0: # %entry
+; RV64ALIGNED-NEXT:    lui a0, %hi(src)
+; RV64ALIGNED-NEXT:    ld a1, %lo(src)(a0)
+; RV64ALIGNED-NEXT:    lui a2, %hi(dst)
+; RV64ALIGNED-NEXT:    addi a0, a0, %lo(src)
+; RV64ALIGNED-NEXT:    lbu a3, 10(a0)
+; RV64ALIGNED-NEXT:    lh a0, 8(a0)
+; RV64ALIGNED-NEXT:    sd a1, %lo(dst)(a2)
+; RV64ALIGNED-NEXT:    addi a1, a2, %lo(dst)
+; RV64ALIGNED-NEXT:    sb a3, 10(a1)
+; RV64ALIGNED-NEXT:    sh a0, 8(a1)
+; RV64ALIGNED-NEXT:    li a0, 0
+; RV64ALIGNED-NEXT:    ret
+;
+; RV32UNALIGNED-LABEL: t0:
+; RV32UNALIGNED:       # %bb.0: # %entry
+; RV32UNALIGNED-NEXT:    lui a0, %hi(src)
+; RV32UNALIGNED-NEXT:    lw a1, %lo(src)(a0)
+; RV32UNALIGNED-NEXT:    lui a2, %hi(dst)
+; RV32UNALIGNED-NEXT:    addi a0, a0, %lo(src)
+; RV32UNALIGNED-NEXT:    lw a3, 7(a0)
+; RV32UNALIGNED-NEXT:    lw a0, 4(a0)
+; RV32UNALIGNED-NEXT:    sw a1, %lo(dst)(a2)
+; RV32UNALIGNED-NEXT:    addi a1, a2, %lo(dst)
+; RV32UNALIGNED-NEXT:    sw a3, 7(a1)
+; RV32UNALIGNED-NEXT:    sw a0, 4(a1)
+; RV32UNALIGNED-NEXT:    li a0, 0
+; RV32UNALIGNED-NEXT:    ret
+;
+; RV64UNALIGNED-LABEL: t0:
+; RV64UNALIGNED:       # %bb.0: # %entry
+; RV64UNALIGNED-NEXT:    lui a0, %hi(src)
+; RV64UNALIGNED-NEXT:    ld a1, %lo(src)(a0)
+; RV64UNALIGNED-NEXT:    addi a0, a0, %lo(src)
+; RV64UNALIGNED-NEXT:    lw a0, 7(a0)
+; RV64UNALIGNED-NEXT:    lui a2, %hi(dst)
+; RV64UNALIGNED-NEXT:    sd a1, %lo(dst)(a2)
+; RV64UNALIGNED-NEXT:    addi a1, a2, %lo(dst)
+; RV64UNALIGNED-NEXT:    sw a0, 7(a1)
+; RV64UNALIGNED-NEXT:    li a0, 0
+; RV64UNALIGNED-NEXT:    ret
 entry:
   call void @llvm.memcpy.p0.p0.i32(ptr align 8 @dst, ptr align 8 @src, i32 11, i1 false)
   ret i32 0
 }
 
 define void @t1(ptr nocapture %C) nounwind {
-; RV32-LABEL: t1:
-; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    lui a1, %hi(.L.str1)
-; RV32-NEXT:    addi a1, a1, %lo(.L.str1)
-; RV32-NEXT:    li a2, 31
-; RV32-NEXT:    tail memcpy@plt
+; RV32ALIGNED-LABEL: t1:
+; RV32ALIGNED:       # %bb.0: # %entry
+; RV32ALIGNED-NEXT:    lui a1, %hi(.L.str1)
+; RV32ALIGNED-NEXT:    addi a1, a1, %lo(.L.str1)
+; RV32ALIGNED-NEXT:    li a2, 31
+; RV32ALIGNED-NEXT:    tail memcpy@plt
 ;
 ; RV64ALIGNED-LABEL: t1:
 ; RV64ALIGNED:       # %bb.0: # %entry
 ; RV64ALIGNED-NEXT:    lui a1, %hi(.L.str1)
 ; RV64ALIGNED-NEXT:    addi a1, a1, %lo(.L.str1)
 ; RV64ALIGNED-NEXT:    li a2, 31
 ; RV64ALIGNED-NEXT:    tail memcpy@plt
 ;
+; RV32UNALIGNED-LABEL: t1:
+; RV32UNALIGNED:       # %bb.0: # %entry
+; RV32UNALIGNED-NEXT:    lui a1, 1141
+; RV32UNALIGNED-NEXT:    addi a1, a1, -439
+; RV32UNALIGNED-NEXT:    sw a1, 27(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 300325
+; RV32UNALIGNED-NEXT:    addi a1, a1, 1107
+; RV32UNALIGNED-NEXT:    sw a1, 24(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 132181
+; RV32UNALIGNED-NEXT:    addi a1, a1, -689
+; RV32UNALIGNED-NEXT:    sw a1, 20(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 340483
+; RV32UNALIGNED-NEXT:    addi a1, a1, -947
+; RV32UNALIGNED-NEXT:    sw a1, 16(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 267556
+; RV32UNALIGNED-NEXT:    addi a1, a1, 1871
+; RV32UNALIGNED-NEXT:    sw a1, 12(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 337154
+; RV32UNALIGNED-NEXT:    addi a1, a1, 69
+; RV32UNALIGNED-NEXT:    sw a1, 8(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 320757
+; RV32UNALIGNED-NEXT:    addi a1, a1, 1107
+; RV32UNALIGNED-NEXT:    sw a1, 4(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 365861
+; RV32UNALIGNED-NEXT:    addi a1, a1, -1980
+; RV32UNALIGNED-NEXT:    sw a1, 0(a0)
+; RV32UNALIGNED-NEXT:    ret
+;
 ; RV64UNALIGNED-LABEL: t1:
 ; RV64UNALIGNED:       # %bb.0: # %entry
 ; RV64UNALIGNED-NEXT:    lui a1, %hi(.L.str1)
 ; RV64UNALIGNED-NEXT:    ld a2, %lo(.L.str1)(a1)
-; RV64UNALIGNED-NEXT:    sd a2, 0(a0)
-; RV64UNALIGNED-NEXT:    lui a2, 4
-; RV64UNALIGNED-NEXT:    addiw a2, a2, 1870
-; RV64UNALIGNED-NEXT:    sh a2, 28(a0)
-; RV64UNALIGNED-NEXT:    lui a2, 300325
-; RV64UNALIGNED-NEXT:    addiw a2, a2, 1107
 ; RV64UNALIGNED-NEXT:    addi a1, a1, %lo(.L.str1)
-; RV64UNALIGNED-NEXT:    ld a3, 16(a1)
+; RV64UNALIGNED-NEXT:    ld a3, 23(a1)
+; RV64UNALIGNED-NEXT:    ld a4, 16(a1)
 ; RV64UNALIGNED-NEXT:    ld a1, 8(a1)
-; RV64UNALIGNED-NEXT:    sw a2, 24(a0)
-; RV64UNALIGNED-NEXT:    sb zero, 30(a0)
-; RV64UNALIGNED-NEXT:    sd a3, 16(a0)
+; RV64UNALIGNED-NEXT:    sd a2, 0(a0)
+; RV64UNALIGNED-NEXT:    sd a3, 23(a0)
+; RV64UNALIGNED-NEXT:    sd a4, 16(a0)
 ; RV64UNALIGNED-NEXT:    sd a1, 8(a0)
 ; RV64UNALIGNED-NEXT:    ret
 entry:
   tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str1, i64 31, i1 false)
   ret void
 }
 
 define void @t2(ptr nocapture %C) nounwind {

 ; RV64ALIGNED-NEXT:    li a1, 72
 ; RV64ALIGNED-NEXT:    sb a1, 1(a0)
 ; RV64ALIGNED-NEXT:    li a1, 68
 ; RV64ALIGNED-NEXT:    sb a1, 0(a0)
 ; RV64ALIGNED-NEXT:    ret
 ;
 ; RV32UNALIGNED-LABEL: t5:
 ; RV32UNALIGNED:       # %bb.0: # %entry
-; RV32UNALIGNED-NEXT:    sb zero, 6(a0)
-; RV32UNALIGNED-NEXT:    lui a1, 5
-; RV32UNALIGNED-NEXT:    addi a1, a1, 1107
-; RV32UNALIGNED-NEXT:    sh a1, 4(a0)
+; RV32UNALIGNED-NEXT:    lui a1, 1349
+; RV32UNALIGNED-NEXT:    addi a1, a1, 857
+; RV32UNALIGNED-NEXT:    sw a1, 3(a0)
 ; RV32UNALIGNED-NEXT:    lui a1, 365861
 ; RV32UNALIGNED-NEXT:    addi a1, a1, -1980
 ; RV32UNALIGNED-NEXT:    sw a1, 0(a0)
 ; RV32UNALIGNED-NEXT:    ret
 ;
 ; RV64UNALIGNED-LABEL: t5:
 ; RV64UNALIGNED:       # %bb.0: # %entry
-; RV64UNALIGNED-NEXT:    sb zero, 6(a0)
-; RV64UNALIGNED-NEXT:    lui a1, 5
-; RV64UNALIGNED-NEXT:    addiw a1, a1, 1107
-; RV64UNALIGNED-NEXT:    sh a1, 4(a0)
+; RV64UNALIGNED-NEXT:    lui a1, 1349
+; RV64UNALIGNED-NEXT:    addiw a1, a1, 857
+; RV64UNALIGNED-NEXT:    sw a1, 3(a0)
 ; RV64UNALIGNED-NEXT:    lui a1, 365861
 ; RV64UNALIGNED-NEXT:    addiw a1, a1, -1980
 ; RV64UNALIGNED-NEXT:    sw a1, 0(a0)
 ; RV64UNALIGNED-NEXT:    ret
 entry:
   tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str5, i64 7, i1 false)
   ret void
 }

 ; RV32UNALIGNED-NEXT:    lui a1, 460503
 ; RV32UNALIGNED-NEXT:    addi a1, a1, 1071
 ; RV32UNALIGNED-NEXT:    sw a1, %lo(spool.splbuf)(a0)
 ; RV32UNALIGNED-NEXT:    ret
 ;
 ; RV64UNALIGNED-LABEL: t6:
 ; RV64UNALIGNED:       # %bb.0: # %entry
 ; RV64UNALIGNED-NEXT:    lui a0, %hi(.L.str6)
-; RV64UNALIGNED-NEXT:    ld a0, %lo(.L.str6)(a0)
-; RV64UNALIGNED-NEXT:    lui a1, %hi(spool.splbuf)
-; RV64UNALIGNED-NEXT:    li a2, 88
-; RV64UNALIGNED-NEXT:    sh a2, %lo(spool.splbuf+12)(a1)
-; RV64UNALIGNED-NEXT:    sd a0, %lo(spool.splbuf)(a1)
-; RV64UNALIGNED-NEXT:    lui a0, 361862
-; RV64UNALIGNED-NEXT:    addiw a0, a0, -1960
-; RV64UNALIGNED-NEXT:    sw a0, %lo(spool.splbuf+8)(a1)
+; RV64UNALIGNED-NEXT:    ld a1, %lo(.L.str6)(a0)
+; RV64UNALIGNED-NEXT:    addi a0, a0, %lo(.L.str6)
+; RV64UNALIGNED-NEXT:    ld a0, 6(a0)
+; RV64UNALIGNED-NEXT:    lui a2, %hi(spool.splbuf)
+; RV64UNALIGNED-NEXT:    sd a1, %lo(spool.splbuf)(a2)
+; RV64UNALIGNED-NEXT:    sd a0, %lo(spool.splbuf+6)(a2)
 ; RV64UNALIGNED-NEXT:    ret
 entry:
   call void @llvm.memcpy.p0.p0.i64(ptr @spool.splbuf, ptr @.str6, i64 14, i1 false)
   ret void
 }
 
 %struct.Foo = type { i32, i32, i32, i32 }
 

 ; RV64UNALIGNED-NEXT:    ret
 entry:
   tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %a, ptr align 4 %b, i32 16, i1 false)
   ret void
 }
 
 declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
 declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV64: {{.*}}

llvm/test/CodeGen/RISCV/unaligned-load-store.ll

 ; MISALIGN-RV64I:       # %bb.0:
 ; MISALIGN-RV64I-NEXT:    sd a1, 0(a0)
 ; MISALIGN-RV64I-NEXT:    ret
   store i64 %v, ptr %p, align 1
   ret void
 }
 
 define void @merge_stores_i8_i16(ptr %p) {
-; ALL-LABEL: merge_stores_i8_i16:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sb zero, 0(a0)
-; ALL-NEXT:    sb zero, 1(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i8_i16:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sb zero, 0(a0)
+; NOMISALIGN-NEXT:    sb zero, 1(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-LABEL: merge_stores_i8_i16:
+; MISALIGN:       # %bb.0:
+; MISALIGN-NEXT:    sh zero, 0(a0)
+; MISALIGN-NEXT:    ret
   store i8 0, ptr %p
   %p2 = getelementptr i8, ptr %p, i32 1
   store i8 0, ptr %p2
   ret void
 }
 
 define void @merge_stores_i8_i32(ptr %p) {
-; ALL-LABEL: merge_stores_i8_i32:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sb zero, 0(a0)
-; ALL-NEXT:    sb zero, 1(a0)
-; ALL-NEXT:    sb zero, 2(a0)
-; ALL-NEXT:    sb zero, 3(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i8_i32:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sb zero, 0(a0)
+; NOMISALIGN-NEXT:    sb zero, 1(a0)
+; NOMISALIGN-NEXT:    sb zero, 2(a0)
+; NOMISALIGN-NEXT:    sb zero, 3(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-LABEL: merge_stores_i8_i32:
+; MISALIGN:       # %bb.0:
+; MISALIGN-NEXT:    sw zero, 0(a0)
+; MISALIGN-NEXT:    ret
   store i8 0, ptr %p
   %p2 = getelementptr i8, ptr %p, i32 1
   store i8 0, ptr %p2
   %p3 = getelementptr i8, ptr %p, i32 2
   store i8 0, ptr %p3
   %p4 = getelementptr i8, ptr %p, i32 3
   store i8 0, ptr %p4
   ret void
 }
 
 define void @merge_stores_i8_i64(ptr %p) {
-; ALL-LABEL: merge_stores_i8_i64:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sb zero, 0(a0)
-; ALL-NEXT:    sb zero, 1(a0)
-; ALL-NEXT:    sb zero, 2(a0)
-; ALL-NEXT:    sb zero, 3(a0)
-; ALL-NEXT:    sb zero, 4(a0)
-; ALL-NEXT:    sb zero, 5(a0)
-; ALL-NEXT:    sb zero, 6(a0)
-; ALL-NEXT:    sb zero, 7(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i8_i64:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sb zero, 0(a0)
+; NOMISALIGN-NEXT:    sb zero, 1(a0)
+; NOMISALIGN-NEXT:    sb zero, 2(a0)
+; NOMISALIGN-NEXT:    sb zero, 3(a0)
+; NOMISALIGN-NEXT:    sb zero, 4(a0)
+; NOMISALIGN-NEXT:    sb zero, 5(a0)
+; NOMISALIGN-NEXT:    sb zero, 6(a0)
+; NOMISALIGN-NEXT:    sb zero, 7(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-RV32I-LABEL: merge_stores_i8_i64:
+; MISALIGN-RV32I:       # %bb.0:
+; MISALIGN-RV32I-NEXT:    sw zero, 0(a0)
+; MISALIGN-RV32I-NEXT:    sw zero, 4(a0)
+; MISALIGN-RV32I-NEXT:    ret
+;
+; MISALIGN-RV64I-LABEL: merge_stores_i8_i64:
+; MISALIGN-RV64I:       # %bb.0:
+; MISALIGN-RV64I-NEXT:    sd zero, 0(a0)
+; MISALIGN-RV64I-NEXT:    ret
   store i8 0, ptr %p
   %p2 = getelementptr i8, ptr %p, i32 1
   store i8 0, ptr %p2
   %p3 = getelementptr i8, ptr %p, i32 2
   store i8 0, ptr %p3
   %p4 = getelementptr i8, ptr %p, i32 3
   store i8 0, ptr %p4
   %p5 = getelementptr i8, ptr %p, i32 4
   store i8 0, ptr %p5
   %p6 = getelementptr i8, ptr %p, i32 5
   store i8 0, ptr %p6
   %p7 = getelementptr i8, ptr %p, i32 6
   store i8 0, ptr %p7
   %p8 = getelementptr i8, ptr %p, i32 7
   store i8 0, ptr %p8
   ret void
 }
 
 define void @merge_stores_i16_i32(ptr %p) {
-; ALL-LABEL: merge_stores_i16_i32:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sh zero, 0(a0)
-; ALL-NEXT:    sh zero, 2(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i16_i32:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sh zero, 0(a0)
+; NOMISALIGN-NEXT:    sh zero, 2(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-LABEL: merge_stores_i16_i32:
+; MISALIGN:       # %bb.0:
+; MISALIGN-NEXT:    sw zero, 0(a0)
+; MISALIGN-NEXT:    ret
   store i16 0, ptr %p
   %p2 = getelementptr i16, ptr %p, i32 1
   store i16 0, ptr %p2
   ret void
 }
 
 define void @merge_stores_i16_i64(ptr %p) {
-; ALL-LABEL: merge_stores_i16_i64:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sh zero, 0(a0)
-; ALL-NEXT:    sh zero, 2(a0)
-; ALL-NEXT:    sh zero, 4(a0)
-; ALL-NEXT:    sh zero, 6(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i16_i64:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sh zero, 0(a0)
+; NOMISALIGN-NEXT:    sh zero, 2(a0)
+; NOMISALIGN-NEXT:    sh zero, 4(a0)
+; NOMISALIGN-NEXT:    sh zero, 6(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-RV32I-LABEL: merge_stores_i16_i64:
+; MISALIGN-RV32I:       # %bb.0:
+; MISALIGN-RV32I-NEXT:    sw zero, 0(a0)
+; MISALIGN-RV32I-NEXT:    sw zero, 4(a0)
+; MISALIGN-RV32I-NEXT:    ret
+;
+; MISALIGN-RV64I-LABEL: merge_stores_i16_i64:
+; MISALIGN-RV64I:       # %bb.0:
+; MISALIGN-RV64I-NEXT:    sd zero, 0(a0)
+; MISALIGN-RV64I-NEXT:    ret
   store i16 0, ptr %p
   %p2 = getelementptr i16, ptr %p, i32 1
   store i16 0, ptr %p2
   %p3 = getelementptr i16, ptr %p, i32 2
   store i16 0, ptr %p3
   %p4 = getelementptr i16, ptr %p, i32 3
   store i16 0, ptr %p4
   ret void
 }
 
 define void @merge_stores_i32_i64(ptr %p) {
-; ALL-LABEL: merge_stores_i32_i64:
-; ALL:       # %bb.0:
-; ALL-NEXT:    sw zero, 0(a0)
-; ALL-NEXT:    sw zero, 4(a0)
-; ALL-NEXT:    ret
+; NOMISALIGN-LABEL: merge_stores_i32_i64:
+; NOMISALIGN:       # %bb.0:
+; NOMISALIGN-NEXT:    sw zero, 0(a0)
+; NOMISALIGN-NEXT:    sw zero, 4(a0)
+; NOMISALIGN-NEXT:    ret
+;
+; MISALIGN-RV32I-LABEL: merge_stores_i32_i64:
+; MISALIGN-RV32I:       # %bb.0:
+; MISALIGN-RV32I-NEXT:    sw zero, 0(a0)
+; MISALIGN-RV32I-NEXT:    sw zero, 4(a0)
+; MISALIGN-RV32I-NEXT:    ret
+;
+; MISALIGN-RV64I-LABEL: merge_stores_i32_i64:
+; MISALIGN-RV64I:       # %bb.0:
+; MISALIGN-RV64I-NEXT:    sd zero, 0(a0)
+; MISALIGN-RV64I-NEXT:    ret
   store i32 0, ptr %p
   %p2 = getelementptr i32, ptr %p, i32 1
   store i32 0, ptr %p2
   ret void
 }