[RISCV] Pass vector argument by stack correctly.

[kito-cheng]

Summary

We've a argument lowering logic to prevent floating-point value pass
passed with bit-conversion, but that rule should not applied to vector
arguments.

---

How to pass argument to foo:

tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                    <vscale x 16 x float> zeroinitializer,
                    <vscale x 16 x float> zeroinitializer,
                    <vscale x 16 x float> zeroinitializer)

foo take 13 arguments, first 8 argument pass in GPR, and next 2 LMUL 8 vector
arguments passed in v8-v23, and now we run out of argument register for GPR and
vector register, so we must pass last LMUL 8 vector argument by stack.

Which means we should reserve vlenb * 8 byte for stack for the last
vector argument.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

12797–12800

I wonder if this should be LocInfo == CCValAssign::BCvt or LocInfo != CCValAssign::Indirect? Seems like an assumption is being made about the LocInfo here more than the type.

[kito-cheng]

Changes:

• Check LocInfo rather than check ValVT.
• Also add an assertion to make sure no vector type got into wrong path.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
           (TLI.getSubtarget().hasVInstructions() && ValVT.isVector())) &&
          "Expected an XLenVT or vector types at this stage");
 
   if (Reg) {
     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     return false;
   }
 
-  // When a floating-point value is passed on the stack, no bit-conversion is
-  // needed.
-  if (ValVT.isFloatingPoint()) {
+  // When a scalar floating-point value is passed on the stack, no
+  // bit-conversion is needed.
+  if (ValVT.isFloatingPoint() && LocInfo != CCValAssign::Indirect) {
+    assert(!ValVT.isVector());
     LocVT = ValVT;
     LocInfo = CCValAssign::Full;
   }
   State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
   return false;
 }
 
 template <typename ArgTy>

llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -treat-scalable-fixed-error-as-warning < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s 2>&1 | FileCheck %s
 
-; CHECK: warning: Invalid size request on a scalable vector
+; CHECK-NOT: warning: Invalid size request on a scalable vector
 
 define void @bar() nounwind {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    sd ra, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    addi s0, sp, 96
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    sub sp, sp, a0
+; CHECK-NEXT:    andi sp, sp, -64
+; CHECK-NEXT:    mv s1, sp
 ; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vs8r.v v8, (sp)
+; CHECK-NEXT:    addi a0, s1, 64
+; CHECK-NEXT:    vs8r.v v8, (a0)
+; CHECK-NEXT:    sd a0, 0(sp)
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    li a2, 0
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    li a4, 0
 ; CHECK-NEXT:    li a5, 0
 ; CHECK-NEXT:    li a6, 0
 ; CHECK-NEXT:    li a7, 0
 ; CHECK-NEXT:    vmv.v.i v16, 0
 ; CHECK-NEXT:    call foo@plt
-; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    addi sp, s0, -96
+; CHECK-NEXT:    ld ra, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 96
 ; CHECK-NEXT:    ret
 entry:
   tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer)
   ret void
 }
 
 declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, <vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) nounwind