[RISCV] Support Zfa fli instructions with vector splats.

[craig.topper]

Summary

-Support fli.h with Zvfh+Zfhmin.
-Return false from RISCVDAGToDAGISel::selectFPImm

[craig.topper]

Reduce code duplication

[reames]

LGTM w/optional comment

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1544

Style: This really should be a switch on VT with a return in each block.

1550

Hm, shouldn't this depend on having the D extension? (follow on)

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1544

Good point. It worked less well as a switch before I made it its own function.

1550

I'll add an assert. the caller in this file already checks D is enabled. The two calls in RISCVISelDAGToDAG.cpp only occur if f64 is a legal type which would require D if Zfa is enabled. Zfa is incompatible with Zdinx.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1550

Ack

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
     ReplaceNode(Node, selectImm(CurDAG, DL, VT, Imm, *Subtarget).getNode());
     return;
   }
   case ISD::ConstantFP: {
     const APFloat &APF = cast<ConstantFPSDNode>(Node)->getValueAPF();
     if (Subtarget->hasStdExtZfa()) {
-      // fli.h requires Zfh, but we might only have Zfhmin.
-      if (VT == MVT::f16 && Subtarget->hasStdExtZfh() &&
+      // fli.h requires Zfh or Zvfh, but we might only have Zfhmin.
+      if (VT == MVT::f16 &&
+          (Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()) &&
           RISCVLoadFPImm::getLoadFP16Imm(APF) != -1)
         break;
       if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1)
         break;
       if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(APF) != -1)
         break;
     }
 

 bool RISCVDAGToDAGISel::selectFPImm(SDValue N, SDValue &Imm) {
   ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N.getNode());
   if (!CFP)
     return false;
   const APFloat &APF = CFP->getValueAPF();
   // td can handle +0.0 already.
   if (APF.isPosZero())
     return false;
+
+  MVT VT = CFP->getSimpleValueType(0);
+
+  if (Subtarget->hasStdExtZfa()) {
+    // fli.h requires Zfh or Zvfh, but we might only have Zfhmin.
+    if (VT == MVT::f16 &&
+        (Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()) &&
+        RISCVLoadFPImm::getLoadFP16Imm(APF) != -1)
+      return false;
+    if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1)
+      return false;
+    if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(APF) != -1)
+      return false;
+  }
+
   MVT XLenVT = Subtarget->getXLenVT();
-  if (CFP->getValueType(0) == MVT::f64 && !Subtarget->is64Bit()) {
+  if (VT == MVT::f64 && !Subtarget->is64Bit()) {
     assert(APF.isNegZero() && "Unexpected constant.");
     return false;
   }
   SDLoc DL(N);
   Imm = selectImm(CurDAG, DL, XLenVT, APF.bitcastToAPInt().getSExtValue(),
                   *Subtarget);
   return true;
 }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool RISCVTargetLowering::isOffsetFoldingLegal(
   // it in the global address node. Later peephole optimisations may choose to
   // fold it back in when profitable.
   return false;
 }
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   if (VT == MVT::f16 && !Subtarget.hasStdExtZfhOrZfhmin())
     return false;
   if (VT == MVT::f32 && !Subtarget.hasStdExtF())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())
     return false;
 
   if (Subtarget.hasStdExtZfa()) {
-    // fli.h requires Zfh, but we might only have Zfhmin.
-    if (VT == MVT::f16 && Subtarget.hasStdExtZfh() &&
+    // fli.h requires Zfh or Zvfh, but we might only have Zfhmin.
+    if (VT == MVT::f16 &&
+        (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh()) &&
         RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1)
       return true;
     if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1)
       return true;
     if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1)
       return true;
   }
 

llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+experimental-zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+experimental-zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 8 x half> @vsplat_f16_0p625() {
+; CHECK-LABEL: vsplat_f16_0p625:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.h ft0, 6.250000e-01
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> poison, half 0.625, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x half> %splat
+}
+
+define <vscale x 8 x float> @vsplat_f32_0p75() {
+; CHECK-LABEL: vsplat_f32_0p75:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.s ft0, 7.500000e-01
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> poison, float 0.75, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x float> %splat
+}
+
+define <vscale x 8 x double> @vsplat_f64_neg1() {
+; CHECK-LABEL: vsplat_f64_neg1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.d ft0, -1.000000e+00
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x double> poison, double -1.0, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x double> %splat
+}