[RISCV] Support Zfa fli instructions with vector splats.

[craig.topper]

Summary

-Support fli.h with Zvfh+Zfhmin.
-Return false from RISCVDAGToDAGISel::selectFPImm

[craig.topper]

Reduce code duplication

[reames]

LGTM w/optional comment

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1544

Style: This really should be a switch on VT with a return in each block.

1550

Hm, shouldn't this depend on having the D extension? (follow on)

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1544

Good point. It worked less well as a switch before I made it its own function.

1550

I'll add an assert. the caller in this file already checks D is enabled. The two calls in RISCVISelDAGToDAG.cpp only occur if f64 is a legal type which would require D if Zfa is enabled. Zfa is incompatible with Zdinx.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1550

Ack

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

case ISD::Constant: {
     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
     ReplaceNode(Node, selectImm(CurDAG, DL, VT, Imm, *Subtarget).getNode());
     return;
   }
   case ISD::ConstantFP: {
     const APFloat &APF = cast<ConstantFPSDNode>(Node)->getValueAPF();
-    if (Subtarget->hasStdExtZfa()) {
-      // fli.h requires Zfh, but we might only have Zfhmin.
-      if (VT == MVT::f16 && Subtarget->hasStdExtZfh() &&
-          RISCVLoadFPImm::getLoadFP16Imm(APF) != -1)
-        break;
-      if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1)
-        break;
-      if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(APF) != -1)
-        break;
-    }
+    if (static_cast<const RISCVTargetLowering *>(TLI)->isLegalZfaFPImm(APF, VT))
 
     bool NegZeroF64 = APF.isNegZero() && VT == MVT::f64;
     SDValue Imm;
     // For +0.0 or f64 -0.0 we need to start from X0. For all others, we will
     // create an integer immediate.
     if (APF.isPosZero() || NegZeroF64)
       Imm = CurDAG->getRegister(RISCV::X0, XLenVT);
     else

 bool RISCVDAGToDAGISel::selectFPImm(SDValue N, SDValue &Imm) {
   ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N.getNode());
   if (!CFP)
     return false;
   const APFloat &APF = CFP->getValueAPF();
   // td can handle +0.0 already.
   if (APF.isPosZero())
     return false;
+
+  MVT VT = CFP->getSimpleValueType(0);
+
+  if (static_cast<const RISCVTargetLowering *>(TLI)->isLegalZfaFPImm(APF, VT))
+    return false;
+
   MVT XLenVT = Subtarget->getXLenVT();
-  if (CFP->getValueType(0) == MVT::f64 && !Subtarget->is64Bit()) {
+  if (VT == MVT::f64 && !Subtarget->is64Bit()) {
     assert(APF.isNegZero() && "Unexpected constant.");
     return false;
   }
   SDLoc DL(N);
   Imm = selectImm(CurDAG, DL, XLenVT, APF.bitcastToAPInt().getSExtValue(),
                   *Subtarget);
   return true;
 }

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
   bool canSplatOperand(Instruction *I, int Operand) const;
   /// Return true if a vector instruction will lower to a target instruction
   /// able to splat the given operand.
   bool canSplatOperand(unsigned Opcode, int Operand) const;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
   bool shouldScalarizeBinop(SDValue VecOp) const override;
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
+  bool isLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
                                unsigned Index) const override;
 
   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
 
   bool preferScalarizeSplat(unsigned Opc) const override;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::isOffsetFoldingLegal(
     const GlobalAddressSDNode *GA) const {
   // In order to maximise the opportunity for common subexpression elimination,
   // keep a separate ADD node for the global address offset instead of folding
   // it in the global address node. Later peephole optimisations may choose to
   // fold it back in when profitable.
   return false;
 }
 
+bool RISCVTargetLowering::isLegalZfaFPImm(const APFloat &Imm, EVT VT) const {
+  if (!Subtarget.hasStdExtZfa() || !VT.isSimple())
+    return false;
+
+  switch (VT.getSimpleVT().SimpleTy) {
+  default:
+    return false;
+  case MVT::f16:
+    return (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh()) &&
+           RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1;
+  case MVT::f32:
+    return RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1;
+  case MVT::f64:
+    assert(Subtarget.hasStdExtD() && "Expect D extension");
+    return RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1;
+  }
+}
+
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   if (VT == MVT::f16 && !Subtarget.hasStdExtZfhOrZfhmin())
     return false;
   if (VT == MVT::f32 && !Subtarget.hasStdExtF())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())
     return false;
 
-  if (Subtarget.hasStdExtZfa()) {
-    // fli.h requires Zfh, but we might only have Zfhmin.
-    if (VT == MVT::f16 && Subtarget.hasStdExtZfh() &&
-        RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1)
-      return true;
-    if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1)
-      return true;
-    if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1)
-      return true;
-  }
+  if (isLegalZfaFPImm(Imm, VT))
 
   // Cannot create a 64 bit floating-point immediate value for rv32.
   if (Subtarget.getXLen() < VT.getScalarSizeInBits()) {
     // td can handle +0.0 or -0.0 already.
     // -0.0 can be created by fmv + fneg.
     return Imm.isZero();
   }
   // Special case: the cost for -0.0 is 1.

llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+experimental-zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+experimental-zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 8 x half> @vsplat_f16_0p625() {
+; CHECK-LABEL: vsplat_f16_0p625:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.h ft0, 0.625
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> poison, half 0.625, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x half> %splat
+}
+
+define <vscale x 8 x float> @vsplat_f32_0p75() {
+; CHECK-LABEL: vsplat_f32_0p75:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.s ft0, 0.75
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> poison, float 0.75, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x float> %splat
+}
+
+define <vscale x 8 x double> @vsplat_f64_neg1() {
+; CHECK-LABEL: vsplat_f64_neg1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.d ft0, -1.0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vfmv.v.f v8, ft0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x double> poison, double -1.0, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x double> %splat
+}