[RISCV] Peak through BITCAST in isUsedByReturnOnly

[luke]

Summary

A follow up to 47b1f8362aa409b591b5e9c8a9ff0e3e1d76ed9c,
This covers some more cases on soft-float ABIs with the f/d extension.
I left the TODO in as there is still the case where we need to handle rv32i without f/d, but that looks like it requires changes to SelectionDAGLegalize::ExpandFPLibCall

[reames]

Can you update the review description to be more specific? The current text sounds like you're adding new libcalls, but you're really just peeking through a bitcast.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13266

Move the bitcast check above the comment please?

13271

The comparison here is non-idiomatic. Use != instead.

[luke]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13271

Whoops, this was left in from an earlier version, will remove

[luke]

Address comments, redo description

[reames]

LGTM

[asb]

LGTM, thanks!

[jrtc27]

s/Peak/Peek/ in the title

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13265–13266

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13265–13266

Never mind, that goes the wrong way...

[luke]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13265–13266

Didn't know that method existed, looks handy.

[luke]

Fix commit message typo

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 // Check if the result of the node is only used as a return value, as
 // otherwise we can't perform a tail-call.
 bool RISCVTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
   if (N->getNumValues() != 1)
     return false;
   if (!N->hasNUsesOfValue(1, 0))
     return false;
 
   SDNode *Copy = *N->use_begin();
   // TODO: Handle additional opcodes in order to support tail-calling libcalls
   // with soft float ABIs.
-  if (Copy->getOpcode() != ISD::CopyToReg) {
+  if (Copy->getOpcode() == ISD::BITCAST)
+    return isUsedByReturnOnly(Copy, Chain);
+
+  if (!(Copy->getOpcode() == ISD::CopyToReg)) {
     return false;
   }
 
   // If the ISD::CopyToReg has a glue operand, we conservatively assume it
   // isn't safe to perform a tail call.
   if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() == MVT::Glue)
     return false;
 

llvm/test/CodeGen/RISCV/float-frem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define float @frem_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: frem_f32:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    addi sp, sp, -16
-; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    call fmodf@plt
-; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    addi sp, sp, 16
-; RV32IF-NEXT:    ret
+; RV32IF-NEXT:    tail fmodf@plt
 ;
 ; RV64IF-LABEL: frem_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call fmodf@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/libcall-tail-calls.ll

 
 declare float @llvm.sin.f32(float)
 
 define float @sin_f32(float %a) nounwind {
 ; F-ABI-ALL-LABEL: sin_f32:
 ; F-ABI-ALL:       # %bb.0:
 ; F-ABI-ALL-NEXT:    tail sinf@plt
 ;
-; RV32-ILP32-ALL-LABEL: sin_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call sinf@plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: sin_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail sinf@plt
+;
+; RV32I-ILP32-LABEL: sin_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call sinf@plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64-LP64-ALL-LABEL: sin_f32:
 ; RV64-LP64-ALL:       # %bb.0:
 ; RV64-LP64-ALL-NEXT:    addi sp, sp, -16
 ; RV64-LP64-ALL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-LP64-ALL-NEXT:    call sinf@plt
 ; RV64-LP64-ALL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-LP64-ALL-NEXT:    addi sp, sp, 16
 ; RV64-LP64-ALL-NEXT:    ret
   %1 = call float @llvm.sin.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.powi.f32.i32(float, i32)
 
 define float @powi_f32(float %a, i32 %b) nounwind {
 ; RV32IFD-ILP32D-LABEL: powi_f32:
 ; RV32IFD-ILP32D:       # %bb.0:
 ; RV32IFD-ILP32D-NEXT:    tail __powisf2@plt
 ;
 ; RV32IF-ILP32F-LABEL: powi_f32:
 ; RV32IF-ILP32F:       # %bb.0:
 ; RV32IF-ILP32F-NEXT:    tail __powisf2@plt
 ;
-; RV32-ILP32-ALL-LABEL: powi_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call __powisf2@plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: powi_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail __powisf2@plt
+;
+; RV32I-ILP32-LABEL: powi_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call __powisf2@plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64IFD-LP64D-LABEL: powi_f32:
 ; RV64IFD-LP64D:       # %bb.0:
 ; RV64IFD-LP64D-NEXT:    addi sp, sp, -16
 ; RV64IFD-LP64D-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-LP64D-NEXT:    sext.w a0, a0
 ; RV64IFD-LP64D-NEXT:    call __powisf2@plt
 ; RV64IFD-LP64D-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload

 ; RV64IF-LP64F:       # %bb.0:
 ; RV64IF-LP64F-NEXT:    addi sp, sp, -16
 ; RV64IF-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-LP64F-NEXT:    call sin@plt
 ; RV64IF-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-LP64F-NEXT:    addi sp, sp, 16
 ; RV64IF-LP64F-NEXT:    ret
 ;
-; RV64-LP64-ALL-LABEL: sin_f64:
-; RV64-LP64-ALL:       # %bb.0:
-; RV64-LP64-ALL-NEXT:    addi sp, sp, -16
-; RV64-LP64-ALL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-LP64-ALL-NEXT:    call sin@plt
-; RV64-LP64-ALL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-LP64-ALL-NEXT:    addi sp, sp, 16
-; RV64-LP64-ALL-NEXT:    ret
+; RV64IFD-LP64-LABEL: sin_f64:
+; RV64IFD-LP64:       # %bb.0:
+; RV64IFD-LP64-NEXT:    tail sin@plt
+;
+; RV64I-LP64-LABEL: sin_f64:
+; RV64I-LP64:       # %bb.0:
+; RV64I-LP64-NEXT:    addi sp, sp, -16
+; RV64I-LP64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64-NEXT:    call sin@plt
+; RV64I-LP64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64-NEXT:    addi sp, sp, 16
+; RV64I-LP64-NEXT:    ret
   %1 = call double @llvm.sin.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.powi.f64.i32(double, i32)
 
 define double @powi_f64(double %a, i32 %b) nounwind {
 ; RV32IFD-ILP32D-LABEL: powi_f64: