[RISCV] Use vfirst.m to extract the first element from mask vector.

[jacquesguan]

Summary

This patch uses vfirst.m to extract the first bit of mask.

[reames]

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

223

Hm, having a vsetvli toggle here is unfortunate. Can we achieve this in a slightly different way?

We could use a id vector, comparison with index, and then and to form a mask which could then be popcnt. This also generalize for any index.

We could use a vfirst.m and a scalar comparison against 0. This only works when index is the first potentially set bit.

We could extract the bottom ETYPE bits of the mask into a scalar, and then mask out the low bit. This works for any index < min(XLEN, sizeinbits(ETYPE)).

Have you given these options (or others) consideration? Your chosen solution appears correct, I'm just looking for some discussion of what other options you considered and rejected before we land this.

[jacquesguan]

change to vfirst.m.

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

223

Let me summarize:

1, For all index:
vmv + vmseq create index mask
vcpop.m extract the element

This way uses 3 instruction which is same as the current method, I don't think this way is better.

2, For the fisrt element:

vfirst.m + sltu

This way will change the vsetvli instruction with a scalar comparison instruction, I think it should be better as maybe avoid potential vsetvl insertion.

3, For the index located in min(XLEN, sizeinbits(ETYPE)):

This alreay achieved with fixed vector, but the scalable vector should be improved.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

1840

This comment appears to have been copy and pasted without updating

[jacquesguan]

Address comment.

[jacquesguan]

Fix typo.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

1840

Done.

[jacquesguan]

ping.

[jacquesguan]

ping.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
 
   // Vector sign/zero extend with additional mask & VL operands.
   VSEXT_VL,
   VZEXT_VL,
 
   //  vcpop.m with additional mask and VL operands.
   VCPOP_VL,
 
+  //  vfirst.m with additional mask and VL operands.
+  VFIRST_VL,
+
   // Reads value of CSR.
   // The first operand is a chain pointer. The second specifies address of the
   // required CSR. Two results are produced, the read value and the new chain
   // pointer.
   READ_CSR,
   // Write value to CSR.
   // The first operand is a chain pointer, the second specifies address of the
   // required CSR and the third is the value to write. The result is the new

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
   SDLoc DL(Op);
   SDValue Idx = Op.getOperand(1);
   SDValue Vec = Op.getOperand(0);
   EVT EltVT = Op.getValueType();
   MVT VecVT = Vec.getSimpleValueType();
   MVT XLenVT = Subtarget.getXLenVT();
 
   if (VecVT.getVectorElementType() == MVT::i1) {
+    // Use vfirst.m to extract the first bit.
+    if (isNullConstant(Idx)) {
+      MVT ContainerVT = VecVT;
+      if (VecVT.isFixedLengthVector()) {
+        ContainerVT = getContainerForFixedLengthVector(VecVT);
+        Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
+      }
+      auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
+      SDValue Vfirst =
+          DAG.getNode(RISCVISD::VFIRST_VL, DL, XLenVT, Vec, Mask, VL);
+      return DAG.getSetCC(DL, XLenVT, Vfirst, DAG.getConstant(0, DL, XLenVT),
+                          ISD::SETEQ);
+    }
     if (VecVT.isFixedLengthVector()) {
       unsigned NumElts = VecVT.getVectorNumElements();
       if (NumElts >= 8) {
         MVT WideEltVT;
         unsigned WidenVecLen;
         SDValue ExtractElementIdx;
         SDValue ExtractBitIdx;
         unsigned MaxEEW = Subtarget.getELEN();

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

 
 def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL",
                             SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
                                                  SDTCisVec<1>, SDTCisInt<1>,
                                                  SDTCVecEltisVT<2, i1>,
                                                  SDTCisSameNumEltsAs<1, 2>,
                                                  SDTCisVT<3, XLenVT>]>>;
 
+def riscv_vfirst_vl : SDNode<"RISCVISD::VFIRST_VL",
+                            SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
+                                                 SDTCisVec<1>, SDTCisInt<1>,
+                                                 SDTCVecEltisVT<2, i1>,
+                                                 SDTCisSameNumEltsAs<1, 2>,
+                                                 SDTCisVT<3, XLenVT>]>>;
+
 def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>,
                                                SDTCisSameNumEltsAs<0, 1>,
                                                SDTCisSameNumEltsAs<1, 2>,
                                                SDTCVecEltisVT<2, i1>,
                                                SDTCisVT<3, XLenVT>]>;
 def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>;
 def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>;
 
foreach mti = AllMasks in {
   def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask),
                                     VLOpFrag)),
             (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX)
                  VR:$rs2, GPR:$vl, mti.Log2SEW)>;
   def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0),
                                     VLOpFrag)),
             (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK")
                  VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
+
+  // 16.3 vfirst find-first-set mask bit
+  def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask true_mask),
+                                    VLOpFrag)),
+            (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX)
+                 VR:$rs2, GPR:$vl, mti.Log2SEW)>;
+  def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask V0),
+                                    VLOpFrag)),
+            (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX # "_MASK")
+                 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
 }
 
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructions] in {
 // 17.1. Integer Scalar Move Instructions
 // 17.4. Vector Register Gather Instruction
 foreach vti = AllIntegerVectors in {

llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll

 ; RV32-NEXT:    vmv1r.v v10, v0
 ; RV32-NEXT:    andi a0, a0, 1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; RV32-NEXT:    vmv.v.x v11, a0
 ; RV32-NEXT:    vmsne.vi v0, v11, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32-NEXT:    vmerge.vvm v8, v9, v8, v0
-; RV32-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; RV32-NEXT:    vmv.v.i v9, 0
-; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.x.s a0, v8
-; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT:    vmv1r.v v0, v10
-; RV32-NEXT:    vmerge.vim v8, v9, 1, v0
-; RV32-NEXT:    vmv.x.s a1, v8
-; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    vfirst.m a1, v10
+; RV32-NEXT:    seqz a1, a1
+; RV32-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; RV32-NEXT:    vmv.v.x v8, a1
 ; RV32-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 10
 ; RV32-NEXT:    vse32.v v8, (a0), v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: constant_folding_crash:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    ld a0, 8(a0)
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    andi a0, a0, 1
 ; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; RV64-NEXT:    vmv.v.x v13, a0
 ; RV64-NEXT:    vmsne.vi v0, v13, 0
 ; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; RV64-NEXT:    vmv.v.i v10, 0
-; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
-; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV64-NEXT:    vmv1r.v v0, v12
-; RV64-NEXT:    vmerge.vim v8, v10, 1, v0
-; RV64-NEXT:    vmv.x.s a1, v8
-; RV64-NEXT:    andi a1, a1, 1
+; RV64-NEXT:    vfirst.m a1, v12
+; RV64-NEXT:    seqz a1, a1
+; RV64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; RV64-NEXT:    vmv.v.x v8, a1
 ; RV64-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 10
 ; RV64-NEXT:    vse32.v v8, (a0), v0.t
 ; RV64-NEXT:    ret
 entry:
   %sunkaddr = getelementptr i8, ptr %v54, i64 8

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

; RV64-NEXT:    ret
   ret i1 %c
 }
 
 define i1 @extractelt_nxv1i1_idx0(<vscale x 1 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv1i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
   %b = icmp eq <vscale x 1 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 1 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv2i1_idx0(<vscale x 2 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv2i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
   %b = icmp eq <vscale x 2 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 2 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv4i1_idx0(<vscale x 4 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv4i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
   %b = icmp eq <vscale x 4 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 4 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv8i1_idx0(<vscale x 8 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv8i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl1r.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
   %b = icmp eq <vscale x 8 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 8 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv16i1_idx0(<vscale x 16 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv16i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v10, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v10
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
   %b = icmp eq <vscale x 16 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 16 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv32i1_idx0(<vscale x 32 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv32i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl4r.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v12, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v12
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 32 x i8>, <vscale x 32 x i8>* %x
   %b = icmp eq <vscale x 32 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 32 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_nxv64i1_idx0(<vscale x 64 x i8>* %x) nounwind {
 ; CHECK-LABEL: extractelt_nxv64i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl8r.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v16, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v16
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <vscale x 64 x i8>, <vscale x 64 x i8>* %x
   %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 64 x i1> %b, i64 0
   ret i1 %c
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

 
 define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
 ; CHECK-LABEL: reverse_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT:    vslidedown.vi v9, v8, 1
-; CHECK-NEXT:    vmv.x.s a0, v9
-; CHECK-NEXT:    vmv.x.s a1, v8
+; CHECK-NEXT:    vslidedown.vi v8, v8, 1
+; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a1, v0
+; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    vmv.v.x v8, a1
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
 ; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
   %res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a)
   ret <2 x i1> %res
 }
 
 define <4 x i1> @reverse_v4i1(<4 x i1> %a) {
 ; CHECK-LABEL: reverse_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    addi a0, sp, 15
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
-; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    vslidedown.vi v9, v8, 1
 ; CHECK-NEXT:    addi a0, sp, 14
 ; CHECK-NEXT:    vse8.v v9, (a0)
 ; CHECK-NEXT:    vslidedown.vi v9, v8, 2
 ; CHECK-NEXT:    addi a0, sp, 13
 ; CHECK-NEXT:    vse8.v v9, (a0)
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 3
 ; CHECK-NEXT:    addi a0, sp, 12
 ; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vfirst.m a1, v0
+; CHECK-NEXT:    seqz a1, a1
+; CHECK-NEXT:    sb a1, 15(sp)
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %res = call <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1> %a)
   ret <4 x i1> %res
 }
 
 define <8 x i1> @reverse_v8i1(<8 x i1> %a) {
 ; RV32-BITS-UNKNOWN-LABEL: reverse_v8i1:
 ; RV32-BITS-UNKNOWN:       # %bb.0:
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, -16
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 16
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
+; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
+; RV32-BITS-UNKNOWN-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 24
 ; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a0, 8(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    addi a0, sp, 8
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-BITS-UNKNOWN-NEXT:    vle8.v v8, (a0)
 ; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, 16
 ; RV32-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV32-BITS-256-LABEL: reverse_v8i1:
 ; RV32-BITS-256:       # %bb.0:
 ; RV32-BITS-256-NEXT:    addi sp, sp, -16
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa_offset 16
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV32-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-BITS-256-NEXT:    vfirst.m a0, v0
+; RV32-BITS-256-NEXT:    seqz a0, a0
+; RV32-BITS-256-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    andi a1, a0, 1
-; RV32-BITS-256-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 30
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 29
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 28
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 12(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 27
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 11(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 26
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 10(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 25
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 9(sp)
 ; RV32-BITS-256-NEXT:    slli a0, a0, 24
 ; RV32-BITS-256-NEXT:    srli a0, a0, 31
 ; RV32-BITS-256-NEXT:    sb a0, 8(sp)
 ; RV32-BITS-256-NEXT:    addi a0, sp, 8
-; RV32-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-BITS-256-NEXT:    vle8.v v8, (a0)
 ; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-256-NEXT:    addi sp, sp, 16
 ; RV32-BITS-256-NEXT:    ret
 ;
 ; RV32-BITS-512-LABEL: reverse_v8i1:
 ; RV32-BITS-512:       # %bb.0:
 ; RV32-BITS-512-NEXT:    addi sp, sp, -16
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa_offset 16
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV32-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-BITS-512-NEXT:    vfirst.m a0, v0
+; RV32-BITS-512-NEXT:    seqz a0, a0
+; RV32-BITS-512-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    andi a1, a0, 1
-; RV32-BITS-512-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 30
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 29
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 28
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 12(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 27
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 11(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 26
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 10(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 25
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 9(sp)
 ; RV32-BITS-512-NEXT:    slli a0, a0, 24
 ; RV32-BITS-512-NEXT:    srli a0, a0, 31
 ; RV32-BITS-512-NEXT:    sb a0, 8(sp)
 ; RV32-BITS-512-NEXT:    addi a0, sp, 8
-; RV32-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-BITS-512-NEXT:    vle8.v v8, (a0)
 ; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-512-NEXT:    addi sp, sp, 16
 ; RV32-BITS-512-NEXT:    ret
 ;
 ; RV64-BITS-UNKNOWN-LABEL: reverse_v8i1:
 ; RV64-BITS-UNKNOWN:       # %bb.0:
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, -16
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 16
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
+; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
+; RV64-BITS-UNKNOWN-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 62
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 56
 ; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a0, 8(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    addi a0, sp, 8
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-BITS-UNKNOWN-NEXT:    vle8.v v8, (a0)
 ; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, 16
 ; RV64-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV64-BITS-256-LABEL: reverse_v8i1:
 ; RV64-BITS-256:       # %bb.0:
 ; RV64-BITS-256-NEXT:    addi sp, sp, -16
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa_offset 16
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV64-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-BITS-256-NEXT:    vfirst.m a0, v0
+; RV64-BITS-256-NEXT:    seqz a0, a0
+; RV64-BITS-256-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    andi a1, a0, 1
-; RV64-BITS-256-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 62
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 61
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 60
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 12(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 59
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 11(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 58
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 10(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 57
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 9(sp)
 ; RV64-BITS-256-NEXT:    slli a0, a0, 56
 ; RV64-BITS-256-NEXT:    srli a0, a0, 63
 ; RV64-BITS-256-NEXT:    sb a0, 8(sp)
 ; RV64-BITS-256-NEXT:    addi a0, sp, 8
-; RV64-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-BITS-256-NEXT:    vle8.v v8, (a0)
 ; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-256-NEXT:    addi sp, sp, 16
 ; RV64-BITS-256-NEXT:    ret
 ;
 ; RV64-BITS-512-LABEL: reverse_v8i1:
 ; RV64-BITS-512:       # %bb.0:
 ; RV64-BITS-512-NEXT:    addi sp, sp, -16
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa_offset 16
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
+; RV64-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-BITS-512-NEXT:    vfirst.m a0, v0
+; RV64-BITS-512-NEXT:    seqz a0, a0
+; RV64-BITS-512-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    andi a1, a0, 1
-; RV64-BITS-512-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 62
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 61
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 60
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 12(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 59
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 11(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 58
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 10(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 57
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 9(sp)
 ; RV64-BITS-512-NEXT:    slli a0, a0, 56
 ; RV64-BITS-512-NEXT:    srli a0, a0, 63
 ; RV64-BITS-512-NEXT:    sb a0, 8(sp)
 ; RV64-BITS-512-NEXT:    addi a0, sp, 8
-; RV64-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-BITS-512-NEXT:    vle8.v v8, (a0)
 ; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-512-NEXT:    addi sp, sp, 16
 ; RV64-BITS-512-NEXT:    ret
   %res = call <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1> %a)
   ret <8 x i1> %res
 }
 
 define <16 x i1> @reverse_v16i1(<16 x i1> %a) {
 ; RV32-BITS-UNKNOWN-LABEL: reverse_v16i1:
 ; RV32-BITS-UNKNOWN:       # %bb.0:
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, -16
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 16
+; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
+; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
+; RV32-BITS-UNKNOWN-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31

 ; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, 16
 ; RV32-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV32-BITS-256-LABEL: reverse_v16i1:
 ; RV32-BITS-256:       # %bb.0:
 ; RV32-BITS-256-NEXT:    addi sp, sp, -16
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa_offset 16
+; RV32-BITS-256-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV32-BITS-256-NEXT:    vfirst.m a0, v0
+; RV32-BITS-256-NEXT:    seqz a0, a0
+; RV32-BITS-256-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-256-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    andi a1, a0, 1
-; RV32-BITS-256-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 30
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 29
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
 ; RV32-BITS-256-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-256-NEXT:    slli a1, a0, 28
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31

 ; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-256-NEXT:    addi sp, sp, 16
 ; RV32-BITS-256-NEXT:    ret
 ;
 ; RV32-BITS-512-LABEL: reverse_v16i1:
 ; RV32-BITS-512:       # %bb.0:
 ; RV32-BITS-512-NEXT:    addi sp, sp, -16
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa_offset 16
+; RV32-BITS-512-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV32-BITS-512-NEXT:    vfirst.m a0, v0
+; RV32-BITS-512-NEXT:    seqz a0, a0
+; RV32-BITS-512-NEXT:    sb a0, 15(sp)
 ; RV32-BITS-512-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    andi a1, a0, 1
-; RV32-BITS-512-NEXT:    sb a1, 15(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 30
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 14(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 29
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
 ; RV32-BITS-512-NEXT:    sb a1, 13(sp)
 ; RV32-BITS-512-NEXT:    slli a1, a0, 28
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31

 ; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-512-NEXT:    addi sp, sp, 16
 ; RV32-BITS-512-NEXT:    ret
 ;
 ; RV64-BITS-UNKNOWN-LABEL: reverse_v16i1:
 ; RV64-BITS-UNKNOWN:       # %bb.0:
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, -16
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 16
+; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
+; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
+; RV64-BITS-UNKNOWN-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 62
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63

 ; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, 16
 ; RV64-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV64-BITS-256-LABEL: reverse_v16i1:
 ; RV64-BITS-256:       # %bb.0:
 ; RV64-BITS-256-NEXT:    addi sp, sp, -16
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa_offset 16
+; RV64-BITS-256-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV64-BITS-256-NEXT:    vfirst.m a0, v0
+; RV64-BITS-256-NEXT:    seqz a0, a0
+; RV64-BITS-256-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-256-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    andi a1, a0, 1
-; RV64-BITS-256-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 62
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 61
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
 ; RV64-BITS-256-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-256-NEXT:    slli a1, a0, 60
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63

 ; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-256-NEXT:    addi sp, sp, 16
 ; RV64-BITS-256-NEXT:    ret
 ;
 ; RV64-BITS-512-LABEL: reverse_v16i1:
 ; RV64-BITS-512:       # %bb.0:
 ; RV64-BITS-512-NEXT:    addi sp, sp, -16
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa_offset 16
+; RV64-BITS-512-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV64-BITS-512-NEXT:    vfirst.m a0, v0
+; RV64-BITS-512-NEXT:    seqz a0, a0
+; RV64-BITS-512-NEXT:    sb a0, 15(sp)
 ; RV64-BITS-512-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    andi a1, a0, 1
-; RV64-BITS-512-NEXT:    sb a1, 15(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 62
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 14(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 61
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
 ; RV64-BITS-512-NEXT:    sb a1, 13(sp)
 ; RV64-BITS-512-NEXT:    slli a1, a0, 60
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63

 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-BITS-UNKNOWN-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-BITS-UNKNOWN-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-UNKNOWN-NEXT:    addi s0, sp, 64
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-UNKNOWN-NEXT:    andi sp, sp, -32
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
+; RV32-BITS-UNKNOWN-NEXT:    li a0, 32
+; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a1, v0
+; RV32-BITS-UNKNOWN-NEXT:    seqz a1, a1
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 31(sp)
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 0(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 30(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 29(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 28(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 27(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 26(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 25(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 24(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 23(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 22(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 21(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 20(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 19(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 18(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 17(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 16(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 8(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 7(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 6(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 5(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 4(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 3(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
+; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a1, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 0(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 30
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 30(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 29
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 29(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 28
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 28(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 27
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 27(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 26
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 26(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 25
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 25(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 24
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 24(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 23
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 23(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 22
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 22(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 21
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 21(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 20
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 20(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 19
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 19(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 18
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 18(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 17
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 17(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 16
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 16(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 15
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 15(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 14
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 14(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 13
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 13(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 12
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 12(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 11
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 11(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 10
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 10(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 9
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 9(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 8
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 8(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 7
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 7(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 6
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 6(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 5
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 5(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 4
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 4(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 3
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 3(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 2
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 2(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a1, a1, 1
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 2(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a0, 1(sp)
-; RV32-BITS-UNKNOWN-NEXT:    li a0, 32
+; RV32-BITS-UNKNOWN-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    mv a1, sp
 ; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV32-BITS-UNKNOWN-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, s0, -64
 ; RV32-BITS-UNKNOWN-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-BITS-UNKNOWN-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, 64
 ; RV32-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV32-BITS-256-LABEL: reverse_v32i1:
 ; RV32-BITS-256:       # %bb.0:
 ; RV32-BITS-256-NEXT:    addi sp, sp, -64
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-BITS-256-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-BITS-256-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-BITS-256-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-256-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-256-NEXT:    addi s0, sp, 64
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-256-NEXT:    andi sp, sp, -32
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    andi a1, a0, 1
+; RV32-BITS-256-NEXT:    li a0, 32
+; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV32-BITS-256-NEXT:    vfirst.m a1, v0
+; RV32-BITS-256-NEXT:    seqz a1, a1
 ; RV32-BITS-256-NEXT:    sb a1, 31(sp)
-; RV32-BITS-256-NEXT:    srli a1, a0, 31
-; RV32-BITS-256-NEXT:    sb a1, 0(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 30
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 30(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 29(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 28(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 27(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 26(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 25(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 24(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 23
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 23(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 22
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 22(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 21
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 21(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 20
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 20(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 19
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 19(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 18
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 18(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 17
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 17(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 16
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 16(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 15
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 15(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 14
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 14(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 13
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 13(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 12
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 12(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 11
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 11(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 10
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 10(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 9
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 9(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 8
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 8(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 7
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 7(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 6
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 6(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 5
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 5(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 4
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 4(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 3
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 3(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 2
+; RV32-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV32-BITS-256-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-256-NEXT:    srli a2, a1, 31
+; RV32-BITS-256-NEXT:    sb a2, 0(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 30
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 30(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 29
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 29(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 28
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 28(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 27
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 27(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 26
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 26(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 25
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 25(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 24
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 24(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 23
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 23(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 22
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 22(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 21
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 21(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 20
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 20(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 19
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 19(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 18
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 18(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 17
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 17(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 16
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 16(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 15
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 15(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 14
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 14(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 13
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 13(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 12
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 12(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 11
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 11(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 10
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 10(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 9
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 9(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 8
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 8(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 7
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 7(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 6
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 6(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 5
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 5(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 4
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 4(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 3
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 3(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 2
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 2(sp)
+; RV32-BITS-256-NEXT:    slli a1, a1, 1
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 2(sp)
-; RV32-BITS-256-NEXT:    slli a0, a0, 1
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    sb a0, 1(sp)
-; RV32-BITS-256-NEXT:    li a0, 32
+; RV32-BITS-256-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-256-NEXT:    mv a1, sp
 ; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV32-BITS-256-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-256-NEXT:    addi sp, s0, -64
 ; RV32-BITS-256-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-BITS-256-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-BITS-256-NEXT:    addi sp, sp, 64
 ; RV32-BITS-256-NEXT:    ret
 ;
 ; RV32-BITS-512-LABEL: reverse_v32i1:
 ; RV32-BITS-512:       # %bb.0:
 ; RV32-BITS-512-NEXT:    addi sp, sp, -64
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-BITS-512-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-BITS-512-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-BITS-512-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-512-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-512-NEXT:    addi s0, sp, 64
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-512-NEXT:    andi sp, sp, -32
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    andi a1, a0, 1
+; RV32-BITS-512-NEXT:    li a0, 32
+; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV32-BITS-512-NEXT:    vfirst.m a1, v0
+; RV32-BITS-512-NEXT:    seqz a1, a1
 ; RV32-BITS-512-NEXT:    sb a1, 31(sp)
-; RV32-BITS-512-NEXT:    srli a1, a0, 31
-; RV32-BITS-512-NEXT:    sb a1, 0(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 30
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 30(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 29(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 28(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 27(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 26(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 25(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 24(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 23
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 23(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 22
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 22(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 21
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 21(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 20
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 20(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 19
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 19(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 18
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 18(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 17
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 17(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 16
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 16(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 15
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 15(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 14
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 14(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 13
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 13(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 12
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 12(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 11
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 11(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 10
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 10(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 9
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 9(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 8
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 8(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 7
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 7(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 6
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 6(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 5
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 5(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 4
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 4(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 3
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 3(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 2
+; RV32-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV32-BITS-512-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-512-NEXT:    srli a2, a1, 31
+; RV32-BITS-512-NEXT:    sb a2, 0(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 30
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 30(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 29
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 29(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 28
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 28(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 27
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 27(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 26
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 26(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 25
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 25(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 24
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 24(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 23
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 23(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 22
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 22(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 21
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 21(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 20
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 20(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 19
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 19(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 18
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 18(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 17
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 17(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 16
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 16(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 15
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 15(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 14
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 14(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 13
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 13(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 12
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 12(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 11
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 11(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 10
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 10(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 9
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 9(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 8
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 8(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 7
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 7(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 6
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 6(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 5
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 5(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 4
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 4(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 3
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 3(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 2
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 2(sp)
+; RV32-BITS-512-NEXT:    slli a1, a1, 1
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 2(sp)
-; RV32-BITS-512-NEXT:    slli a0, a0, 1
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    sb a0, 1(sp)
-; RV32-BITS-512-NEXT:    li a0, 32
+; RV32-BITS-512-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-512-NEXT:    mv a1, sp
 ; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV32-BITS-512-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-512-NEXT:    addi sp, s0, -64
 ; RV32-BITS-512-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-BITS-512-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-BITS-512-NEXT:    addi sp, sp, 64
 ; RV32-BITS-512-NEXT:    ret
 ;
 ; RV64-BITS-UNKNOWN-LABEL: reverse_v32i1:
 ; RV64-BITS-UNKNOWN:       # %bb.0:
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, -64
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-BITS-UNKNOWN-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-BITS-UNKNOWN-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-UNKNOWN-NEXT:    addi s0, sp, 64
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-UNKNOWN-NEXT:    andi sp, sp, -32
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
+; RV64-BITS-UNKNOWN-NEXT:    li a0, 32
+; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a1, v0
+; RV64-BITS-UNKNOWN-NEXT:    seqz a1, a1
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 31(sp)
-; RV64-BITS-UNKNOWN-NEXT:    srliw a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 0(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 30(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 29(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 28(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 27(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 26(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 25(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 24(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 55
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 23(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 54
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 22(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 53
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 21(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 52
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 20(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 51
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 19(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 50
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 18(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 49
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 17(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 48
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 16(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 47
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 46
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 45
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 44
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 43
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 42
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 41
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 40
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 8(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 39
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 7(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 38
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 6(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 37
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 5(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 36
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 4(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 35
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 3(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 34
+; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-UNKNOWN-NEXT:    srliw a2, a1, 31
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 0(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 62
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 30(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 61
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 29(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 60
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 28(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 59
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 27(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 58
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 26(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 57
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 25(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 56
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 24(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 55
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 23(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 54
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 22(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 53
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 21(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 52
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 20(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 51
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 19(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 50
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 18(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 49
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 17(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 48
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 16(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 47
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 15(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 46
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 14(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 45
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 13(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 44
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 12(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 43
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 11(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 42
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 10(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 41
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 9(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 40
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 8(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 39
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 7(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 38
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 6(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 37
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 5(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 36
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 4(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 35
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 3(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 34
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 2(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a1, a1, 33
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 2(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 33
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a0, 1(sp)
-; RV64-BITS-UNKNOWN-NEXT:    li a0, 32
+; RV64-BITS-UNKNOWN-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    mv a1, sp
 ; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV64-BITS-UNKNOWN-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, s0, -64
 ; RV64-BITS-UNKNOWN-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-BITS-UNKNOWN-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, 64
 ; RV64-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV64-BITS-256-LABEL: reverse_v32i1:
 ; RV64-BITS-256:       # %bb.0:
 ; RV64-BITS-256-NEXT:    addi sp, sp, -64
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-BITS-256-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-BITS-256-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-BITS-256-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-256-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-256-NEXT:    addi s0, sp, 64
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-256-NEXT:    andi sp, sp, -32
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    andi a1, a0, 1
+; RV64-BITS-256-NEXT:    li a0, 32
+; RV64-BITS-256-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV64-BITS-256-NEXT:    vfirst.m a1, v0
+; RV64-BITS-256-NEXT:    seqz a1, a1
 ; RV64-BITS-256-NEXT:    sb a1, 31(sp)
-; RV64-BITS-256-NEXT:    srliw a1, a0, 31
-; RV64-BITS-256-NEXT:    sb a1, 0(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 62
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 30(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 29(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 28(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 27(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 26(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 25(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 24(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 55
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 23(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 54
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 22(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 53
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 21(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 52
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 20(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 51
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 19(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 50
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 18(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 49
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 17(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 48
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 16(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 47
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 15(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 46
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 14(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 45
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 13(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 44
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 12(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 43
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 11(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 42
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 10(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 41
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 9(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 40
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 8(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 39
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 7(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 38
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 6(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 37
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 5(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 36
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 4(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 35
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 3(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 34
+; RV64-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV64-BITS-256-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-256-NEXT:    srliw a2, a1, 31
+; RV64-BITS-256-NEXT:    sb a2, 0(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 62
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 30(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 61
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 29(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 60
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 28(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 59
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 27(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 58
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 26(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 57
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 25(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 56
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 24(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 55
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 23(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 54
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 22(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 53
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 21(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 52
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 20(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 51
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 19(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 50
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 18(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 49
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 17(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 48
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 16(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 47
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 15(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 46
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 14(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 45
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 13(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 44
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 12(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 43
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 11(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 42
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 10(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 41
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 9(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 40
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 8(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 39
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 7(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 38
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 6(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 37
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 5(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 36
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 4(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 35
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 3(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 34
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 2(sp)
+; RV64-BITS-256-NEXT:    slli a1, a1, 33
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 2(sp)
-; RV64-BITS-256-NEXT:    slli a0, a0, 33
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    sb a0, 1(sp)
-; RV64-BITS-256-NEXT:    li a0, 32
+; RV64-BITS-256-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-256-NEXT:    mv a1, sp
 ; RV64-BITS-256-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV64-BITS-256-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-256-NEXT:    addi sp, s0, -64
 ; RV64-BITS-256-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-BITS-256-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-BITS-256-NEXT:    addi sp, sp, 64
 ; RV64-BITS-256-NEXT:    ret
 ;
 ; RV64-BITS-512-LABEL: reverse_v32i1:
 ; RV64-BITS-512:       # %bb.0:
 ; RV64-BITS-512-NEXT:    addi sp, sp, -64
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-BITS-512-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-BITS-512-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-BITS-512-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-512-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-512-NEXT:    addi s0, sp, 64
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-512-NEXT:    andi sp, sp, -32
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    andi a1, a0, 1
+; RV64-BITS-512-NEXT:    li a0, 32
+; RV64-BITS-512-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; RV64-BITS-512-NEXT:    vfirst.m a1, v0
+; RV64-BITS-512-NEXT:    seqz a1, a1
 ; RV64-BITS-512-NEXT:    sb a1, 31(sp)
-; RV64-BITS-512-NEXT:    srliw a1, a0, 31
-; RV64-BITS-512-NEXT:    sb a1, 0(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 62
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 30(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 29(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 28(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 27(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 26(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 25(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 24(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 55
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 23(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 54
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 22(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 53
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 21(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 52
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 20(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 51
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 19(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 50
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 18(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 49
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 17(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 48
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 16(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 47
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 15(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 46
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 14(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 45
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 13(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 44
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 12(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 43
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 11(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 42
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 10(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 41
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 9(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 40
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 8(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 39
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 7(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 38
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 6(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 37
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 5(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 36
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 4(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 35
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 3(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 34
+; RV64-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
+; RV64-BITS-512-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-512-NEXT:    srliw a2, a1, 31
+; RV64-BITS-512-NEXT:    sb a2, 0(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 62
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 30(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 61
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 29(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 60
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 28(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 59
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 27(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 58
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 26(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 57
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 25(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 56
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 24(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 55
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 23(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 54
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 22(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 53
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 21(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 52
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 20(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 51
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 19(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 50
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 18(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 49
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 17(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 48
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 16(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 47
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 15(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 46
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 14(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 45
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 13(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 44
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 12(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 43
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 11(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 42
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 10(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 41
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 9(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 40
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 8(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 39
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 7(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 38
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 6(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 37
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 5(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 36
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 4(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 35
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 3(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 34
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 2(sp)
+; RV64-BITS-512-NEXT:    slli a1, a1, 33
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 2(sp)
-; RV64-BITS-512-NEXT:    slli a0, a0, 33
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    sb a0, 1(sp)
-; RV64-BITS-512-NEXT:    li a0, 32
+; RV64-BITS-512-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-512-NEXT:    mv a1, sp
 ; RV64-BITS-512-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; RV64-BITS-512-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-512-NEXT:    addi sp, s0, -64
 ; RV64-BITS-512-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-BITS-512-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload

 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-BITS-UNKNOWN-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-BITS-UNKNOWN-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-UNKNOWN-NEXT:    addi s0, sp, 128
 ; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-UNKNOWN-NEXT:    andi sp, sp, -64
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
+; RV32-BITS-UNKNOWN-NEXT:    li a0, 64
+; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a1, v0
+; RV32-BITS-UNKNOWN-NEXT:    seqz a1, a1
 ; RV32-BITS-UNKNOWN-NEXT:    sb a1, 63(sp)
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 32(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 62(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 61(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 60(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 59(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 58(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 57(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 56(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 55(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 54(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 53(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 52(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 51(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 50(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 49(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 48(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 47(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 46(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 45(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 44(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 43(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 42(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 41(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 40(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 39(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 38(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 37(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 36(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 35(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
+; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a1, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 32(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 30
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 62(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 29
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 61(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 28
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 60(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 27
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 59(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 26
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 58(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 25
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 57(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 24
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 56(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 23
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 55(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 22
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 54(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 21
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 53(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 20
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 52(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 19
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 51(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 18
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 50(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 17
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 49(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 16
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 48(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 15
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 47(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 14
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 46(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 13
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 45(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 12
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 44(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 11
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 43(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 10
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 42(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 9
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 41(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 8
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 40(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 7
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 39(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 6
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 38(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 5
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 37(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 4
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 36(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 3
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 35(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 2
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 34(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a1, a1, 1
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 34(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a0, 33(sp)
+; RV32-BITS-UNKNOWN-NEXT:    sb a1, 33(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v8
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 31(sp)
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 0(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 30(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 29(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 28(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 27(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 26(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 25(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 24(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 23(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 22(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 21(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 20(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 19(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 18(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 17(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 16(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
+; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v8
+; RV32-BITS-UNKNOWN-NEXT:    andi a2, a1, 1
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 31(sp)
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a1, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 0(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 30
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 30(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 29
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 29(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 28
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 28(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 27
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 27(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 26
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 26(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 25
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 25(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 24
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 24(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 23
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 23(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 22
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 22(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 21
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 21(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 20
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 20(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 19
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 19(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 18
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 18(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 17
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 17(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 16
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 16(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 15
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 15(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 14
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 14(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 13
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 13(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 12
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 12(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 11
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 11(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 10
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 10(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 9
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 9(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 8
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 8(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 7
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 7(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 6
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 6(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 5
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 5(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 4
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 4(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 3
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 3(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 2
+; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
+; RV32-BITS-UNKNOWN-NEXT:    sb a2, 2(sp)
+; RV32-BITS-UNKNOWN-NEXT:    slli a1, a1, 1
 ; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 8(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 7(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 6(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 5(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 4(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 3(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a1, 2(sp)
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    sb a0, 1(sp)
-; RV32-BITS-UNKNOWN-NEXT:    li a0, 64
+; RV32-BITS-UNKNOWN-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-UNKNOWN-NEXT:    mv a1, sp
 ; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV32-BITS-UNKNOWN-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, s0, -128
 ; RV32-BITS-UNKNOWN-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-BITS-UNKNOWN-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, 128
 ; RV32-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV32-BITS-256-LABEL: reverse_v64i1:
 ; RV32-BITS-256:       # %bb.0:
 ; RV32-BITS-256-NEXT:    addi sp, sp, -128
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-BITS-256-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-BITS-256-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-BITS-256-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-256-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-256-NEXT:    addi s0, sp, 128
 ; RV32-BITS-256-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-256-NEXT:    andi sp, sp, -64
-; RV32-BITS-256-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    andi a1, a0, 1
+; RV32-BITS-256-NEXT:    li a0, 64
+; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV32-BITS-256-NEXT:    vfirst.m a1, v0
+; RV32-BITS-256-NEXT:    seqz a1, a1
 ; RV32-BITS-256-NEXT:    sb a1, 63(sp)
-; RV32-BITS-256-NEXT:    srli a1, a0, 31
-; RV32-BITS-256-NEXT:    sb a1, 32(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 30
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 62(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 61(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 60(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 59(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 58(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 57(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 56(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 23
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 55(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 22
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 54(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 21
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 53(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 20
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 52(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 19
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 51(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 18
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 50(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 17
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 49(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 16
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 48(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 15
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 47(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 14
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 46(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 13
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 45(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 12
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 44(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 11
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 43(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 10
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 42(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 9
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 41(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 8
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 40(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 7
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 39(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 6
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 38(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 5
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 37(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 4
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 36(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 3
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 35(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 2
+; RV32-BITS-256-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-BITS-256-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-256-NEXT:    srli a2, a1, 31
+; RV32-BITS-256-NEXT:    sb a2, 32(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 30
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 62(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 29
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 61(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 28
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 60(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 27
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 59(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 26
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 58(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 25
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 57(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 24
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 56(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 23
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 55(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 22
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 54(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 21
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 53(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 20
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 52(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 19
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 51(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 18
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 50(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 17
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 49(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 16
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 48(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 15
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 47(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 14
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 46(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 13
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 45(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 12
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 44(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 11
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 43(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 10
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 42(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 9
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 41(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 8
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 40(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 7
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 39(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 6
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 38(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 5
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 37(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 4
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 36(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 3
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 35(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 2
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 34(sp)
+; RV32-BITS-256-NEXT:    slli a1, a1, 1
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 34(sp)
-; RV32-BITS-256-NEXT:    slli a0, a0, 1
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    sb a0, 33(sp)
+; RV32-BITS-256-NEXT:    sb a1, 33(sp)
 ; RV32-BITS-256-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v8
-; RV32-BITS-256-NEXT:    andi a1, a0, 1
-; RV32-BITS-256-NEXT:    sb a1, 31(sp)
-; RV32-BITS-256-NEXT:    srli a1, a0, 31
-; RV32-BITS-256-NEXT:    sb a1, 0(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 30
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 30(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 29(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 28(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 27(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 26(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
+; RV32-BITS-256-NEXT:    vmv.x.s a1, v8
+; RV32-BITS-256-NEXT:    andi a2, a1, 1
+; RV32-BITS-256-NEXT:    sb a2, 31(sp)
+; RV32-BITS-256-NEXT:    srli a2, a1, 31
+; RV32-BITS-256-NEXT:    sb a2, 0(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 30
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 30(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 29
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 29(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 28
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 28(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 27
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 27(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 26
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 26(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 25
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 25(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 24
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 24(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 23
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 23(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 22
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 22(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 21
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 21(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 20
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 20(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 19
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 19(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 18
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 18(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 17
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 17(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 16
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 16(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 15
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 15(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 14
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 14(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 13
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 13(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 12
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 12(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 11
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 11(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 10
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 10(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 9
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 9(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 8
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 8(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 7
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 7(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 6
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 6(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 5
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 5(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 4
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 4(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 3
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 3(sp)
+; RV32-BITS-256-NEXT:    slli a2, a1, 2
+; RV32-BITS-256-NEXT:    srli a2, a2, 31
+; RV32-BITS-256-NEXT:    sb a2, 2(sp)
+; RV32-BITS-256-NEXT:    slli a1, a1, 1
 ; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 25(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 24(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 23
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 23(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 22
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 22(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 21
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 21(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 20
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 20(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 19
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 19(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 18
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 18(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 17
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 17(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 16
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 16(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 15
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 15(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 14
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 14(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 13
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 13(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 12
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 12(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 11
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 11(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 10
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 10(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 9
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 9(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 8
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 8(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 7
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 7(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 6
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 6(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 5
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 5(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 4
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 4(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 3
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 3(sp)
-; RV32-BITS-256-NEXT:    slli a1, a0, 2
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    sb a1, 2(sp)
-; RV32-BITS-256-NEXT:    slli a0, a0, 1
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    sb a0, 1(sp)
-; RV32-BITS-256-NEXT:    li a0, 64
+; RV32-BITS-256-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-256-NEXT:    mv a1, sp
 ; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV32-BITS-256-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-256-NEXT:    addi sp, s0, -128
 ; RV32-BITS-256-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-BITS-256-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-BITS-256-NEXT:    addi sp, sp, 128
 ; RV32-BITS-256-NEXT:    ret
 ;
 ; RV32-BITS-512-LABEL: reverse_v64i1:
 ; RV32-BITS-512:       # %bb.0:
 ; RV32-BITS-512-NEXT:    addi sp, sp, -128
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-BITS-512-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-BITS-512-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-BITS-512-NEXT:    .cfi_offset ra, -4
 ; RV32-BITS-512-NEXT:    .cfi_offset s0, -8
 ; RV32-BITS-512-NEXT:    addi s0, sp, 128
 ; RV32-BITS-512-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-BITS-512-NEXT:    andi sp, sp, -64
-; RV32-BITS-512-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    andi a1, a0, 1
+; RV32-BITS-512-NEXT:    li a0, 64
+; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV32-BITS-512-NEXT:    vfirst.m a1, v0
+; RV32-BITS-512-NEXT:    seqz a1, a1
 ; RV32-BITS-512-NEXT:    sb a1, 63(sp)
-; RV32-BITS-512-NEXT:    srli a1, a0, 31
-; RV32-BITS-512-NEXT:    sb a1, 32(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 30
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 62(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 61(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 60(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 59(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 58(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 57(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 56(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 23
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 55(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 22
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 54(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 21
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 53(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 20
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 52(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 19
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 51(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 18
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 50(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 17
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 49(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 16
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 48(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 15
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 47(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 14
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 46(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 13
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 45(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 12
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 44(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 11
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 43(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 10
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 42(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 9
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 41(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 8
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 40(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 7
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 39(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 6
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 38(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 5
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 37(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 4
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 36(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 3
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 35(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 2
+; RV32-BITS-512-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-BITS-512-NEXT:    vmv.x.s a1, v0
+; RV32-BITS-512-NEXT:    srli a2, a1, 31
+; RV32-BITS-512-NEXT:    sb a2, 32(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 30
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 62(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 29
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 61(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 28
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 60(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 27
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 59(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 26
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 58(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 25
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 57(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 24
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 56(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 23
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 55(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 22
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 54(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 21
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 53(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 20
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 52(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 19
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 51(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 18
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 50(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 17
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 49(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 16
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 48(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 15
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 47(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 14
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 46(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 13
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 45(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 12
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 44(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 11
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 43(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 10
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 42(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 9
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 41(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 8
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 40(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 7
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 39(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 6
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 38(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 5
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 37(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 4
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 36(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 3
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 35(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 2
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 34(sp)
+; RV32-BITS-512-NEXT:    slli a1, a1, 1
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 34(sp)
-; RV32-BITS-512-NEXT:    slli a0, a0, 1
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    sb a0, 33(sp)
+; RV32-BITS-512-NEXT:    sb a1, 33(sp)
 ; RV32-BITS-512-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v8
-; RV32-BITS-512-NEXT:    andi a1, a0, 1
-; RV32-BITS-512-NEXT:    sb a1, 31(sp)
-; RV32-BITS-512-NEXT:    srli a1, a0, 31
-; RV32-BITS-512-NEXT:    sb a1, 0(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 30
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 30(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 29(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 28(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 27(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 26(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 25(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 24(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 23
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 23(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 22
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 22(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 21
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 21(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 20
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 20(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 19
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 19(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 18
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 18(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 17
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 17(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 16
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 16(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 15
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 15(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 14
+; RV32-BITS-512-NEXT:    vmv.x.s a1, v8
+; RV32-BITS-512-NEXT:    andi a2, a1, 1
+; RV32-BITS-512-NEXT:    sb a2, 31(sp)
+; RV32-BITS-512-NEXT:    srli a2, a1, 31
+; RV32-BITS-512-NEXT:    sb a2, 0(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 30
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 30(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 29
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 29(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 28
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 28(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 27
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 27(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 26
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 26(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 25
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 25(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 24
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 24(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 23
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 23(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 22
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 22(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 21
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 21(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 20
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 20(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 19
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 19(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 18
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 18(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 17
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 17(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 16
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 16(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 15
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 15(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 14
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 14(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 13
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 13(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 12
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 12(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 11
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 11(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 10
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 10(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 9
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 9(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 8
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 8(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 7
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 7(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 6
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 6(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 5
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 5(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 4
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 4(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 3
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 3(sp)
+; RV32-BITS-512-NEXT:    slli a2, a1, 2
+; RV32-BITS-512-NEXT:    srli a2, a2, 31
+; RV32-BITS-512-NEXT:    sb a2, 2(sp)
+; RV32-BITS-512-NEXT:    slli a1, a1, 1
 ; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 14(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 13
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 13(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 12
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 12(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 11
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 11(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 10
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 10(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 9
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 9(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 8
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 8(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 7
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 7(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 6
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 6(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 5
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 5(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 4
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 4(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 3
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 3(sp)
-; RV32-BITS-512-NEXT:    slli a1, a0, 2
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    sb a1, 2(sp)
-; RV32-BITS-512-NEXT:    slli a0, a0, 1
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    sb a0, 1(sp)
-; RV32-BITS-512-NEXT:    li a0, 64
+; RV32-BITS-512-NEXT:    sb a1, 1(sp)
 ; RV32-BITS-512-NEXT:    mv a1, sp
 ; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV32-BITS-512-NEXT:    vle8.v v8, (a1)
 ; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-BITS-512-NEXT:    addi sp, s0, -128
 ; RV32-BITS-512-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-BITS-512-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-BITS-512-NEXT:    addi sp, sp, 128
 ; RV32-BITS-512-NEXT:    ret
 ;
 ; RV64-BITS-UNKNOWN-LABEL: reverse_v64i1:
 ; RV64-BITS-UNKNOWN:       # %bb.0:
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, -128
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-BITS-UNKNOWN-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-BITS-UNKNOWN-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-UNKNOWN-NEXT:    addi s0, sp, 128
 ; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-UNKNOWN-NEXT:    andi sp, sp, -64
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    andi a1, a0, 1
+; RV64-BITS-UNKNOWN-NEXT:    li a0, 64
+; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a1, v0
+; RV64-BITS-UNKNOWN-NEXT:    seqz a1, a1
 ; RV64-BITS-UNKNOWN-NEXT:    sb a1, 63(sp)
-; RV64-BITS-UNKNOWN-NEXT:    srliw a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 32(sp)
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 0(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 62(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 61(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 60(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 59(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 58(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 57(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 56(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 55
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 55(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 54
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 54(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 53
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 53(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 52
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 52(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 51
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 51(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 50
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 50(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 49
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 49(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 48
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 48(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 47
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 47(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 46
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 46(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 45
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 45(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 44
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 44(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 43
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 43(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 42
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 42(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 41
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 41(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 40
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 40(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 39
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 39(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 38
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 38(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 37
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 37(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 36
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 36(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 35
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 35(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 34
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 34(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 33
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 33(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 31(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 30(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 29(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 28(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 27(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 26(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 25(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 24(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 23(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 22(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 21(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 20(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 19(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 18(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 17(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 16(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 15(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 14(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 13(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 12(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 11(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 10(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 9(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 8(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 7(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 6(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 5(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 4(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 3(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
+; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-UNKNOWN-NEXT:    srliw a2, a1, 31
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 32(sp)
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a1, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 0(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 62
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 62(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 61
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 61(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 60
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 60(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 59
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 59(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 58
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 58(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 57
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 57(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 56
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 56(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 55
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 55(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 54
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 54(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 53
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 53(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 52
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 52(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 51
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 51(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 50
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 50(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 49
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 49(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 48
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 48(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 47
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 47(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 46
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 46(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 45
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 45(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 44
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 44(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 43
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 43(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 42
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 42(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 41
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 41(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 40
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 40(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 39
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 39(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 38
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 38(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 37
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 37(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 36
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 36(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 35
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 35(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 34
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 34(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 33
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 33(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 31
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 31(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 30
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 30(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 29
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 29(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 28
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 28(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 27
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 27(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 26
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 26(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 25
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 25(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 24
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 24(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 23
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 23(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 22
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 22(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 21
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 21(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 20
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 20(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 19
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 19(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 18
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 18(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 17
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 17(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 16
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 16(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 15
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 15(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 14
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 14(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 13
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 13(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 12
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 12(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 11
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 11(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 10
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 10(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 9
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 9(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 8
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 8(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 7
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 7(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 6
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 6(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 5
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 5(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 4
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 4(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 3
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 3(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a2, a1, 2
+; RV64-BITS-UNKNOWN-NEXT:    srli a2, a2, 63
+; RV64-BITS-UNKNOWN-NEXT:    sb a2, 2(sp)
+; RV64-BITS-UNKNOWN-NEXT:    slli a1, a1, 1
 ; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a1, 2(sp)
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 1
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    sb a0, 1(sp)
-; RV64-BITS-UNKNOWN-NEXT:    li a0, 64
+; RV64-BITS-UNKNOWN-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-UNKNOWN-NEXT:    mv a1, sp
 ; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV64-BITS-UNKNOWN-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, s0, -128
 ; RV64-BITS-UNKNOWN-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-BITS-UNKNOWN-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, 128
 ; RV64-BITS-UNKNOWN-NEXT:    ret
 ;
 ; RV64-BITS-256-LABEL: reverse_v64i1:
 ; RV64-BITS-256:       # %bb.0:
 ; RV64-BITS-256-NEXT:    addi sp, sp, -128
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-BITS-256-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-BITS-256-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-BITS-256-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-256-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-256-NEXT:    addi s0, sp, 128
 ; RV64-BITS-256-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-256-NEXT:    andi sp, sp, -64
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    andi a1, a0, 1
+; RV64-BITS-256-NEXT:    li a0, 64
+; RV64-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV64-BITS-256-NEXT:    vfirst.m a1, v0
+; RV64-BITS-256-NEXT:    seqz a1, a1
 ; RV64-BITS-256-NEXT:    sb a1, 63(sp)
-; RV64-BITS-256-NEXT:    srliw a1, a0, 31
-; RV64-BITS-256-NEXT:    sb a1, 32(sp)
-; RV64-BITS-256-NEXT:    srli a1, a0, 63
-; RV64-BITS-256-NEXT:    sb a1, 0(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 62
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 62(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 61(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 60(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 59(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 58(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 57(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 56(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 55
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 55(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 54
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 54(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 53
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 53(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 52
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 52(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 51
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 51(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 50
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 50(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 49
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 49(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 48
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 48(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 47
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 47(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 46
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 46(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 45
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 45(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 44
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 44(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 43
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 43(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 42
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 42(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 41
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 41(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 40
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 40(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 39
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 39(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 38
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 38(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 37
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 37(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 36
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 36(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 35
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 35(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 34
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 34(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 33
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 33(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 31
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 31(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 30
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 30(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 29
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 29(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 28
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 28(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 27
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 27(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 26
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 26(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 25
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 25(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 24
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 24(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 23
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 23(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 22
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 22(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 21
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 21(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 20
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 20(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 19
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 19(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 18
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 18(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 17
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 17(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 16
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 16(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 15
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 15(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 14
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 14(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 13
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 13(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 12
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 12(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 11
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 11(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 10
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 10(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 9
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 9(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 8
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 8(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 7
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 7(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 6
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 6(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 5
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 5(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 4
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 4(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 3
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 3(sp)
-; RV64-BITS-256-NEXT:    slli a1, a0, 2
+; RV64-BITS-256-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
+; RV64-BITS-256-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-256-NEXT:    srliw a2, a1, 31
+; RV64-BITS-256-NEXT:    sb a2, 32(sp)
+; RV64-BITS-256-NEXT:    srli a2, a1, 63
+; RV64-BITS-256-NEXT:    sb a2, 0(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 62
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 62(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 61
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 61(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 60
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 60(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 59
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 59(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 58
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 58(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 57
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 57(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 56
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 56(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 55
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 55(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 54
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 54(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 53
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 53(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 52
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 52(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 51
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 51(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 50
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 50(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 49
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 49(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 48
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 48(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 47
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 47(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 46
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 46(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 45
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 45(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 44
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 44(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 43
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 43(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 42
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 42(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 41
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 41(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 40
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 40(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 39
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 39(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 38
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 38(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 37
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 37(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 36
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 36(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 35
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 35(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 34
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 34(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 33
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 33(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 31
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 31(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 30
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 30(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 29
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 29(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 28
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 28(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 27
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 27(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 26
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 26(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 25
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 25(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 24
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 24(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 23
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 23(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 22
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 22(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 21
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 21(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 20
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 20(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 19
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 19(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 18
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 18(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 17
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 17(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 16
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 16(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 15
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 15(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 14
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 14(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 13
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 13(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 12
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 12(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 11
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 11(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 10
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 10(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 9
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 9(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 8
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 8(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 7
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 7(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 6
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 6(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 5
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 5(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 4
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 4(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 3
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 3(sp)
+; RV64-BITS-256-NEXT:    slli a2, a1, 2
+; RV64-BITS-256-NEXT:    srli a2, a2, 63
+; RV64-BITS-256-NEXT:    sb a2, 2(sp)
+; RV64-BITS-256-NEXT:    slli a1, a1, 1
 ; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    sb a1, 2(sp)
-; RV64-BITS-256-NEXT:    slli a0, a0, 1
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    sb a0, 1(sp)
-; RV64-BITS-256-NEXT:    li a0, 64
+; RV64-BITS-256-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-256-NEXT:    mv a1, sp
 ; RV64-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV64-BITS-256-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-256-NEXT:    addi sp, s0, -128
 ; RV64-BITS-256-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-BITS-256-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-BITS-256-NEXT:    addi sp, sp, 128
 ; RV64-BITS-256-NEXT:    ret
 ;
 ; RV64-BITS-512-LABEL: reverse_v64i1:
 ; RV64-BITS-512:       # %bb.0:
 ; RV64-BITS-512-NEXT:    addi sp, sp, -128
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-BITS-512-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-BITS-512-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-BITS-512-NEXT:    .cfi_offset ra, -8
 ; RV64-BITS-512-NEXT:    .cfi_offset s0, -16
 ; RV64-BITS-512-NEXT:    addi s0, sp, 128
 ; RV64-BITS-512-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-BITS-512-NEXT:    andi sp, sp, -64
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    andi a1, a0, 1
+; RV64-BITS-512-NEXT:    li a0, 64
+; RV64-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; RV64-BITS-512-NEXT:    vfirst.m a1, v0
+; RV64-BITS-512-NEXT:    seqz a1, a1
 ; RV64-BITS-512-NEXT:    sb a1, 63(sp)
-; RV64-BITS-512-NEXT:    srliw a1, a0, 31
-; RV64-BITS-512-NEXT:    sb a1, 32(sp)
-; RV64-BITS-512-NEXT:    srli a1, a0, 63
-; RV64-BITS-512-NEXT:    sb a1, 0(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 62
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 62(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 61(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 60(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 59(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 58(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 57(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 56(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 55
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 55(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 54
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 54(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 53
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 53(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 52
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 52(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 51
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 51(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 50
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 50(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 49
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 49(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 48
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 48(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 47
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 47(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 46
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 46(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 45
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 45(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 44
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 44(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 43
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 43(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 42
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 42(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 41
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 41(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 40
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 40(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 39
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 39(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 38
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 38(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 37
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 37(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 36
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 36(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 35
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 35(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 34
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 34(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 33
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 33(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 31
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 31(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 30
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 30(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 29
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 29(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 28
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 28(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 27
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 27(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 26
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 26(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 25
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 25(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 24
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 24(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 23
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 23(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 22
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 22(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 21
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 21(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 20
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 20(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 19
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 19(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 18
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 18(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 17
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 17(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 16
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 16(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 15
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 15(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 14
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 14(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 13
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 13(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 12
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 12(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 11
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 11(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 10
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 10(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 9
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 9(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 8
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 8(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 7
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 7(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 6
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 6(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 5
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 5(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 4
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 4(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 3
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 3(sp)
-; RV64-BITS-512-NEXT:    slli a1, a0, 2
+; RV64-BITS-512-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
+; RV64-BITS-512-NEXT:    vmv.x.s a1, v0
+; RV64-BITS-512-NEXT:    srliw a2, a1, 31
+; RV64-BITS-512-NEXT:    sb a2, 32(sp)
+; RV64-BITS-512-NEXT:    srli a2, a1, 63
+; RV64-BITS-512-NEXT:    sb a2, 0(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 62
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 62(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 61
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 61(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 60
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 60(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 59
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 59(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 58
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 58(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 57
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 57(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 56
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 56(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 55
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 55(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 54
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 54(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 53
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 53(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 52
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 52(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 51
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 51(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 50
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 50(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 49
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 49(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 48
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 48(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 47
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 47(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 46
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 46(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 45
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 45(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 44
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 44(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 43
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 43(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 42
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 42(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 41
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 41(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 40
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 40(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 39
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 39(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 38
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 38(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 37
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 37(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 36
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 36(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 35
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 35(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 34
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 34(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 33
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 33(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 31
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 31(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 30
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 30(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 29
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 29(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 28
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 28(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 27
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 27(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 26
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 26(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 25
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 25(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 24
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 24(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 23
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 23(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 22
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 22(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 21
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 21(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 20
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 20(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 19
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 19(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 18
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 18(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 17
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 17(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 16
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 16(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 15
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 15(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 14
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 14(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 13
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 13(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 12
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 12(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 11
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 11(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 10
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 10(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 9
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 9(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 8
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 8(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 7
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 7(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 6
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 6(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 5
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 5(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 4
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 4(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 3
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 3(sp)
+; RV64-BITS-512-NEXT:    slli a2, a1, 2
+; RV64-BITS-512-NEXT:    srli a2, a2, 63
+; RV64-BITS-512-NEXT:    sb a2, 2(sp)
+; RV64-BITS-512-NEXT:    slli a1, a1, 1
 ; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    sb a1, 2(sp)
-; RV64-BITS-512-NEXT:    slli a0, a0, 1
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    sb a0, 1(sp)
-; RV64-BITS-512-NEXT:    li a0, 64
+; RV64-BITS-512-NEXT:    sb a1, 1(sp)
 ; RV64-BITS-512-NEXT:    mv a1, sp
 ; RV64-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; RV64-BITS-512-NEXT:    vle8.v v8, (a1)
 ; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
 ; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-BITS-512-NEXT:    addi sp, s0, -128
 ; RV64-BITS-512-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-BITS-512-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

; RV64ZBS-NEXT:    ret
   ret i1 %c
 }
 
 define i1 @extractelt_v1i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v1i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <1 x i8>, ptr %x
   %b = icmp eq <1 x i8> %a, zeroinitializer
   %c = extractelement <1 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v2i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v2i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <2 x i8>, ptr %x
   %b = icmp eq <2 x i8> %a, zeroinitializer
   %c = extractelement <2 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v4i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v4i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmseq.vi v0, v8, 0
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <4 x i8>, ptr %x
   %b = icmp eq <4 x i8> %a, zeroinitializer
   %c = extractelement <4 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v8i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v8i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmseq.vi v8, v8, 0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, ptr %x
   %b = icmp eq <8 x i8> %a, zeroinitializer
   %c = extractelement <8 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v16i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v16i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmseq.vi v8, v8, 0
-; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vfirst.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, ptr %x
   %b = icmp eq <16 x i8> %a, zeroinitializer
   %c = extractelement <16 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v32i1_idx0(ptr %x) nounwind {
 ; CHECK-LABEL: extractelt_v32i1_idx0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmseq.vi v10, v8, 0
-; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.x.s a0, v10
-; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vfirst.m a0, v10
+; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, ptr %x
   %b = icmp eq <32 x i8> %a, zeroinitializer
   %c = extractelement <32 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v64i1_idx0(ptr %x) nounwind {
-; RV32-LABEL: extractelt_v64i1_idx0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    li a1, 64
-; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT:    vle8.v v8, (a0)
-; RV32-NEXT:    vmseq.vi v12, v8, 0
-; RV32-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.x.s a0, v12
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: extractelt_v64i1_idx0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, 64
-; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT:    vle8.v v8, (a0)
-; RV64-NEXT:    vmseq.vi v12, v8, 0
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-NEXT:    vmv.x.s a0, v12
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    ret
-;
-; RV32ZBS-LABEL: extractelt_v64i1_idx0:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    li a1, 64
-; RV32ZBS-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; RV32ZBS-NEXT:    vle8.v v8, (a0)
-; RV32ZBS-NEXT:    vmseq.vi v12, v8, 0
-; RV32ZBS-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32ZBS-NEXT:    vmv.x.s a0, v12
-; RV32ZBS-NEXT:    andi a0, a0, 1
-; RV32ZBS-NEXT:    ret
-;
-; RV64ZBS-LABEL: extractelt_v64i1_idx0:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a1, 64
-; RV64ZBS-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; RV64ZBS-NEXT:    vle8.v v8, (a0)
-; RV64ZBS-NEXT:    vmseq.vi v12, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64ZBS-NEXT:    vmv.x.s a0, v12
-; RV64ZBS-NEXT:    andi a0, a0, 1
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: extractelt_v64i1_idx0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 64
+; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmseq.vi v12, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v12
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
   %a = load <64 x i8>, ptr %x
   %b = icmp eq <64 x i8> %a, zeroinitializer
   %c = extractelement <64 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v128i1_idx0(ptr %x) nounwind {
-; RV32-LABEL: extractelt_v128i1_idx0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    li a1, 128
-; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT:    vle8.v v8, (a0)
-; RV32-NEXT:    vmseq.vi v16, v8, 0
-; RV32-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
-; RV32-NEXT:    vmv.x.s a0, v16
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: extractelt_v128i1_idx0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, 128
-; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT:    vle8.v v8, (a0)
-; RV64-NEXT:    vmseq.vi v16, v8, 0
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-NEXT:    vmv.x.s a0, v16
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    ret
-;
-; RV32ZBS-LABEL: extractelt_v128i1_idx0:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    li a1, 128
-; RV32ZBS-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV32ZBS-NEXT:    vle8.v v8, (a0)
-; RV32ZBS-NEXT:    vmseq.vi v16, v8, 0
-; RV32ZBS-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
-; RV32ZBS-NEXT:    vmv.x.s a0, v16
-; RV32ZBS-NEXT:    andi a0, a0, 1
-; RV32ZBS-NEXT:    ret
-;
-; RV64ZBS-LABEL: extractelt_v128i1_idx0:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a1, 128
-; RV64ZBS-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV64ZBS-NEXT:    vle8.v v8, (a0)
-; RV64ZBS-NEXT:    vmseq.vi v16, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64ZBS-NEXT:    vmv.x.s a0, v16
-; RV64ZBS-NEXT:    andi a0, a0, 1
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: extractelt_v128i1_idx0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 128
+; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmseq.vi v16, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v16
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
   %a = load <128 x i8>, ptr %x
   %b = icmp eq <128 x i8> %a, zeroinitializer
   %c = extractelement <128 x i1> %b, i64 0
   ret i1 %c
 }
 
 define i1 @extractelt_v256i1_idx0(ptr %x) nounwind {
-; RV32-LABEL: extractelt_v256i1_idx0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    li a1, 128
-; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT:    vle8.v v8, (a0)
-; RV32-NEXT:    vmseq.vi v16, v8, 0
-; RV32-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
-; RV32-NEXT:    vmv.x.s a0, v16
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: extractelt_v256i1_idx0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, 128
-; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT:    vle8.v v8, (a0)
-; RV64-NEXT:    vmseq.vi v16, v8, 0
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-NEXT:    vmv.x.s a0, v16
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    ret
-;
-; RV32ZBS-LABEL: extractelt_v256i1_idx0:
-; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    li a1, 128
-; RV32ZBS-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV32ZBS-NEXT:    vle8.v v8, (a0)
-; RV32ZBS-NEXT:    vmseq.vi v16, v8, 0
-; RV32ZBS-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
-; RV32ZBS-NEXT:    vmv.x.s a0, v16
-; RV32ZBS-NEXT:    andi a0, a0, 1
-; RV32ZBS-NEXT:    ret
-;
-; RV64ZBS-LABEL: extractelt_v256i1_idx0:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a1, 128
-; RV64ZBS-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; RV64ZBS-NEXT:    vle8.v v8, (a0)
-; RV64ZBS-NEXT:    vmseq.vi v16, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64ZBS-NEXT:    vmv.x.s a0, v16
-; RV64ZBS-NEXT:    andi a0, a0, 1
-; RV64ZBS-NEXT:    ret
+; CHECK-LABEL: extractelt_v256i1_idx0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 128
+; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmseq.vi v16, v8, 0
+; CHECK-NEXT:    vfirst.m a0, v16
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
   %a = load <256 x i8>, ptr %x
   %b = icmp eq <256 x i8> %a, zeroinitializer
   %c = extractelement <256 x i1> %b, i64 0
   ret i1 %c
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
 ; RV32ZVE32F-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    vmv1r.v v8, v9
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1i8:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB0_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB0_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
 ; RV64ZVE32F-NEXT:    vlse8.v v8, (a0), zero
 ; RV64ZVE32F-NEXT:  .LBB0_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x i8> @llvm.masked.gather.v1i8.v1p0(<1 x ptr> %ptrs, i32 1, <1 x i1> %m, <1 x i8> %passthru)
   ret <1 x i8> %v
 }

 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, mu
 ; RV32ZVE32F-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    vmv1r.v v8, v9
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1i16:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB13_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB13_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV64ZVE32F-NEXT:    vlse16.v v8, (a0), zero
 ; RV64ZVE32F-NEXT:  .LBB13_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x i16> @llvm.masked.gather.v1i16.v1p0(<1 x ptr> %ptrs, i32 2, <1 x i1> %m, <1 x i16> %passthru)
   ret <1 x i16> %v
 }

 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV32ZVE32F-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    vmv.v.v v8, v9
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1i32:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB27_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB27_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV64ZVE32F-NEXT:    vlse32.v v8, (a0), zero
 ; RV64ZVE32F-NEXT:  .LBB27_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x i32> @llvm.masked.gather.v1i32.v1p0(<1 x ptr> %ptrs, i32 4, <1 x i1> %m, <1 x i32> %passthru)
   ret <1 x i32> %v
 }

 ; RV64V-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64V-NEXT:    vluxei64.v v9, (zero), v8, v0.t
 ; RV64V-NEXT:    vmv.v.v v8, v9
 ; RV64V-NEXT:    ret
 ;
 ; RV32ZVE32F-LABEL: mgather_v1i64:
 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV32ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV32ZVE32F-NEXT:    vmv.x.s a2, v9
-; RV32ZVE32F-NEXT:    andi a2, a2, 1
-; RV32ZVE32F-NEXT:    beqz a2, .LBB42_2
+; RV32ZVE32F-NEXT:    vfirst.m a2, v0
+; RV32ZVE32F-NEXT:    bnez a2, .LBB42_2
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
 ; RV32ZVE32F-NEXT:  .LBB42_2: # %else
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1i64:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v8, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v8, v8, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a2, v8
-; RV64ZVE32F-NEXT:    andi a2, a2, 1
-; RV64ZVE32F-NEXT:    beqz a2, .LBB42_2
+; RV64ZVE32F-NEXT:    vfirst.m a2, v0
+; RV64ZVE32F-NEXT:    bnez a2, .LBB42_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    ld a1, 0(a0)
 ; RV64ZVE32F-NEXT:  .LBB42_2: # %else
 ; RV64ZVE32F-NEXT:    mv a0, a1
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> %ptrs, i32 8, <1 x i1> %m, <1 x i64> %passthru)
   ret <1 x i64> %v
 }

 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, mu
 ; RV32ZVE32F-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    vmv1r.v v8, v9
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1f16:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB58_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB58_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV64ZVE32F-NEXT:    vlse16.v v8, (a0), zero
 ; RV64ZVE32F-NEXT:  .LBB58_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x half> @llvm.masked.gather.v1f16.v1p0(<1 x ptr> %ptrs, i32 2, <1 x i1> %m, <1 x half> %passthru)
   ret <1 x half> %v
 }

 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV32ZVE32F-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    vmv.v.v v8, v9
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1f32:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB68_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB68_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV64ZVE32F-NEXT:    vlse32.v v8, (a0), zero
 ; RV64ZVE32F-NEXT:  .LBB68_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x float> @llvm.masked.gather.v1f32.v1p0(<1 x ptr> %ptrs, i32 4, <1 x i1> %m, <1 x float> %passthru)
   ret <1 x float> %v
 }

 ; RV64V-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64V-NEXT:    vluxei64.v v9, (zero), v8, v0.t
 ; RV64V-NEXT:    vmv.v.v v8, v9
 ; RV64V-NEXT:    ret
 ;
 ; RV32ZVE32F-LABEL: mgather_v1f64:
 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV32ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV32ZVE32F-NEXT:    vmv.x.s a0, v9
-; RV32ZVE32F-NEXT:    andi a0, a0, 1
-; RV32ZVE32F-NEXT:    beqz a0, .LBB81_2
+; RV32ZVE32F-NEXT:    vfirst.m a0, v0
+; RV32ZVE32F-NEXT:    bnez a0, .LBB81_2
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a0)
 ; RV32ZVE32F-NEXT:  .LBB81_2: # %else
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_v1f64:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v8, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v8, v8, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v8
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB81_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB81_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.load
 ; RV64ZVE32F-NEXT:    fld fa0, 0(a0)
 ; RV64ZVE32F-NEXT:  .LBB81_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   %v = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> %ptrs, i32 8, <1 x i1> %m, <1 x double> %passthru)
   ret <1 x double> %v
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
 ; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1i8:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB0_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB0_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
 ; RV64ZVE32F-NEXT:    vse8.v v8, (a0)
 ; RV64ZVE32F-NEXT:  .LBB0_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1i8.v1p0(<1 x i8> %val, <1 x ptr> %ptrs, i32 1, <1 x i1> %m)
   ret void
 }

 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1i16:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB10_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB10_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV64ZVE32F-NEXT:    vse16.v v8, (a0)
 ; RV64ZVE32F-NEXT:  .LBB10_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1i16.v1p0(<1 x i16> %val, <1 x ptr> %ptrs, i32 2, <1 x i1> %m)
   ret void
 }

 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1i32:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB22_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB22_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV64ZVE32F-NEXT:    vse32.v v8, (a0)
 ; RV64ZVE32F-NEXT:  .LBB22_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1i32.v1p0(<1 x i32> %val, <1 x ptr> %ptrs, i32 4, <1 x i1> %m)
   ret void
 }

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
 ;
 ; RV32ZVE32F-LABEL: mscatter_v1i64:
 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV32ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV32ZVE32F-NEXT:    vmv.x.s a2, v9
-; RV32ZVE32F-NEXT:    andi a2, a2, 1
-; RV32ZVE32F-NEXT:    beqz a2, .LBB36_2
+; RV32ZVE32F-NEXT:    vfirst.m a2, v0
+; RV32ZVE32F-NEXT:    bnez a2, .LBB36_2
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    sw a1, 4(a2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(a2)
 ; RV32ZVE32F-NEXT:  .LBB36_2: # %else
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1i64:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v8, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v8, v8, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a2, v8
-; RV64ZVE32F-NEXT:    andi a2, a2, 1
-; RV64ZVE32F-NEXT:    beqz a2, .LBB36_2
+; RV64ZVE32F-NEXT:    vfirst.m a2, v0
+; RV64ZVE32F-NEXT:    bnez a2, .LBB36_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    sd a0, 0(a1)
 ; RV64ZVE32F-NEXT:  .LBB36_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> %val, <1 x ptr> %ptrs, i32 8, <1 x i1> %m)
   ret void
 }
 

 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1f16:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB52_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB52_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV64ZVE32F-NEXT:    vse16.v v8, (a0)
 ; RV64ZVE32F-NEXT:  .LBB52_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1f16.v1p0(<1 x half> %val, <1 x ptr> %ptrs, i32 2, <1 x i1> %m)
   ret void
 }

 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1f32:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB62_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB62_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; RV64ZVE32F-NEXT:    vse32.v v8, (a0)
 ; RV64ZVE32F-NEXT:  .LBB62_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1f32.v1p0(<1 x float> %val, <1 x ptr> %ptrs, i32 4, <1 x i1> %m)
   ret void
 }

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
 ; RV64-NEXT:    ret
 ;
 ; RV32ZVE32F-LABEL: mscatter_v1f64:
 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT:    vmv.v.i v9, 0
-; RV32ZVE32F-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV32ZVE32F-NEXT:    vmv.x.s a0, v9
-; RV32ZVE32F-NEXT:    andi a0, a0, 1
-; RV32ZVE32F-NEXT:    beqz a0, .LBB75_2
+; RV32ZVE32F-NEXT:    vfirst.m a0, v0
+; RV32ZVE32F-NEXT:    bnez a0, .LBB75_2
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)
 ; RV32ZVE32F-NEXT:  .LBB75_2: # %else
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v1f64:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.i v8, 0
-; RV64ZVE32F-NEXT:    vmerge.vim v8, v8, 1, v0
-; RV64ZVE32F-NEXT:    vmv.x.s a1, v8
-; RV64ZVE32F-NEXT:    andi a1, a1, 1
-; RV64ZVE32F-NEXT:    beqz a1, .LBB75_2
+; RV64ZVE32F-NEXT:    vfirst.m a1, v0
+; RV64ZVE32F-NEXT:    bnez a1, .LBB75_2
 ; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store
 ; RV64ZVE32F-NEXT:    fsd fa0, 0(a0)
 ; RV64ZVE32F-NEXT:  .LBB75_2: # %else
 ; RV64ZVE32F-NEXT:    ret
   call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> %val, <1 x ptr> %ptrs, i32 8, <1 x i1> %m)
   ret void
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV64
 
 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_or_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_or_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_or_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_or_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_or_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_or_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_xor_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_and_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_and_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_and_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_and_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_and_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_and_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_umax_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_umax_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_umax_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_umax_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_umax_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_smax_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_smax_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_smax_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_smax_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_smax_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_umin_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_umin_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_umin_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_umin_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_umin_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_smin_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_smin_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_smin_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_smin_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_smin_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v2i1:

 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_add_v1i1(<1 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v1i1:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX1-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v1i1:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX1-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX1-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX1-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX1-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX1-RV64-NEXT:    ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v1i1:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV32-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV32-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV32-NEXT:    slli a0, a0, 31
-; LMULMAX8-RV32-NEXT:    srai a0, a0, 31
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_add_v1i1:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT:    vmv.v.i v8, 0
-; LMULMAX8-RV64-NEXT:    vmerge.vim v8, v8, 1, v0
-; LMULMAX8-RV64-NEXT:    vmv.x.s a0, v8
-; LMULMAX8-RV64-NEXT:    slli a0, a0, 63
-; LMULMAX8-RV64-NEXT:    srai a0, a0, 63
-; LMULMAX8-RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_add_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_add_v2i1(<2 x i1> %v) {
 ; LMULMAX1-RV32-LABEL: vreduce_add_v2i1: