[RISCV] Optimize i64 insertelt on RV32.

[craig.topper]

Summary

We can use tail undisturbed vslide1down to insert into the vector.

This should make D136640 unneeded.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (IsLegalInsert) {
     SDValue ValLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Val, Zero);
     SDValue ValHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Val, One);
     MVT I32ContainerVT =
         MVT::getVectorVT(MVT::i32, ContainerVT.getVectorElementCount() * 2);
     SDValue I32Mask =
         getDefaultScalableVLOps(I32ContainerVT, DL, DAG, Subtarget).first;
     // Limit the active VL to two.
     SDValue InsertI64VL = DAG.getConstant(2, DL, XLenVT);
+    // If the Idx is 0 we can insert directly into the vector.
+    if (isNullConstant(Idx)) {
+      // First slide in the lo value, then the hi in above it. We use slide1down
+      // to avoid the register group overlap constraint of vslide1up.
+      ValInVec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32ContainerVT,
+                             Vec, Vec, ValLo, I32Mask, InsertI64VL);
+      // If the source vector is undef don't pass along the tail elements from
+      // the previous slide1down.
+      SDValue Tail = Vec.isUndef() ? Vec : ValInVec;
+      ValInVec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32ContainerVT,
+                             Tail, ValInVec, ValHi, I32Mask, InsertI64VL);
+      // Bitcast back to the right container type.
+      ValInVec = DAG.getBitcast(ContainerVT, ValInVec);
+
+      if (!VecVT.isFixedLengthVector())
+        return ValInVec;
+      return convertFromScalableVector(VecVT, ValInVec, DAG, Subtarget);
+    }
+
     // First slide in the lo value, then the hi in above it. We use slide1down
     // to avoid the register group overlap constraint of vslide1up.
     ValInVec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32ContainerVT,
                            DAG.getUNDEF(I32ContainerVT),
                            DAG.getUNDEF(I32ContainerVT), ValLo,
                            I32Mask, InsertI64VL);
     ValInVec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32ContainerVT,
                            DAG.getUNDEF(I32ContainerVT), ValInVec, ValHi,

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

; RV64ELEN32-NEXT:    ret
   ret <1 x i32> %b
 }
 
 define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v4i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v9, 0
+; RV32-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v4i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
 ;
; RV64ELEN32-NEXT:    ret
   ret <4 x i16> %b
 }
 
 define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v2i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v9, 0
+; RV32-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
 ;
; RV64ELEN32-NEXT:    ret
   ret <2 x i32> %b
 }
 
 define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v9, 0
+; RV32-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
 ;
 ; ELEN32-LABEL: bitcast_i64_v1i64:
 ; ELEN32:       # %bb.0:
 ; ELEN32-NEXT:    ret
   %b = bitcast i64 %a to <1 x i64>
   ret <1 x i64> %b
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

; RV64-FP-NEXT:    ret
   ret <1 x float> %b
 }
 
 define <4 x half> @bitcast_i64_v4f16(i64 %a) {
 ; RV32-FP-LABEL: bitcast_i64_v4f16:
 ; RV32-FP:       # %bb.0:
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-FP-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v9, 0
+; RV32-FP-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v4f16:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-FP-NEXT:    vmv.s.x v8, a0
 ; RV64-FP-NEXT:    ret
   %b = bitcast i64 %a to <4 x half>
   ret <4 x half> %b
 }
 
 define <2 x float> @bitcast_i64_v2f32(i64 %a) {
 ; RV32-FP-LABEL: bitcast_i64_v2f32:
 ; RV32-FP:       # %bb.0:
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-FP-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v9, 0
+; RV32-FP-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v2f32:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-FP-NEXT:    vmv.s.x v8, a0
 ; RV64-FP-NEXT:    ret
   %b = bitcast i64 %a to <2 x float>
   ret <2 x float> %b
 }
 
 define <1 x double> @bitcast_i64_v1f64(i64 %a) {
 ; RV32-FP-LABEL: bitcast_i64_v1f64:
 ; RV32-FP:       # %bb.0:
 ; RV32-FP-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32-FP-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-FP-NEXT:    vslide1down.vx v9, v8, a1
-; RV32-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV32-FP-NEXT:    vslideup.vi v8, v9, 0
+; RV32-FP-NEXT:    vslide1down.vx v8, v8, a1
 ; RV32-FP-NEXT:    ret
 ;
 ; RV64-FP-LABEL: bitcast_i64_v1f64:
 ; RV64-FP:       # %bb.0:
 ; RV64-FP-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-FP-NEXT:    vmv.s.x v8, a0
 ; RV64-FP-NEXT:    ret
   %b = bitcast i64 %a to <1 x double>

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

 ; RV32-NEXT:  .LBB5_2: # %else2
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB5_3: # %cond.load
 ; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-NEXT:    vmv.x.s a1, v8
 ; RV32-NEXT:    lw a2, 0(a1)
 ; RV32-NEXT:    lw a1, 4(a1)
-; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v8, a2
-; RV32-NEXT:    vslide1down.vx v10, v10, a1
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, tu, ma
-; RV32-NEXT:    vslideup.vi v9, v10, 0
+; RV32-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
+; RV32-NEXT:    vslide1down.vx v9, v9, a2
+; RV32-NEXT:    vslide1down.vx v9, v9, a1
 ; RV32-NEXT:    andi a0, a0, 2
 ; RV32-NEXT:    beqz a0, .LBB5_2
 ; RV32-NEXT:  .LBB5_4: # %cond.load1
 ; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
 ; RV32-NEXT:    vslidedown.vi v8, v8, 1
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    lw a1, 0(a0)
 ; RV32-NEXT:    lw a0, 4(a0)

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
   ret <vscale x 16 x i32> %r
 }
 
 define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT:    vslide1down.vx v9, v8, a0
-; CHECK-NEXT:    vslide1down.vx v9, v9, a1
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 0
+; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
+; CHECK-NEXT:    vslide1down.vx v8, v8, a0
+; CHECK-NEXT:    vslide1down.vx v8, v8, a1
 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
   ret <vscale x 1 x i64> %r
 }
 
 define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv1i64_imm:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
   ret <vscale x 1 x i64> %r
 }
 
 define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-NEXT:    vslide1down.vx v10, v8, a0
-; CHECK-NEXT:    vslide1down.vx v10, v10, a1
-; CHECK-NEXT:    vsetivli zero, 1, e64, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 0
+; CHECK-NEXT:    vsetivli zero, 2, e32, m2, tu, ma
+; CHECK-NEXT:    vslide1down.vx v8, v8, a0
+; CHECK-NEXT:    vslide1down.vx v8, v8, a1
 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
   ret <vscale x 2 x i64> %r
 }
 
 define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv2i64_imm:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
   ret <vscale x 2 x i64> %r
 }
 
 define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, m4, ta, ma
-; CHECK-NEXT:    vslide1down.vx v12, v8, a0
-; CHECK-NEXT:    vslide1down.vx v12, v12, a1
-; CHECK-NEXT:    vsetivli zero, 1, e64, m4, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v12, 0
+; CHECK-NEXT:    vsetivli zero, 2, e32, m4, tu, ma
+; CHECK-NEXT:    vslide1down.vx v8, v8, a0
+; CHECK-NEXT:    vslide1down.vx v8, v8, a1
 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
   ret <vscale x 4 x i64> %r
 }
 
 define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv4i64_imm:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
   ret <vscale x 4 x i64> %r
 }
 
 define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, m8, ta, ma
-; CHECK-NEXT:    vslide1down.vx v16, v8, a0
-; CHECK-NEXT:    vslide1down.vx v16, v16, a1
-; CHECK-NEXT:    vsetivli zero, 1, e64, m8, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v16, 0
+; CHECK-NEXT:    vsetivli zero, 2, e32, m8, tu, ma
+; CHECK-NEXT:    vslide1down.vx v8, v8, a0
+; CHECK-NEXT:    vslide1down.vx v8, v8, a1
 ; CHECK-NEXT:    ret
   %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
   ret <vscale x 8 x i64> %r
 }
 
 define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
 ; CHECK-LABEL: insertelt_nxv8i64_imm:
 ; CHECK:       # %bb.0: