[AArch64]Change printVectorList to print SVE vector range

[CarolineConcatto]

Summary

This patch has the prefered disassembly changed for SVE vector list.
For instance, instead of printing this assembly:

ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]

it will print this:

ld4d { z1.d-z4.d }, p0/z, [x0]

[sdesmalen]

llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll

459

it would be nice to have a space here, e.g. { z0.h - z3.h }.

llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll

9

Hi @CarolineConcatto, the vector-lists with two vectors should keep using the comma separated form, which is the preferred syntax for vector-lists as described in the Architecture Reference Manual.

[CarolineConcatto]

• Set of two sve registers should be separated by with ','

[sdesmalen]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1469–1473

We should be doing the same for NEON, but I'm happy for that to happen in a different patch.

1475–1492

There should be a fallback to the comma-separated form if the registers are not consecutive, for example when the register wraps as in:

ld4b  { z29.b, z30.b, z31.b, z0.b }, p0/z, [x0, x0]

This should remain a comma-separated list.

It would also be good to have a test for this, in case it doesn't exist yet.

llvm/test/CodeGen/AArch64/sve-merging-stores.ll

1 ↗

(On Diff #467739)

This test doesn't need changing at all now that it remains a comma-separated vector list.

llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s

2574

These whitespace changes should not be here.

[CarolineConcatto]

-Remove wrap-around sve vector list from using range

[CarolineConcatto]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1475–1492

I have added at least one test for st3/st4 and ld3/l4

llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s

2574

I removed the white spaces, but it was added by update_mca_test_checks.py.

[sdesmalen]

Nice one, thanks @CarolineConcatto

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   // If it's a D-reg, we need to promote it to the equivalent Q-reg before
   // printing (otherwise getRegisterName fails).
   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
     const MCRegisterClass &FPR128RC =
         MRI.getRegClass(AArch64::FPR128RegClassID);
     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
   }
 
+  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) && NumRegs > 1 &&
+      // Do not print the range when the last register is lower than the first.
+      // Because it is a wrap-around register.
+      Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
+    printRegName(O, Reg);
+    O << LayoutSuffix;
+    if (NumRegs > 1) {
+      // Set of two sve registers should be separated by ','
+      StringRef split_char = NumRegs == 2 ? ", " : " - ";
+      O << split_char;
+      printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
+      O << LayoutSuffix;
+    }
+  } else {
     for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
+      // wrap-around sve register
       if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
         printRegName(O, Reg);
       else
         printRegName(O, Reg, AArch64::vreg);
       O << LayoutSuffix;
-
       if (i + 1 != NumRegs)
         O << ", ";
     }
-
+  }
   O << " }";
 }
 
 void
 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
                                                    unsigned OpNum,
                                                    const MCSubtargetInfo &STI,
                                                    raw_ostream &O) {

llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+sve | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 ; Make sure callers set up the arguments correctly - tests AArch64ISelLowering::LowerCALL
 
 define float @foo1(double* %x0, double* %x1, double* %x2) nounwind {
 ; CHECK-LABEL: foo1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    fmov s0, #1.00000000
-; CHECK-NEXT:    ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
-; CHECK-NEXT:    ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
+; CHECK-NEXT:    ld4d { z1.d - z4.d }, p0/z, [x0]
+; CHECK-NEXT:    ld4d { z16.d - z19.d }, p0/z, [x1]
 ; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x2]
 ; CHECK-NEXT:    mov x0, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z16.d }, p0, [sp]
 ; CHECK-NEXT:    st1d { z17.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1d { z18.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    st1d { z19.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    bl callee1

 define float @foo2(double* %x0, double* %x1) nounwind {
 ; CHECK-LABEL: foo2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    add x9, sp, #16
-; CHECK-NEXT:    ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
-; CHECK-NEXT:    ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
+; CHECK-NEXT:    ld4d { z1.d - z4.d }, p0/z, [x0]
+; CHECK-NEXT:    ld4d { z16.d - z19.d }, p0/z, [x1]
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    add x8, sp, #16
 ; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    mov w1, #1
 ; CHECK-NEXT:    mov w2, #2
 ; CHECK-NEXT:    st1d { z16.d }, p0, [x9]
 ; CHECK-NEXT:    add x9, sp, #16

 
 define float @foo3(double* %x0, double* %x1, double* %x2) nounwind {
 ; CHECK-LABEL: foo3:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-3
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    fmov s0, #1.00000000
-; CHECK-NEXT:    ld4d { z2.d, z3.d, z4.d, z5.d }, p0/z, [x0]
-; CHECK-NEXT:    ld3d { z16.d, z17.d, z18.d }, p0/z, [x1]
+; CHECK-NEXT:    ld4d { z2.d - z5.d }, p0/z, [x0]
+; CHECK-NEXT:    ld3d { z16.d - z18.d }, p0/z, [x1]
 ; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x2]
 ; CHECK-NEXT:    fmov s1, #2.00000000
 ; CHECK-NEXT:    mov x0, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z16.d }, p0, [sp]
 ; CHECK-NEXT:    st1d { z17.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1d { z18.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    bl callee3

 entry:
   %ptr1.bc = bitcast double * %ptr1 to <vscale x 8 x double> *
   store volatile <vscale x 8 x double> %x2, <vscale x 8 x double>* %ptr1.bc
   %ptr2.bc = bitcast double * %ptr2 to <vscale x 6 x double> *
   store volatile <vscale x 6 x double> %x3, <vscale x 6 x double>* %ptr2.bc
   ret double %x0
 }
 
-; Use AAVPCS, SVE register in z0-z7 used
+; Use AAVPCS, SVE register in z0 - z7 used
 
 define void @aavpcs1(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, <vscale x 4 x i32> %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, i32 * %ptr) nounwind {
 ; CHECK-LABEL: aavpcs1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldp x8, x9, [sp]
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ld1w { z3.s }, p0/z, [x8]
 ; CHECK-NEXT:    ld1w { z24.s }, p0/z, [x7]
entry:
   store volatile <vscale x 4 x i32> %s12, <vscale x 4 x i32>* %ptr1.bc
   store volatile <vscale x 4 x i32> %s13, <vscale x 4 x i32>* %ptr1.bc
   store volatile <vscale x 4 x i32> %s14, <vscale x 4 x i32>* %ptr1.bc
   store volatile <vscale x 4 x i32> %s15, <vscale x 4 x i32>* %ptr1.bc
   store volatile <vscale x 4 x i32> %s16, <vscale x 4 x i32>* %ptr1.bc
   ret void
 }
 
-; Use AAVPCS, SVE register in z0-z7 used
+; Use AAVPCS, SVE register in z0 - z7 used
 
 define void @aavpcs2(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, <vscale x 4 x float> %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12,<vscale x 4 x float> %s13,<vscale x 4 x float> %s14,<vscale x 4 x float> %s15,<vscale x 4 x float> %s16,float * %ptr) nounwind {
 ; CHECK-LABEL: aavpcs2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldp x8, x9, [sp]
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x7]
entry:
   store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
   ret void
 }
 
-; Use AAVPCS, no SVE register in z0-z7 used (floats occupy z0-z7) but predicate arg is used
+; Use AAVPCS, no SVE register in z0 - z7 used (floats occupy z0 - z7) but predicate arg is used
 
 define void @aavpcs3(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, <vscale x 16 x i1> %p0, float * %ptr) nounwind {
 ; CHECK-LABEL: aavpcs3:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldr x8, [sp]
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x7]
entry:
   store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
   store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
   ret void
 }
 
-; use AAVPCS, SVE register in z0-z7 used (i32s dont occupy z0-z7)
+; use AAVPCS, SVE register in z0 - z7 used (i32s dont occupy z0 - z7)
 
 define void @aavpcs4(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, i32 %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, <vscale x 4 x i32> %s17, i32 * %ptr) nounwind {
 ; CHECK-LABEL: aavpcs4:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldr x8, [sp]
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ldr x9, [sp, #16]
 ; CHECK-NEXT:    ld1w { z24.s }, p0/z, [x8]

llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll

; CHECK-NEXT:    ret
   ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 ; ld3b
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #3
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #-24
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -24
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_upper_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #21
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 21
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_not_multiple_of_3_01(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_not_multiple_of_3_01:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #4
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_not_multiple_of_3_02(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_not_multiple_of_3_02:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #5
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_outside_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_outside_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #-27
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -27
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8_outside_upper_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld3.nxv48i8_outside_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #24
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 24
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 ; ld3h
 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld3.nxv24i16(<vscale x 8 x i1> %Pg, <vscale x 8 x i16> *%addr) {
 ; CHECK-LABEL: ld3.nxv24i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #21
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x8]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 21
   %base_ptr = bitcast <vscale x 8 x i16>* %base to i16 *
   %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16(<vscale x 8 x i1> %Pg, i16 *%base_ptr)
   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res
 }
 
 define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld3.nxv24f16(<vscale x 8 x i1> %Pg, <vscale x 8 x half> *%addr) {
 ; CHECK-LABEL: ld3.nxv24f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #21
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x8]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 21
   %base_ptr = bitcast <vscale x 8 x half>* %base to half *
   %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16(<vscale x 8 x i1> %Pg, half *%base_ptr)
   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
 }
 
 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld3.nxv24bf16(<vscale x 8 x i1> %Pg, <vscale x 8 x bfloat> *%addr) #0 {
 ; CHECK-LABEL: ld3.nxv24bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-24
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x8]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %addr, i64 -24
   %base_ptr = bitcast <vscale x 8 x bfloat>* %base to bfloat *
   %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld3.sret.nxv8bf16(<vscale x 8 x i1> %Pg, bfloat *%base_ptr)
   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res
 }
 
 ; ld3w
 define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld3.nxv12i32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> *%addr) {
 ; CHECK-LABEL: ld3.nxv12i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #21
-; CHECK-NEXT:    ld3w { z0.s, z1.s, z2.s }, p0/z, [x8]
+; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 21
   %base_ptr = bitcast <vscale x 4 x i32>* %base to i32 *
   %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1> %Pg, i32 *%base_ptr)
   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res
 }
 
 define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld3.nxv12f32(<vscale x 4 x i1> %Pg, <vscale x 4 x float> *%addr) {
 ; CHECK-LABEL: ld3.nxv12f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-24
-; CHECK-NEXT:    ld3w { z0.s, z1.s, z2.s }, p0/z, [x8]
+; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 -24
   %base_ptr = bitcast <vscale x 4 x float>* %base to float *
   %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1> %Pg, float *%base_ptr)
   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
 }
 
 ; ld3d
 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld3.nxv6i64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> *%addr) {
 ; CHECK-LABEL: ld3.nxv6i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #21
-; CHECK-NEXT:    ld3d { z0.d, z1.d, z2.d }, p0/z, [x8]
+; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 21
   %base_ptr = bitcast <vscale x 2 x i64>* %base to i64 *
   %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1> %Pg, i64 *%base_ptr)
   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
 }
 
 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld3.nxv6f64(<vscale x 2 x i1> %Pg, <vscale x 2 x double> *%addr) {
 ; CHECK-LABEL: ld3.nxv6f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-24
-; CHECK-NEXT:    ld3d { z0.d, z1.d, z2.d }, p0/z, [x8]
+; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -24
   %base_ptr = bitcast <vscale x 2 x double>* %base to double *
   %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1> %Pg, double *%base_ptr)
   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 ; ; ld4b
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #4
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #-32
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -32
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_upper_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #28
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 28
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_not_multiple_of_4_01(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_not_multiple_of_4_01:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #5
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_not_multiple_of_4_02(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_not_multiple_of_4_02:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #6
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 6
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_not_multiple_of_4_03(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_not_multiple_of_4_03:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #7
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 7
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_outside_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_outside_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    mov x9, #-576
 ; CHECK-NEXT:    lsr x8, x8, #4
 ; CHECK-NEXT:    mul x8, x8, x9
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
 ; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #4) #9)
 ; xM = -9 * 2^6
 ; xP = RDVL * 2^-4
 ; xOFFSET = RDVL * 2^-4 * -9 * 2^6 = RDVL * -36
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -36
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8_outside_upper_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
 ; CHECK-LABEL: ld4.nxv64i8_outside_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    mov w9, #512
 ; CHECK-NEXT:    lsr x8, x8, #4
 ; CHECK-NEXT:    mul x8, x8, x9
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x8]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
 ; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #16) #2)
 ; xM = 2^9
 ; xP = RDVL * 2^-4
 ; xOFFSET = RDVL * 2^-4 * 2^9 = RDVL * 32
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 32
   %base_ptr = bitcast <vscale x 16 x i8>* %base to i8 *
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 ; ld4h
 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld4.nxv32i16(<vscale x 8 x i1> %Pg, <vscale x 8 x i16> *%addr) {
 ; CHECK-LABEL: ld4.nxv32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #8
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 8
   %base_ptr = bitcast <vscale x 8 x i16>* %base to i16 *
   %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16(<vscale x 8 x i1> %Pg, i16 *%base_ptr)
   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res
 }
 
 define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld4.nxv32f16(<vscale x 8 x i1> %Pg, <vscale x 8 x half> *%addr) {
 ; CHECK-LABEL: ld4.nxv32f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #28
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 28
   %base_ptr = bitcast <vscale x 8 x half>* %base to half *
   %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16(<vscale x 8 x i1> %Pg, half *%base_ptr)
   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
 }
 
 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld4.nxv32bf16(<vscale x 8 x i1> %Pg, <vscale x 8 x bfloat> *%addr) #0 {
 ; CHECK-LABEL: ld4.nxv32bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-32
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %addr, i64 -32
   %base_ptr = bitcast <vscale x 8 x bfloat>* %base to bfloat *
   %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld4.sret.nxv8bf16(<vscale x 8 x i1> %Pg, bfloat *%base_ptr)
   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res
 }
 
 ; ld4w
 define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld4.nxv16i32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> *%addr) {
 ; CHECK-LABEL: ld4.nxv16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #28
-; CHECK-NEXT:    ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8]
+; CHECK-NEXT:    ld4w { z0.s - z3.s }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 28
   %base_ptr = bitcast <vscale x 4 x i32>* %base to i32 *
   %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32(<vscale x 4 x i1> %Pg, i32 *%base_ptr)
   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res
 }
 
 define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld4.nxv16f32(<vscale x 4 x i1> %Pg, <vscale x 4 x float>* %addr) {
 ; CHECK-LABEL: ld4.nxv16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-32
-; CHECK-NEXT:    ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8]
+; CHECK-NEXT:    ld4w { z0.s - z3.s }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 -32
   %base_ptr = bitcast <vscale x 4 x float>* %base to float *
   %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld4.sret.nxv4f32(<vscale x 4 x i1> %Pg, float *%base_ptr)
   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
 }
 
 ; ld4d
 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld4.nxv8i64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> *%addr) {
 ; CHECK-LABEL: ld4.nxv8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #28
-; CHECK-NEXT:    ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8]
+; CHECK-NEXT:    ld4d { z0.d - z3.d }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 28
   %base_ptr = bitcast <vscale x 2 x i64>* %base to i64 *
   %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> %Pg, i64 *%base_ptr)
   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
 }
 
 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld4.nxv8f64(<vscale x 2 x i1> %Pg, <vscale x 2 x double> *%addr) {
 ; CHECK-LABEL: ld4.nxv8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    addvl x8, x0, #-32
-; CHECK-NEXT:    ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8]
+; CHECK-NEXT:    ld4d { z0.d - z3.d }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -32
   %base_ptr = bitcast <vscale x 2 x double>* %base to double *
   %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %Pg, double * %base_ptr)
   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1>, i8*)

llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=sve < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=sme < %s | FileCheck %s
 
 ; ld2b
 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
 ; CHECK-LABEL: ld2.nxv32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ld2b { z0.b, z1.b }, p0/z, [x0, x1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i8, i8 *  %addr, i64 %a
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%addr2)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 ; ld2h
 define { <vscale x 8 x i16>, <vscale x 8 x i16> } @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
; CHECK-NEXT:    ret
   %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64(<vscale x 2 x i1> %Pg, double *%addr2)
   ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 ; ld3b
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv48i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x1]
+; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [x0, x1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i8, i8 *  %addr, i64 %a
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%addr2)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 ; ld3h
 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv24i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i16, i16 *  %addr, i64 %a
   %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16(<vscale x 8 x i1> %Pg, i16 *%addr2)
   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res
 }
 
 define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld3.nxv24f16(<vscale x 8 x i1> %Pg, half *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv24f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr half, half *  %addr, i64 %a
   %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16(<vscale x 8 x i1> %Pg, half *%addr2)
   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
 }
 
 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld3.nxv24bf16(<vscale x 8 x i1> %Pg, bfloat *%addr, i64 %a) #0 {
 ; CHECK-LABEL: ld3.nxv24bf16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr bfloat, bfloat *  %addr, i64 %a
   %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld3.sret.nxv8bf16(<vscale x 8 x i1> %Pg, bfloat *%addr2)
   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res
 }
 
 ; ld3w
 define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld3.nxv12i32(<vscale x 4 x i1> %Pg, i32 *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv12i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i32, i32 *  %addr, i64 %a
   %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1> %Pg, i32 *%addr2)
   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res
 }
 
 define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld3.nxv12f32(<vscale x 4 x i1> %Pg, float *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv12f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr float, float *  %addr, i64 %a
   %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1> %Pg, float *%addr2)
   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
 }
 
 ; ld3d
 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv6i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i64, i64 *  %addr, i64 %a
   %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1> %Pg, i64 *%addr2)
   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
 }
 
 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld3.nxv6f64(<vscale x 2 x i1> %Pg, double *%addr, i64 %a) {
 ; CHECK-LABEL: ld3.nxv6f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr double, double *  %addr, i64 %a
   %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1> %Pg, double *%addr2)
   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 ; ld4b
 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv64i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x1]
+; CHECK-NEXT:    ld4b { z0.b - z3.b }, p0/z, [x0, x1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i8, i8 *  %addr, i64 %a
   %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, i8 *%addr2)
   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
 }
 
 ; ld4h
 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld4.nxv32i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv32i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i16, i16 *  %addr, i64 %a
   %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16(<vscale x 8 x i1> %Pg, i16 *%addr2)
   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res
 }
 
 define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld4.nxv32f16(<vscale x 8 x i1> %Pg, half *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv32f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr half, half *  %addr, i64 %a
   %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16(<vscale x 8 x i1> %Pg, half *%addr2)
   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
 }
 
 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld4.nxv32bf16(<vscale x 8 x i1> %Pg, bfloat *%addr, i64 %a) #0 {
 ; CHECK-LABEL: ld4.nxv32bf16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT:    ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr bfloat, bfloat *  %addr, i64 %a
   %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld4.sret.nxv8bf16(<vscale x 8 x i1> %Pg, bfloat *%addr2)
   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res
 }
 
 ; ld4w
 define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld4.nxv16i32(<vscale x 4 x i1> %Pg, i32 *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv16i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    ld4w { z0.s - z3.s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i32, i32 *  %addr, i64 %a
   %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32(<vscale x 4 x i1> %Pg, i32 *%addr2)
   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res
 }
 
 define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld4.nxv16f32(<vscale x 4 x i1> %Pg, float *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv16f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    ld4w { z0.s - z3.s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr float, float *  %addr, i64 %a
   %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld4.sret.nxv4f32(<vscale x 4 x i1> %Pg, float *%addr2)
   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
 }
 
 ; ld4d
 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld4.nxv8i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv8i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT:    ld4d { z0.d - z3.d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr i64, i64 *  %addr, i64 %a
   %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> %Pg, i64 *%addr2)
   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
 }
 
 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld4.nxv8f64(<vscale x 2 x i1> %Pg, double *%addr, i64 %a) {
 ; CHECK-LABEL: ld4.nxv8f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT:    ld4d { z0.d - z3.d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %addr2 = getelementptr double, double *  %addr, i64 %a
   %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %Pg, double *%addr2)
   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
 }
 
 declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1>, i8*)
 declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16(<vscale x 8 x i1>, i16*)

llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll

 ;
 
 define void @st3b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_valid_imm:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, #3, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_invalid_imm_not_multiple_of_3_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_01:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    rdvl x8, #4
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, x8]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_invalid_imm_not_multiple_of_3_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_02:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    rdvl x8, #5
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, x8]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_invalid_imm_out_of_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    rdvl x8, #-27
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, x8]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -27, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_invalid_imm_out_of_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    rdvl x8, #24
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, x8]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 24, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_valid_imm_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, #-24, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -24, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st3b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st3b_i8_valid_imm_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, #21, mul vl]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, #21, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 21, i64 0
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 ;
 ; ST3H
 ;
 
 define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
 ; CHECK-LABEL: st3h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0, #6, mul vl]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0, #6, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 6, i64 0
   call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i1> %pred,
                                           i16* %base)
   ret void
 }
 
 define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
 ; CHECK-LABEL: st3h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0, #9, mul vl]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0, #9, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 9, i64 0
   call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x i1> %pred,
                                           half* %base)
   ret void
 }
 
 ;
 ; ST3W
 ;
 
 define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
 ; CHECK-LABEL: st3w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0, #12, mul vl]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0, #12, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 12, i64 0
   call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i1> %pred,
                                           i32* %base)
   ret void
 }
 
 define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
 ; CHECK-LABEL: st3w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0, #15, mul vl]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0, #15, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 15, i64 0
   call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x i1> %pred,
                                           float* %base)
   ret void
 }
 
 ;
 ; ST3D
 ;
 
 define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
 ; CHECK-LABEL: st3d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0, #18, mul vl]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0, #18, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 18, i64 0
   call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i1> %pred,
                                           i64* %base)
   ret void
 }
 
 define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
 ; CHECK-LABEL: st3d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0, #-3, mul vl]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0, #-3, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -3, i64 0
   call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x i1> %pred,
                                           double* %base)
   ret void
 }
 
 ;
 ; ST4B
 ;
 
 define void @st4b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_valid_imm:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #4, mul vl]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, #4, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_invalid_imm_not_multiple_of_4_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_01:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    rdvl x8, #5
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x8]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_invalid_imm_not_multiple_of_4_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_02:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    rdvl x8, #6
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x8]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 6, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_invalid_imm_not_multiple_of_4_03(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_03:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    rdvl x8, #7
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x8]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 7, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_invalid_imm_out_of_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    mov x9, #-576
 ; CHECK-NEXT:    lsr x8, x8, #4
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    mul x8, x8, x9
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x8]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
 ; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #4) #9)
 ; xM = -9 * 2^6
 ; xP = RDVL * 2^-4
 ; xBASE = RDVL * 2^-4 * -9 * 2^6 = RDVL * -36
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -36, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,

 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    mov w9, #512
 ; CHECK-NEXT:    lsr x8, x8, #4
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    mul x8, x8, x9
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x8]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x8]
 ; CHECK-NEXT:    ret
 ; FIXME: optimize OFFSET computation so that xOFFSET = (shl (RDVL #16) #1)
 ; xM = 2^9
 ; xP = RDVL * 2^-4
 ; xOFFSET = RDVL * 2^-4 * 2^9 = RDVL * 32
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 32, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_valid_imm_lower_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #-32, mul vl]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, #-32, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -32, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 define void @st4b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
 ; CHECK-LABEL: st4b_i8_valid_imm_upper_bound:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #28, mul vl]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, #28, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 28, i64 0
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %base)
   ret void
 }
 
 ;
 ; ST4H
 ;
 
 define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
 ; CHECK-LABEL: st4h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #8, mul vl]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0, #8, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 8, i64 0
   call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i16> %v3,
                                           <vscale x 8 x i1> %pred,
                                           i16* %base)
   ret void
 }
 
 define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
 ; CHECK-LABEL: st4h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #12, mul vl]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0, #12, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 12, i64 0
   call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x half> %v3,
                                           <vscale x 8 x i1> %pred,
                                           half* %base)
   ret void
 }
 
 ;
 ; ST4W
 ;
 
 define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
 ; CHECK-LABEL: st4w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #16, mul vl]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0, #16, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 16, i64 0
   call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i32> %v3,
                                           <vscale x 4 x i1> %pred,
                                           i32* %base)
   ret void
 }
 
 define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
 ; CHECK-LABEL: st4w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #20, mul vl]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0, #20, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 20, i64 0
   call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x float> %v3,
                                           <vscale x 4 x i1> %pred,
                                           float* %base)
   ret void
 }
 
 ;
 ; ST4D
 ;
 
 define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
 ; CHECK-LABEL: st4d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #24, mul vl]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0, #24, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 24, i64 0
   call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i64> %v3,
                                           <vscale x 2 x i1> %pred,
                                           i64* %base)
   ret void
 }
 
 define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
 ; CHECK-LABEL: st4d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #28, mul vl]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0, #28, mul vl]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 28, i64 0
   call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x double> %v3,
                                           <vscale x 2 x i1> %pred,
                                           double* %base)

llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll

 ;
 
 define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
 ; CHECK-LABEL: st3b_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0, x1]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0, x1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i8, i8* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %1)
   ret void
 }
 
 ;
 ; ST3H
 ;
 
 define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
 ; CHECK-LABEL: st3h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i16, i16* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i1> %pred,
                                           i16* %1)
   ret void
 }
 
 define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
 ; CHECK-LABEL: st3h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr half, half* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x i1> %pred,
                                           half* %1)
   ret void
 }
 
 ;
 ; ST3W
 ;
 
 define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
 ; CHECK-LABEL: st3w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i32, i32* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i1> %pred,
                                           i32* %1)
   ret void
 }
 
 define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
 ; CHECK-LABEL: st3w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %1 = getelementptr float, float* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x i1> %pred,
                                           float* %1)
   ret void
 }
 
 ;
 ; ST3D
 ;
 
 define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
 ; CHECK-LABEL: st3d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i64, i64* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i1> %pred,
                                           i64* %1)
   ret void
 }
 
 define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
 ; CHECK-LABEL: st3d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %1 = getelementptr double, double* %addr, i64 %offset
   call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x i1> %pred,
                                           double* %1)
   ret void
 }
 
 ;
 ; ST4B
 ;
 
 define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
 ; CHECK-LABEL: st4b_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x1]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0, x1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i8, i8* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %1)
   ret void
 }
 
 ;
 ; ST4H
 ;
 
 define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
 ; CHECK-LABEL: st4h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i16, i16* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i16> %v3,
                                           <vscale x 8 x i1> %pred,
                                           i16* %1)
   ret void
 }
 
 define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
 ; CHECK-LABEL: st4h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT:    ret
   %1 = getelementptr half, half* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x half> %v3,
                                           <vscale x 8 x i1> %pred,
                                           half* %1)
   ret void
 }
 
 ;
 ; ST4W
 ;
 
 define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
 ; CHECK-LABEL: st4w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i32, i32* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i32> %v3,
                                           <vscale x 4 x i1> %pred,
                                           i32* %1)
   ret void
 }
 
 define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
 ; CHECK-LABEL: st4w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT:    ret
   %1 = getelementptr float, float* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x float> %v3,
                                           <vscale x 4 x i1> %pred,
                                           float* %1)
   ret void
 }
 
 ;
 ; ST4D
 ;
 
 define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
 ; CHECK-LABEL: st4d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %1 = getelementptr i64, i64* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i64> %v3,
                                           <vscale x 2 x i1> %pred,
                                           i64* %1)
   ret void
 }
 
 define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
 ; CHECK-LABEL: st4d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT:    ret
   %1 = getelementptr double, double* %addr, i64 %offset
   call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x double> %v3,
                                           <vscale x 2 x i1> %pred,
                                           double* %1)

llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

 ;
 
 define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: st3b_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3b { z0.b, z1.b, z2.b }, p0, [x0]
+; CHECK-NEXT:    st3b { z0.b - z2.b }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i1> %pred,
                                           i8* %addr)
   ret void
 }
 
 ;
 ; ST3H
 ;
 
 define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr) {
 ; CHECK-LABEL: st3h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i1> %pred,
                                           i16* %addr)
   ret void
 }
 
 define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr) {
 ; CHECK-LABEL: st3h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x i1> %pred,
                                           half* %addr)
   ret void
 }
 
 define void @st3h_bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x i1> %pred, bfloat* %addr) #0 {
 ; CHECK-LABEL: st3h_bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT:    st3h { z0.h - z2.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv8bf16(<vscale x 8 x bfloat> %v0,
                                           <vscale x 8 x bfloat> %v1,
                                           <vscale x 8 x bfloat> %v2,
                                           <vscale x 8 x i1> %pred,
                                           bfloat* %addr)
   ret void
 }
 
 ;
 ; ST3W
 ;
 
 define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr) {
 ; CHECK-LABEL: st3w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i1> %pred,
                                           i32* %addr)
   ret void
 }
 
 define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr) {
 ; CHECK-LABEL: st3w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3w { z0.s, z1.s, z2.s }, p0, [x0]
+; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x i1> %pred,
                                           float* %addr)
   ret void
 }
 
 ;
 ; ST3D
 ;
 
 define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr) {
 ; CHECK-LABEL: st3d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i1> %pred,
                                           i64* %addr)
   ret void
 }
 
 define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr) {
 ; CHECK-LABEL: st3d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x i1> %pred,
                                           double* %addr)
   ret void
 }
 
 define void @st3d_ptr(<vscale x 2 x i8*> %v0, <vscale x 2 x i8*> %v1, <vscale x 2 x i8*> %v2, <vscale x 2 x i1> %pred, i8** %addr) {
 ; CHECK-LABEL: st3d_ptr:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2 def $z0_z1_z2
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2 def $z0_z1_z2
-; CHECK-NEXT:    st3d { z0.d, z1.d, z2.d }, p0, [x0]
+; CHECK-NEXT:    st3d { z0.d - z2.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st3.nxv2p0i8(<vscale x 2 x i8*> %v0,
                                            <vscale x 2 x i8*> %v1,
                                            <vscale x 2 x i8*> %v2,
                                            <vscale x 2 x i1> %pred,
                                            i8** %addr)
   ret void
 }
 
 ;
 ; ST4B
 ;
 
 define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: st4b_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+; CHECK-NEXT:    st4b { z0.b - z3.b }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
                                           <vscale x 16 x i8> %v1,
                                           <vscale x 16 x i8> %v2,
                                           <vscale x 16 x i8> %v3,
                                           <vscale x 16 x i1> %pred,
                                           i8* %addr)
   ret void
 }
 
 ;
 ; ST4H
 ;
 
 define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr) {
 ; CHECK-LABEL: st4h_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
                                           <vscale x 8 x i16> %v1,
                                           <vscale x 8 x i16> %v2,
                                           <vscale x 8 x i16> %v3,
                                           <vscale x 8 x i1> %pred,
                                           i16* %addr)
   ret void
 }
 
 define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr) {
 ; CHECK-LABEL: st4h_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
                                           <vscale x 8 x half> %v1,
                                           <vscale x 8 x half> %v2,
                                           <vscale x 8 x half> %v3,
                                           <vscale x 8 x i1> %pred,
                                           half* %addr)
   ret void
 }
 
 define void @st4h_bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x i1> %pred, bfloat* %addr) #0 {
 ; CHECK-LABEL: st4h_bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT:    st4h { z0.h - z3.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv8bf16(<vscale x 8 x bfloat> %v0,
                                           <vscale x 8 x bfloat> %v1,
                                           <vscale x 8 x bfloat> %v2,
                                           <vscale x 8 x bfloat> %v3,
                                           <vscale x 8 x i1> %pred,
                                           bfloat* %addr)
   ret void
 }
 
 ;
 ; ST4W
 ;
 
 define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr) {
 ; CHECK-LABEL: st4w_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
                                           <vscale x 4 x i32> %v1,
                                           <vscale x 4 x i32> %v2,
                                           <vscale x 4 x i32> %v3,
                                           <vscale x 4 x i1> %pred,
                                           i32* %addr)
   ret void
 }
 
 define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr) {
 ; CHECK-LABEL: st4w_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+; CHECK-NEXT:    st4w { z0.s - z3.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
                                           <vscale x 4 x float> %v1,
                                           <vscale x 4 x float> %v2,
                                           <vscale x 4 x float> %v3,
                                           <vscale x 4 x i1> %pred,
                                           float* %addr)
   ret void
 }
 
 ;
 ; ST4D
 ;
 
 define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr) {
 ; CHECK-LABEL: st4d_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
                                           <vscale x 2 x i64> %v1,
                                           <vscale x 2 x i64> %v2,
                                           <vscale x 2 x i64> %v3,
                                           <vscale x 2 x i1> %pred,
                                           i64* %addr)
   ret void
 }
 
 define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr) {
 ; CHECK-LABEL: st4d_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
                                           <vscale x 2 x double> %v1,
                                           <vscale x 2 x double> %v2,
                                           <vscale x 2 x double> %v3,
                                           <vscale x 2 x i1> %pred,
                                           double* %addr)
   ret void
 }
 
 define void @st4d_ptr(<vscale x 2 x i8*> %v0, <vscale x 2 x i8*> %v1, <vscale x 2 x i8*> %v2, <vscale x 2 x i8*> %v3, <vscale x 2 x i1> %pred, i8** %addr) {
 ; CHECK-LABEL: st4d_ptr:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
 ; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
-; CHECK-NEXT:    st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+; CHECK-NEXT:    st4d { z0.d - z3.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.st4.nxv2p0i8(<vscale x 2 x i8*> %v0,
                                            <vscale x 2 x i8*> %v1,
                                            <vscale x 2 x i8*> %v2,
                                            <vscale x 2 x i8*> %v3,
                                            <vscale x 2 x i1> %pred,
                                            i8** %addr)
   ret void

llvm/test/CodeGen/AArch64/sve-ldN.mir

bb.0:
     ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [sp, #14, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3b { z0.b - z2.b }, p0/z, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3b { z0.b - z2.b }, p0/z, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3h { z0.h - z2.h }, p0/z, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3h { z0.h - z2.h }, p0/z, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3w { z0.s - z2.s }, p0/z, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3w { z0.s - z2.s }, p0/z, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3d { z0.d - z2.d }, p0/z, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3d { z0.d - z2.d }, p0/z, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4b { z0.b - z3.b }, p0/z, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4b { z0.b - z3.b }, p0/z, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4h { z0.h - z3.h }, p0/z, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4h { z0.h - z3.h }, p0/z, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4w { z0.s - z3.s }, p0/z, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4w { z0.s - z3.s }, p0/z, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4d { z0.d - z3.d }, p0/z, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4d { z0.d - z3.d }, p0/z, [sp, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #31
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #1
     ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16
     ; CHECK-OFFSET-NEXT: ret
 
     renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, -8
     renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, 7
     renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, -8
bb.0:
     ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [x8, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #2
     ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [x8, #14, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2
     ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #2
     ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8, #14, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3b { z0.b - z2.b }, p0/z, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3b { z0.b - z2.b }, p0/z, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3h { z0.h - z2.h }, p0/z, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3h { z0.h - z2.h }, p0/z, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3w { z0.s - z2.s }, p0/z, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3w { z0.s - z2.s }, p0/z, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3d { z0.d - z2.d }, p0/z, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: ld3d { z0.d - z2.d }, p0/z, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4b { z0.b - z3.b }, p0/z, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4b { z0.b - z3.b }, p0/z, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4h { z0.h - z3.h }, p0/z, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4h { z0.h - z3.h }, p0/z, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4w { z0.s - z3.s }, p0/z, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4w { z0.s - z3.s }, p0/z, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4d { z0.d - z3.d }, p0/z, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: ld4d { z0.d - z3.d }, p0/z, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #31
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #1
     ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16
     ; CHECK-OFFSET-NEXT: ret
 
     renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, -9
     renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, 8
     renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, -9

llvm/test/CodeGen/AArch64/sve-stN.mir

bb.0:
     ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [sp, #14, mul vl]
     ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [sp, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [sp, #14, mul vl]
-    ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [sp, #-24, mul vl]
-    ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [sp, #21, mul vl]
-    ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [sp, #28, mul vl]
-    ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [sp, #-32, mul vl]
-    ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st3b { z0.b - z2.b }, p0, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3b { z0.b - z2.b }, p0, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3h { z0.h - z2.h }, p0, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3h { z0.h - z2.h }, p0, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3w { z0.s - z2.s }, p0, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3w { z0.s - z2.s }, p0, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3d { z0.d - z2.d }, p0, [sp, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3d { z0.d - z2.d }, p0, [sp, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st4b { z0.b - z3.b }, p0, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4b { z0.b - z3.b }, p0, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4h { z0.h - z3.h }, p0, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4h { z0.h - z3.h }, p0, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4w { z0.s - z3.s }, p0, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4w { z0.s - z3.s }, p0, [sp, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4d { z0.d - z3.d }, p0, [sp, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4d { z0.d - z3.d }, p0, [sp, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #31
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #1
     ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16
     ; CHECK-OFFSET-NEXT: ret
 
     ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, -8
     ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, 7
     ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, -8
bb.0:
     ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [x8, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #2
     ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [x8, #14, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2
     ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [x8, #-16, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #2
     ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [x8, #14, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3b { z0.b - z2.b }, p0, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3b { z0.b - z2.b }, p0, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3h { z0.h - z2.h }, p0, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3h { z0.h - z2.h }, p0, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3w { z0.s - z2.s }, p0, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3w { z0.s - z2.s }, p0, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3
-    ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x8, #-24, mul vl]
+    ; CHECK-OFFSET-NEXT: st3d { z0.d - z2.d }, p0, [x8, #-24, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #3
-    ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x8, #21, mul vl]
+    ; CHECK-OFFSET-NEXT: st3d { z0.d - z2.d }, p0, [x8, #21, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4b { z0.b - z3.b }, p0, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4b { z0.b - z3.b }, p0, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4h { z0.h - z3.h }, p0, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4h { z0.h - z3.h }, p0, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4w { z0.s - z3.s }, p0, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4w { z0.s - z3.s }, p0, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4
-    ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x8, #-32, mul vl]
+    ; CHECK-OFFSET-NEXT: st4d { z0.d - z3.d }, p0, [x8, #-32, mul vl]
     ; CHECK-OFFSET-NEXT: addvl x8, sp, #4
-    ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x8, #28, mul vl]
+    ; CHECK-OFFSET-NEXT: st4d { z0.d - z3.d }, p0, [x8, #28, mul vl]
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #31
     ; CHECK-OFFSET-NEXT: addvl sp, sp, #1
     ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16
     ; CHECK-OFFSET-NEXT: ret
 
     ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, -9
     ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, 8
     ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, -9

llvm/test/MC/AArch64/SVE/ld3b.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
-// CHECK-INST: ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
+// CHECK-INST: ld3b    { z0.b - z2.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a440c000 <unknown>
 
 ld3b    { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
-// CHECK-INST: ld3b    { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
+// CHECK-INST: ld3b    { z5.b - z7.b }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0xce,0x50,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a450ce25 <unknown>
 
 ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
-// CHECK-INST: ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
+// CHECK-INST: ld3b    { z0.b - z2.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a440e000 <unknown>
 
 ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
-// CHECK-INST: ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3b    { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x48,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a448edb7 <unknown>
 
 ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
-// CHECK-INST: ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3b    { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a445f555 <unknown>

llvm/test/MC/AArch64/SVE/ld3d.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld3d    { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5c0c000 <unknown>
 
 ld3d    { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld3d    { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld3d    { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0xce,0xd0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5d0ce25 <unknown>
 
 ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
-// CHECK-INST: ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
+// CHECK-INST: ld3d    { z0.d - z2.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5c0e000 <unknown>
 
 ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
-// CHECK-INST: ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3d    { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5c8edb7 <unknown>
 
 ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
-// CHECK-INST: ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3d    { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5c5f555 <unknown>

llvm/test/MC/AArch64/SVE/ld3h.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld3h    { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4c0c000 <unknown>
 
 ld3h    { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld3h    { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld3h    { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0xce,0xd0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4d0ce25 <unknown>
 
 ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
-// CHECK-INST: ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
+// CHECK-INST: ld3h    { z0.h - z2.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4c0e000 <unknown>
 
 ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
-// CHECK-INST: ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3h    { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4c8edb7 <unknown>
 
 ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
-// CHECK-INST: ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3h    { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4c5f555 <unknown>
+
+ld3h    { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3h    { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x5e,0xf5,0xc5,0xa4]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: a4c5f55e <unknown>

llvm/test/MC/AArch64/SVE/ld3w.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld3w    { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a540c000 <unknown>
 
 ld3w    { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld3w    { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld3w    { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0xce,0x50,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a550ce25 <unknown>
 
 ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
-// CHECK-INST: ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
+// CHECK-INST: ld3w    { z0.s - z2.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a540e000 <unknown>
 
 ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
-// CHECK-INST: ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3w    { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x48,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a548edb7 <unknown>
 
 ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
-// CHECK-INST: ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3w    { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a545f555 <unknown>

llvm/test/MC/AArch64/SVE/ld4b.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
-// CHECK-INST: ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
+// CHECK-INST: ld4b    { z0.b - z3.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a460c000 <unknown>
 
 ld4b    { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
-// CHECK-INST: ld4b    { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
+// CHECK-INST: ld4b    { z5.b - z8.b }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0xce,0x70,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a470ce25 <unknown>
 
 ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
-// CHECK-INST: ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
+// CHECK-INST: ld4b    { z0.b - z3.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a460e000 <unknown>
 
 ld4b    { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
-// CHECK-INST: ld4b    { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
+// CHECK-INST: ld4b    { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a468edb7 <unknown>
 
 ld4b    { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
-// CHECK-INST: ld4b    { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
+// CHECK-INST: ld4b    { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a465f555 <unknown>

llvm/test/MC/AArch64/SVE/ld4d.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld4d    { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5e0c000 <unknown>
 
 ld4d    { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld4d    { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld4d    { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0xce,0xf0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5f0ce25 <unknown>
 
 ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
-// CHECK-INST: ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
+// CHECK-INST: ld4d    { z0.d - z3.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5e0e000 <unknown>
 
 ld4d    { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
-// CHECK-INST: ld4d    { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
+// CHECK-INST: ld4d    { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5e8edb7 <unknown>
 
 ld4d    { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
-// CHECK-INST: ld4d    { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
+// CHECK-INST: ld4d    { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a5e5f555 <unknown>

llvm/test/MC/AArch64/SVE/ld4h.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld4h    { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4e0c000 <unknown>
 
 ld4h    { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld4h    { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld4h    { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0xce,0xf0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4f0ce25 <unknown>
 
 ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
-// CHECK-INST: ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
+// CHECK-INST: ld4h    { z0.h - z3.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4e0e000 <unknown>
 
 ld4h    { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
-// CHECK-INST: ld4h    { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
+// CHECK-INST: ld4h    { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4e8edb7 <unknown>
 
 ld4h    { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
-// CHECK-INST: ld4h    { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
+// CHECK-INST: ld4h    { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a4e5f555 <unknown>
+
+ld4h    { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]
+// CHECK-INST: ld4h    { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x5f,0xf5,0xe5,0xa4]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: a4e5f55f <unknown>

llvm/test/MC/AArch64/SVE/ld4w.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld4w    { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a560c000 <unknown>
 
 ld4w    { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld4w    { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld4w    { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0xce,0x70,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a570ce25 <unknown>
 
 ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
-// CHECK-INST: ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
+// CHECK-INST: ld4w    { z0.s - z3.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a560e000 <unknown>
 
 ld4w    { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
-// CHECK-INST: ld4w    { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
+// CHECK-INST: ld4w    { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a568edb7 <unknown>
 
 ld4w    { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
-// CHECK-INST: ld4w    { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
+// CHECK-INST: ld4w    { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: a565f555 <unknown>

llvm/test/MC/AArch64/SVE/st3b.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st3b    { z0.b, z1.b, z2.b }, p0, [x0, x0]
-// CHECK-INST: st3b    { z0.b, z1.b, z2.b }, p0, [x0, x0]
+// CHECK-INST: st3b    { z0.b - z2.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4406000 <unknown>
 
 st3b    { z5.b, z6.b, z7.b }, p3, [x17, x16]
-// CHECK-INST: st3b    { z5.b, z6.b, z7.b }, p3, [x17, x16]
+// CHECK-INST: st3b    { z5.b - z7.b }, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x6e,0x50,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4506e25 <unknown>
 
 st3b    { z0.b, z1.b, z2.b }, p0, [x0]
-// CHECK-INST: st3b    { z0.b, z1.b, z2.b }, p0, [x0]
+// CHECK-INST: st3b    { z0.b - z2.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x50,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e450e000 <unknown>
 
 st3b    { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
-// CHECK-INST: st3b    { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3b    { z23.b - z25.b }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x58,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e458edb7 <unknown>
 
 st3b    { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
-// CHECK-INST: st3b    { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3b    { z21.b - z23.b }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x55,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e455f555 <unknown>

llvm/test/MC/AArch64/SVE/st3d.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st3d    { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
-// CHECK-INST: st3d    { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
+// CHECK-INST: st3d    { z0.d - z2.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5c06000 <unknown>
 
 st3d    { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
-// CHECK-INST: st3d    { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
+// CHECK-INST: st3d    { z5.d - z7.d }, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5d06e25 <unknown>
 
 st3d    { z0.d, z1.d, z2.d }, p0, [x0]
-// CHECK-INST: st3d    { z0.d, z1.d, z2.d }, p0, [x0]
+// CHECK-INST: st3d    { z0.d - z2.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5d0e000 <unknown>
 
 st3d    { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
-// CHECK-INST: st3d    { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3d    { z23.d - z25.d }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5d8edb7 <unknown>
 
 st3d    { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
-// CHECK-INST: st3d    { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3d    { z21.d - z23.d }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5d5f555 <unknown>

llvm/test/MC/AArch64/SVE/st3h.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st3h    { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
-// CHECK-INST: st3h    { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st3h    { z0.h - z2.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4c06000 <unknown>
 
 st3h    { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
-// CHECK-INST: st3h    { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
+// CHECK-INST: st3h    { z5.h - z7.h }, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4d06e25 <unknown>
 
 st3h    { z0.h, z1.h, z2.h }, p0, [x0]
-// CHECK-INST: st3h    { z0.h, z1.h, z2.h }, p0, [x0]
+// CHECK-INST: st3h    { z0.h - z2.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4d0e000 <unknown>
 
 st3h    { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
-// CHECK-INST: st3h    { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3h    { z23.h - z25.h }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4d8edb7 <unknown>
 
 st3h    { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
-// CHECK-INST: st3h    { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3h    { z21.h - z23.h }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4d5f555 <unknown>
+
+st3h    { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3h    { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x5f,0xf5,0xd5,0xe4]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e4d5f55f <unknown>

llvm/test/MC/AArch64/SVE/st3w.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st3w    { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
-// CHECK-INST: st3w    { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st3w    { z0.s - z2.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5406000 <unknown>
 
 st3w    { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
-// CHECK-INST: st3w    { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
+// CHECK-INST: st3w    { z5.s - z7.s }, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x6e,0x50,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5506e25 <unknown>
 
 st3w    { z0.s, z1.s, z2.s }, p0, [x0]
-// CHECK-INST: st3w    { z0.s, z1.s, z2.s }, p0, [x0]
+// CHECK-INST: st3w    { z0.s - z2.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x50,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e550e000 <unknown>
 
 st3w    { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
-// CHECK-INST: st3w    { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3w    { z23.s - z25.s }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x58,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e558edb7 <unknown>
 
 st3w    { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
-// CHECK-INST: st3w    { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3w    { z21.s - z23.s }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x55,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e555f555 <unknown>

llvm/test/MC/AArch64/SVE/st4b.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
-// CHECK-INST: st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
+// CHECK-INST: st4b    { z0.b - z3.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4606000 <unknown>
 
 st4b    { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
-// CHECK-INST: st4b    { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
+// CHECK-INST: st4b    { z5.b - z8.b }, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x6e,0x70,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4706e25 <unknown>
 
 st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
-// CHECK-INST: st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+// CHECK-INST: st4b    { z0.b - z3.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x70,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e470e000 <unknown>
 
 st4b    { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
-// CHECK-INST: st4b    { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4b    { z23.b - z26.b }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x78,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e478edb7 <unknown>
 
 st4b    { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
-// CHECK-INST: st4b    { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4b    { z21.b - z24.b }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x75,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e475f555 <unknown>

llvm/test/MC/AArch64/SVE/st4d.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
-// CHECK-INST: st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
+// CHECK-INST: st4d    { z0.d - z3.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5e06000 <unknown>
 
 st4d    { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
-// CHECK-INST: st4d    { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
+// CHECK-INST: st4d    { z5.d - z8.d }, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5f06e25 <unknown>
 
 st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
-// CHECK-INST: st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+// CHECK-INST: st4d    { z0.d - z3.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5f0e000 <unknown>
 
 st4d    { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
-// CHECK-INST: st4d    { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4d    { z23.d - z26.d }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5f8edb7 <unknown>
 
 st4d    { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
-// CHECK-INST: st4d    { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4d    { z21.d - z24.d }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5f5f555 <unknown>

llvm/test/MC/AArch64/SVE/st4h.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
-// CHECK-INST: st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
+// CHECK-INST: st4h    { z0.h - z3.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4e06000 <unknown>
 
 st4h    { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
-// CHECK-INST: st4h    { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
+// CHECK-INST: st4h    { z5.h - z8.h }, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4f06e25 <unknown>
 
 st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
-// CHECK-INST: st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+// CHECK-INST: st4h    { z0.h - z3.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4f0e000 <unknown>
 
 st4h    { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
-// CHECK-INST: st4h    { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4h    { z23.h - z26.h }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4f8edb7 <unknown>
 
 st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
-// CHECK-INST: st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4h    { z21.h - z24.h }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e4f5f555 <unknown>
+
+st4h    { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4h    { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x5d,0xf5,0xf5,0xe4]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e4f5f55d <unknown>

llvm/test/MC/AArch64/SVE/st4w.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
-// CHECK-INST: st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
+// CHECK-INST: st4w    { z0.s - z3.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5606000 <unknown>
 
 st4w    { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
-// CHECK-INST: st4w    { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
+// CHECK-INST: st4w    { z5.s - z8.s }, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x6e,0x70,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5706e25 <unknown>
 
 st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
-// CHECK-INST: st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+// CHECK-INST: st4w    { z0.s - z3.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x70,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e570e000 <unknown>
 
 st4w    { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
-// CHECK-INST: st4w    { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4w    { z23.s - z26.s }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x78,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e578edb7 <unknown>
 
 st4w    { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
-// CHECK-INST: st4w    { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4w    { z21.s - z24.s }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x75,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e575f555 <unknown>

llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s

 # CHECK-NEXT:  1      1     0.50                        addvl x0, x0, #-32
 # CHECK-NEXT:  1      1     0.50                        addvl x21, x21, #0
 # CHECK-NEXT:  1      1     0.50                        addvl x23, x8, #-1
 # CHECK-NEXT:  2      5     2.00                        adr z0.d, [z0.d, z0.d, lsl #1]
 # CHECK-NEXT:  2      5     2.00                        adr z0.d, [z0.d, z0.d, lsl #2]
 # CHECK-NEXT:  2      5     2.00                        adr z0.d, [z0.d, z0.d, lsl #3]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, sxtw #1]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, sxtw #2]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, sxtw #3]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, sxtw]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, uxtw #1]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, uxtw #2]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, uxtw #3]
 # CHECK-NEXT:  1      4     0.50                        adr z0.d, [z0.d, z0.d, uxtw]
 # CHECK-NEXT:  2      5     2.00                        adr z0.d, [z0.d, z0.d]
 # CHECK-NEXT:  2      5     2.00                        adr z0.s, [z0.s, z0.s, lsl #1]
 # CHECK-NEXT:  2      5     2.00                        adr z0.s, [z0.s, z0.s, lsl #2]

 # CHECK-NEXT:  3      15    4.50    *             U     ld2h  { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  3      15    4.50    *             U     ld2h  { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  3      15    4.50    *             U     ld2h  { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 # CHECK-NEXT:  3      12    1.50    *             U     ld2w  { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 # CHECK-NEXT:  2      11    1.00    *             U     ld2w  { z0.s, z1.s }, p0/z, [x0]
 # CHECK-NEXT:  2      11    1.00    *             U     ld2w  { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  2      11    1.00    *             U     ld2w  { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  3      12    1.50    *             U     ld2w  { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  4      12    2.00    *             U     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      12    2.00    *             U     ld3d  { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  4      12    2.00    *             U     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      12    2.00    *             U     ld3w  { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  5      12    2.50    *             U     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      12    2.50    *             U     ld4d  { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  5      12    2.50    *             U     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      12    2.50    *             U     ld4w  { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3b  { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  4      12    2.00    *             U     ld3d  { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3d  { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      12    2.00    *             U     ld3d  { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      15    6.50    *             U     ld3h  { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  4      12    2.00    *             U     ld3w  { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  3      11    1.50    *             U     ld3w  { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      12    2.00    *             U     ld3w  { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4b  { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  5      12    2.50    *             U     ld4d  { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4d  { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      12    2.50    *             U     ld4d  { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      15    8.50    *             U     ld4h  { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  5      12    2.50    *             U     ld4w  { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      11    2.00    *             U     ld4w  { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      12    2.50    *             U     ld4w  { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
 # CHECK-NEXT:  1      11    0.50    *             U     ldff1b  { z0.d }, p0/z, [x0, x0]
 # CHECK-NEXT:  1      16    2.00    *             U     ldff1b  { z0.d }, p0/z, [z0.d]
 # CHECK-NEXT:  1      11    0.50    *             U     ldff1b  { z0.h }, p0/z, [x0, x0]
 # CHECK-NEXT:  1      11    0.50    *             U     ldff1b  { z0.s }, p0/z, [x0, x0]
 # CHECK-NEXT:  1      23    4.00    *             U     ldff1b  { z0.s }, p0/z, [x0, z0.s, sxtw]
 # CHECK-NEXT:  1      23    4.00    *             U     ldff1b  { z0.s }, p0/z, [x0, z0.s, uxtw]
 # CHECK-NEXT:  1      19    4.00    *             U     ldff1b  { z0.s }, p0/z, [z0.s]
 # CHECK-NEXT:  1      20    2.00    *             U     ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]

 # CHECK-NEXT:  3      12    8.00           *      U     st2h  { z21.h, z22.h }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  3      12    8.00           *      U     st2h  { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  3      12    8.00           *      U     st2h  { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 # CHECK-NEXT:  2      11    2.00           *      U     st2w  { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 # CHECK-NEXT:  3      12    2.00           *      U     st2w  { z0.s, z1.s }, p0, [x0]
 # CHECK-NEXT:  3      12    2.00           *      U     st2w  { z21.s, z22.s }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  3      12    2.00           *      U     st2w  { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  2      11    2.00           *      U     st2w  { z5.s, z6.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z0.b, z1.b, z2.b }, p0, [x0, x0]
-# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z0.b, z1.b, z2.b }, p0, [x0]
-# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z5.b, z6.b, z7.b }, p3, [x17, x16]
-# CHECK-NEXT:  3      11    3.00           *      U     st3d  { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z0.d, z1.d, z2.d }, p0, [x0]
-# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      11    3.00           *      U     st3d  { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z0.h, z1.h, z2.h }, p0, [x0]
-# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  3      11    3.00           *      U     st3w  { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z0.s, z1.s, z2.s }, p0, [x0]
-# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      11    3.00           *      U     st3w  { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
-# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
-# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
-# CHECK-NEXT:  4      11    4.00           *      U     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
-# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  4      11    4.00           *      U     st4d  { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
-# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  4      11    4.00           *      U     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
-# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  4      11    4.00           *      U     st4w  { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      15    12.00          *      U     st3b  { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT:  3      11    3.00           *      U     st3d  { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  4      12    3.00           *      U     st3d  { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      11    3.00           *      U     st3d  { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  4      15    12.00          *      U     st3h  { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  3      11    3.00           *      U     st3w  { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  4      12    3.00           *      U     st3w  { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      11    3.00           *      U     st3w  { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      15    16.00          *      U     st4b  { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT:  4      11    4.00           *      U     st4d  { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  5      12    4.00           *      U     st4d  { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  4      11    4.00           *      U     st4d  { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  5      15    16.00          *      U     st4h  { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  4      11    4.00           *      U     st4w  { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  5      12    4.00           *      U     st4w  { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  4      11    4.00           *      U     st4w  { z5.s - z8.s }, p3, [x17, x16, lsl #2]
 # CHECK-NEXT:  1      11    1.00           *            stnt1b  { z0.b }, p0, [x0, x0]
 # CHECK-NEXT:  1      11    1.00           *            stnt1b  { z0.b }, p0, [x0]
 # CHECK-NEXT:  1      11    1.00           *            stnt1b  { z21.b }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  1      11    1.00           *            stnt1b  { z23.b }, p3, [x13, #-8, mul vl]
 # CHECK-NEXT:  1      11    1.00           *            stnt1d  { z0.d }, p0, [x0, x0, lsl #3]
 # CHECK-NEXT:  1      11    1.00           *            stnt1d  { z0.d }, p0, [x0]
 # CHECK-NEXT:  1      11    1.00           *            stnt1d  { z21.d }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  1      11    1.00           *            stnt1d  { z23.d }, p3, [x13, #-8, mul vl]

 # CHECK-NEXT:  -     4.50   4.50    -      -      -      -      -     ld2h  { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  -     4.50   4.50    -      -      -      -      -     ld2h  { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  -     4.50   4.50    -      -      -      -      -     ld2h  { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 # CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld2w  { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 # CHECK-NEXT:  -     1.00   1.00    -      -      -      -      -     ld2w  { z0.s, z1.s }, p0/z, [x0]
 # CHECK-NEXT:  -     1.00   1.00    -      -      -      -      -     ld2w  { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  -     1.00   1.00    -      -      -      -      -     ld2w  { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld2w  { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3d  { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3w  { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4d  { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4w  { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3b  { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3d  { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3d  { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3d  { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -      -      -      -     ld3h  { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3w  { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -     1.50   1.50    -      -      -      -      -     ld3w  { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld3w  { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4b  { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4d  { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4d  { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4d  { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -      -      -      -     ld4h  { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4w  { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -      -      -      -     ld4w  { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     2.50   2.50    -      -      -      -      -     ld4w  { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     ldff1b  { z0.d }, p0/z, [x0, x0]
 # CHECK-NEXT:  -     2.00   2.00    -      -     1.00    -      -     ldff1b  { z0.d }, p0/z, [z0.d]
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     ldff1b  { z0.h }, p0/z, [x0, x0]
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     ldff1b  { z0.s }, p0/z, [x0, x0]
 # CHECK-NEXT:  -     4.00   4.00   1.00    -     2.00    -      -     ldff1b  { z0.s }, p0/z, [x0, z0.s, sxtw]
 # CHECK-NEXT:  -     4.00   4.00   1.00    -     2.00    -      -     ldff1b  { z0.s }, p0/z, [x0, z0.s, uxtw]
 # CHECK-NEXT:  -     4.00   4.00    -      -     2.00    -      -     ldff1b  { z0.s }, p0/z, [z0.s]
 # CHECK-NEXT:  -     2.00   2.00   1.00    -     1.00    -      -     ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]

 # CHECK-NEXT:  -     4.50   4.50    -      -     8.00    -      -     st2h  { z21.h, z22.h }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  -     4.50   4.50    -      -     8.00    -      -     st2h  { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  -     4.50   4.50    -      -     8.00    -      -     st2h  { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 # CHECK-NEXT:  -     1.00   1.00    -      -     2.00    -      -     st2w  { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 # CHECK-NEXT:  -     1.50   1.50    -      -     2.00    -      -     st2w  { z0.s, z1.s }, p0, [x0]
 # CHECK-NEXT:  -     1.50   1.50    -      -     2.00    -      -     st2w  { z21.s, z22.s }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  -     1.50   1.50    -      -     2.00    -      -     st2w  { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  -     1.00   1.00    -      -     2.00    -      -     st2w  { z5.s, z6.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z0.b, z1.b, z2.b }, p0, [x0, x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z0.b, z1.b, z2.b }, p0, [x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z5.b, z6.b, z7.b }, p3, [x17, x16]
-# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3d  { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z0.d, z1.d, z2.d }, p0, [x0]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3d  { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z0.h, z1.h, z2.h }, p0, [x0]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3w  { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z0.s, z1.s, z2.s }, p0, [x0]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3w  { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
-# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4d  { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4w  { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3b  { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3d  { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3d  { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3d  { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     6.50   6.50    -      -     12.00   -      -     st3h  { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3w  { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -     3.00    -      -     st3w  { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -     1.50   1.50    -      -     3.00    -      -     st3w  { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4b  { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4d  { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4d  { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4d  { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     8.50   8.50    -      -     16.00   -      -     st4h  { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4w  { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -     2.50   2.50    -      -     4.00    -      -     st4w  { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -     2.00   2.00    -      -     4.00    -      -     st4w  { z5.s - z8.s }, p3, [x17, x16, lsl #2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1b  { z0.b }, p0, [x0, x0]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1b  { z0.b }, p0, [x0]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1b  { z21.b }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1b  { z23.b }, p3, [x13, #-8, mul vl]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1d  { z0.d }, p0, [x0, x0, lsl #3]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1d  { z0.d }, p0, [x0]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1d  { z21.d }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stnt1d  { z23.d }, p3, [x13, #-8, mul vl]

llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

 # CHECK-NEXT:  2      8     0.50    *             U     ld2h  { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  2      8     0.50    *             U     ld2h  { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  2      9     0.50    *             U     ld2h  { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 # CHECK-NEXT:  2      9     0.50    *             U     ld2w  { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 # CHECK-NEXT:  2      8     0.50    *             U     ld2w  { z0.s, z1.s }, p0/z, [x0]
 # CHECK-NEXT:  2      8     0.50    *             U     ld2w  { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  2      8     0.50    *             U     ld2w  { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  2      9     0.50    *             U     ld2w  { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z0.b, z1.b, z2.b }, p0/z, [x0]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3b  { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z0.d, z1.d, z2.d }, p0/z, [x0]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3d  { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z0.h, z1.h, z2.h }, p0/z, [x0]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3h  { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z0.s, z1.s, z2.s }, p0/z, [x0]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  3      10    0.67    *             U     ld3w  { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4b  { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4d  { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4h  { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  6      10    1.00    *             U     ld4w  { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3b  { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3b  { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3b  { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3d  { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3d  { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3d  { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3h  { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3h  { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3h  { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3w  { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  2      9     0.50    *             U     ld3w  { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  3      10    0.67    *             U     ld3w  { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4b  { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4b  { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4b  { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4d  { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4d  { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4d  { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4h  { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4h  { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4h  { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4w  { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  4      9     1.00    *             U     ld4w  { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  6      10    1.00    *             U     ld4w  { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
 # CHECK-NEXT:  2      6     0.50    *             U     ldff1b  { z0.d }, p0/z, [x0, x0]
 # CHECK-NEXT:  4      9     1.00    *             U     ldff1b  { z0.d }, p0/z, [z0.d]
 # CHECK-NEXT:  2      6     0.50    *             U     ldff1b  { z0.h }, p0/z, [x0, x0]
 # CHECK-NEXT:  2      6     0.50    *             U     ldff1b  { z0.s }, p0/z, [x0, x0]
 # CHECK-NEXT:  2      9     0.50    *             U     ldff1b  { z0.s }, p0/z, [x0, z0.s, sxtw]
 # CHECK-NEXT:  2      9     0.50    *             U     ldff1b  { z0.s }, p0/z, [x0, z0.s, uxtw]
 # CHECK-NEXT:  2      9     0.50    *             U     ldff1b  { z0.s }, p0/z, [z0.s]
 # CHECK-NEXT:  4      9     1.00    *             U     ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]

 # CHECK-NEXT:  2      4     0.50           *      U     st2h  { z21.h, z22.h }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  2      4     0.50           *      U     st2h  { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  3      4     0.50           *      U     st2h  { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 # CHECK-NEXT:  2      4     0.50           *      U     st2w  { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 # CHECK-NEXT:  2      4     0.50           *      U     st2w  { z0.s, z1.s }, p0, [x0]
 # CHECK-NEXT:  2      4     0.50           *      U     st2w  { z21.s, z22.s }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  2      4     0.50           *      U     st2w  { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  2      4     0.50           *      U     st2w  { z5.s, z6.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  15     7     2.50           *      U     st3b  { z0.b, z1.b, z2.b }, p0, [x0, x0]
-# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z0.b, z1.b, z2.b }, p0, [x0]
-# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  15     7     2.50           *      U     st3b  { z5.b, z6.b, z7.b }, p3, [x17, x16]
-# CHECK-NEXT:  15     7     2.50           *      U     st3d  { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z0.d, z1.d, z2.d }, p0, [x0]
-# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  15     7     2.50           *      U     st3d  { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  15     7     2.50           *      U     st3h  { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z0.h, z1.h, z2.h }, p0, [x0]
-# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  15     7     2.50           *      U     st3h  { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  15     7     2.50           *      U     st3w  { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z0.s, z1.s, z2.s }, p0, [x0]
-# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  15     7     2.50           *      U     st3w  { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  27     11    4.50           *      U     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
-# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
-# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  27     11    4.50           *      U     st4b  { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
-# CHECK-NEXT:  27     11    4.50           *      U     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
-# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  27     11    4.50           *      U     st4d  { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  27     11    4.50           *      U     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
-# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  27     11    4.50           *      U     st4h  { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  27     11    4.50           *      U     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
-# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  27     11    4.50           *      U     st4w  { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  15     7     2.50           *      U     st3b  { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  10     7     2.50           *      U     st3b  { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  15     7     2.50           *      U     st3b  { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT:  15     7     2.50           *      U     st3d  { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  10     7     2.50           *      U     st3d  { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  15     7     2.50           *      U     st3d  { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  15     7     2.50           *      U     st3h  { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  10     7     2.50           *      U     st3h  { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  15     7     2.50           *      U     st3h  { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  15     7     2.50           *      U     st3w  { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  10     7     2.50           *      U     st3w  { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  15     7     2.50           *      U     st3w  { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  27     11    4.50           *      U     st4b  { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  18     11    4.50           *      U     st4b  { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  27     11    4.50           *      U     st4b  { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT:  27     11    4.50           *      U     st4d  { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  18     11    4.50           *      U     st4d  { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  27     11    4.50           *      U     st4d  { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  27     11    4.50           *      U     st4h  { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  18     11    4.50           *      U     st4h  { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  27     11    4.50           *      U     st4h  { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  27     11    4.50           *      U     st4w  { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  18     11    4.50           *      U     st4w  { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  27     11    4.50           *      U     st4w  { z5.s - z8.s }, p3, [x17, x16, lsl #2]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z0.b }, p0, [x0, x0]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z0.b }, p0, [x0]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z0.d }, p0, [z1.d]
 # CHECK-NEXT:  4      4     1.00           *            stnt1b  { z0.s }, p0, [z1.s]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z21.b }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z23.b }, p3, [x13, #-8, mul vl]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z31.d }, p7, [z31.d, x0]
 # CHECK-NEXT:  2      2     0.50           *            stnt1b  { z31.d }, p7, [z31.d]

 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2w { z0.s, z1.s }, p0/z, [x0]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z0.b, z1.b, z2.b }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z0.d, z1.d, z2.d }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z0.s, z1.s, z2.s }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3b { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3b { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     0.50   0.50   ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4b { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4b { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -     1.00   1.00   1.00   1.00   ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     0.50   0.50    -      -     ldff1b { z0.d }, p0/z, [x0, x0]
 # CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ldff1b { z0.d }, p0/z, [z0.d]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     0.50   0.50    -      -     ldff1b { z0.h }, p0/z, [x0, x0]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     0.50   0.50    -      -     ldff1b { z0.s }, p0/z, [x0, x0]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
 # CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -      -      -     0.50   0.50   ldff1b { z0.s }, p0/z, [z0.s]
 # CHECK-NEXT:  -      -      -      -     0.67   0.67   0.67    -      -      -      -     1.00   1.00   ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]

 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -     0.50   0.50   0.50   0.50   st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2w { z0.s, z1.s }, p0, [x0]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3b { z0.b, z1.b, z2.b }, p0, [x0, x0]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z0.b, z1.b, z2.b }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3b { z5.b, z6.b, z7.b }, p3, [x17, x16]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z0.d, z1.d, z2.d }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z0.h, z1.h, z2.h }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z0.s, z1.s, z2.s }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3b { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3b { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -      -      -     2.50   2.50   st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     2.50   2.50    -      -     2.50   2.50   2.50   2.50   st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4b { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4b { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -      -      -     4.50   4.50   st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT:  -      -      -      -      -     4.50   4.50    -      -     4.50   4.50   4.50   4.50   st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z0.b }, p0, [x0, x0]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z0.b }, p0, [x0]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z0.d }, p0, [z1.d]
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -     1.00   1.00   stnt1b { z0.s }, p0, [z1.s]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z21.b }, p5, [x10, #7, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z23.b }, p3, [x13, #-8, mul vl]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z31.d }, p7, [z31.d, x0]
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -     0.50   0.50   stnt1b { z31.d }, p7, [z31.d]