Page MenuHomePhabricator

andreadb (Andrea Di Biagio)
User

Projects

User does not belong to any projects.

User Details

User Since
May 9 2013, 11:10 AM (310 w, 2 h)

Recent Activity

Tue, Apr 16

andreadb committed rG57cef5867295: [MCA] Moved the bottleneck analysis to its own file. NFCI (authored by andreadb).
[MCA] Moved the bottleneck analysis to its own file. NFCI
Tue, Apr 16, 11:02 PM

Thu, Apr 11

andreadb committed rG2050dff996a2: [MCA] Remove wrong comments from a test. NFC (authored by andreadb).
[MCA] Remove wrong comments from a test. NFC
Thu, Apr 11, 3:14 AM

Wed, Apr 10

andreadb accepted D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX..

Architecturally that read really does exist. Its not a false dependency. That read defines the upper bits of the result. The fact that AVX and SSE were different before this patch seems like a bug. It looks like with your proposed change they would still be different. That doesn't seem right.

Right. Sorry. The upper bits of the result are unmodified for the SSE variants. So yes, it was a bug before, and that read does exist in practice.

Wed, Apr 10, 4:59 AM · Restricted Project

Tue, Apr 9

andreadb added a comment to D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX..

Architecturally that read really does exist. Its not a false dependency. That read defines the upper bits of the result. The fact that AVX and SSE were different before this patch seems like a bug. It looks like with your proposed change they would still be different. That doesn't seem right.

Tue, Apr 9, 11:11 AM · Restricted Project
andreadb added a comment to D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX..

The reason why there is a regression is because this patch adds an extra input operand to the following instructions:

cvtsi2ssl  %ecx, %xmm0
cvtsi2sdl  %ecx, %xmm0
Tue, Apr 9, 9:48 AM · Restricted Project
andreadb added a comment to D60441: [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX..

Many of our instructions have both a _Int form used by intrinsics and a form used by other IR constructs.

Is there any documentation, a comment, a mail thread somewhere that explains why this is the way it is?
I.e. why are those _Int variants need to exist? (are they temporary, or to stay forever)

The mca(?) regression is troubling.

Tue, Apr 9, 8:56 AM · Restricted Project

Mon, Apr 8

andreadb committed rGf6a60f1f8031: [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI (authored by andreadb).
[llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI
Mon, Apr 8, 9:07 AM

Fri, Apr 5

andreadb accepted D60286: [x86] make 8-bit shl undesirable.

Looks good to me.

Fri, Apr 5, 3:24 AM · Restricted Project

Thu, Apr 4

andreadb accepted D60138: [X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand..

LGTM

Thu, Apr 4, 2:54 AM · Restricted Project

Wed, Apr 3

andreadb accepted D60185: [X86] Make the post machine scheduler macrofusion-aware..

Sounds reasonable to me.

Wed, Apr 3, 2:32 AM · Restricted Project

Fri, Mar 29

andreadb added a comment to D59997: [x86] allow movmsk with 2-element reductions.

llvm-mca numbers are quite accurate for btver2 (see below for the perf results):

Fri, Mar 29, 10:47 AM · Restricted Project
andreadb committed rGe074ac60b452: [MCA] Add an experimental MicroOpQueue stage. (authored by andreadb).
[MCA] Add an experimental MicroOpQueue stage.
Fri, Mar 29, 5:16 AM
andreadb added inline comments to D59928: [MCA] Add an experimental MicroOpQueue stage..
Fri, Mar 29, 4:20 AM · Restricted Project

Thu, Mar 28

andreadb updated the diff for D59928: [MCA] Add an experimental MicroOpQueue stage..

Address review comment.

Thu, Mar 28, 10:41 AM · Restricted Project
andreadb accepted D59689: [ScheduleDAG] Move `Topo` and `addEdge` to base class..
Thu, Mar 28, 9:57 AM · Restricted Project
andreadb added a comment to D59689: [ScheduleDAG] Move `Topo` and `addEdge` to base class..

LGTM

Thu, Mar 28, 9:57 AM · Restricted Project
andreadb accepted D59688: [X86] Make post-ra scheduling macrofusion-aware..

Thanks Clement.

Thu, Mar 28, 8:12 AM · Restricted Project
andreadb updated the diff for D59928: [MCA] Add an experimental MicroOpQueue stage..

Patch updated.

Thu, Mar 28, 8:05 AM · Restricted Project
andreadb added inline comments to D59928: [MCA] Add an experimental MicroOpQueue stage..
Thu, Mar 28, 7:52 AM · Restricted Project
andreadb created D59928: [MCA] Add an experimental MicroOpQueue stage..
Thu, Mar 28, 6:04 AM · Restricted Project
andreadb accepted D59872: [X86MacroFusion] Handle branch fusion (AMD CPUs)..
Thu, Mar 28, 5:13 AM · Restricted Project
andreadb added a comment to D59872: [X86MacroFusion] Handle branch fusion (AMD CPUs)..

Macro-op fusion on Intel processors is essentially a form branch fusion.
The only difference in practice is that - starting from Sandybridge - a few extra opcodes (mostly arithmetic) other than CMP/TEST can now be fuse with branches.
But conceptually, what AMD calls branch fusion is (a form of) macro-op fusion.
Using FeatureMacroFusion and FeatureBranchFusion to refer to the two different forms of macro-op fusion may be a bit misleading... But then, I am not good with names, so I am not sure I am able to suggest better names for those :-( .

Thu, Mar 28, 4:26 AM · Restricted Project

Wed, Mar 27

andreadb committed rGa194656fa245: [MCA] Fix -Wparentheses warning breaking the -Werror build. (authored by andreadb).
[MCA] Fix -Wparentheses warning breaking the -Werror build.
Wed, Mar 27, 9:24 AM
andreadb committed rG333a3264f472: [MCA][Pipeline] Don't visit stages in reverse order when calling method… (authored by andreadb).
[MCA][Pipeline] Don't visit stages in reverse order when calling method…
Wed, Mar 27, 8:43 AM

Tue, Mar 26

andreadb committed rGddce32e2f3a0: [MCA] Correctly update the UsedResourceGroups mask in the InstrBuilder. (authored by andreadb).
[MCA] Correctly update the UsedResourceGroups mask in the InstrBuilder.
Tue, Mar 26, 8:41 AM
andreadb added inline comments to D51160: Adjust MIScheduler to use ProcResource counts.
Tue, Mar 26, 5:00 AM · Restricted Project

Mon, Mar 25

andreadb added a comment to D59688: [X86] Make post-ra scheduling macrofusion-aware..

I plan to run some experiments today using your patch.

That's great, thanks.

Sorry, I was over optimistic about my other workload. I don't think I'll get a chance to get any perf numbers anytime soon.

That being said, I tried your patch on a few small examples on some different targets, and results seem good.
For example, before your patch I saw cases where the test/cmp was not emitted before the conditional branch. Your patch seems to fix that "issue" in most cases.

My only concern is that the macro-fusion mutator might be a bit too aggressive for AMD processors.
X86MacroFusion assumes that branch fusion can happen with ADD/SUB/INC/DEC too. That is okay for Intel processors, but not necessarily for

AMD processors where branch fusion (as far as I remember) is limited to CMP/TEST opcodes only.

That is consistent with what is stated in agner's microarchitecture, amd sog for piledriver.

Since your patch enables that mutator for targets with FeatureMacroFusion, it would be nice to get some feedback from somebody with access to an AMD target where macro fusion is enabled (Bobcat/Jaguar doesn't do branch fusion). Perhaps @lebedev.ri can run some quick tests on BdVer2?

It will, as usual, depend on whether this happens to affect the hotpath or not.
I did just run my rawspeed benchmark, and i'm not observing any notable non-noise perf changes.

Mon, Mar 25, 2:48 PM · Restricted Project
Herald added a project to D46662: [X86] condition branches folding for three-way conditional codes: Restricted Project.
In D46662#1246781, @xur wrote:

Hi Andrea,

Thanks for running this test, and the explanation. Can you run the tests
on Bulldozer/Ryzen? I don't have access to these platforms. If I need to do
this in subtarget way, it would be good to know the performance there.

CC'ing @lebedev.ri and @GGanesh.
They should be able to help you with running those tests on Bulldozer/Ryzen. Unfortunately, I don't have access to those machines.

I *think* this should be fine on bdver2, as per https://www.agner.org/optimize/microarchitecture.pdf:

19.15 Branches and loops
The branch prediction mechanism is described on page 34. There is no longer any
restriction on the number of branches per 16 bytes of code that can be predicted efficiently.
The misprediction penalty is quite high because of a long pipeline.

...
Bench: 4evencases.cc
...
Bench: 15evencases.cc
...
I wouldn't be surprised if instead this patch improves the performance of code on other big AMD cores like Bulldozer/ryzen.

Are these benchmarks available from somewhere? Can i run them

Mon, Mar 25, 2:43 PM · Restricted Project
andreadb updated subscribers of D59688: [X86] Make post-ra scheduling macrofusion-aware..

I plan to run some experiments today using your patch.

That's great, thanks.

Mon, Mar 25, 7:35 AM · Restricted Project

Fri, Mar 22

andreadb added a comment to D59688: [X86] Make post-ra scheduling macrofusion-aware..

Nice patch Clement!

I always wondered why on x86 we only enabled that mutator in the pre-ra scheduler.
In the past, I remember I did some quick experiments with enabling that mutator in the post-RA scheduler. I must admit that I wasn't particularly lucky wih the experiments (i.e. I couldn't find significant/promising improvements). But then - again - those were just quick experiments, and I didn't try it on many codebases. If you think you can share some numbers then that would be great.

Thanks Andrea.

Yes, that's essentially what the comment in X86.td says:

"This generally gives a nice performance increase on silvermont, with largely neutral behavior on other contemporary large core processors."

However, that was before the round of scheduling information fixes that Simon & I made based on llvm-exegesis. I wanted to give it another try after that, and from my first experiments it seems that it indeed makes sense to look at it again.
What I have done for now is run our (internal, sorry) main macrobenchmark with post-ra enabled. With the base code I see a consistent regression of 0.5% to 1% depending on metrics. With this patch I see a consistent improvement of 0.5% to 2%.

Fri, Mar 22, 6:25 AM · Restricted Project
andreadb added a comment to D59688: [X86] Make post-ra scheduling macrofusion-aware..

Nice patch Clement!

Fri, Mar 22, 4:58 AM · Restricted Project

Wed, Mar 20

andreadb committed rG624f5deff429: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI (authored by andreadb).
[X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI
Wed, Mar 20, 4:21 AM

Tue, Mar 19

andreadb updated the diff for D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.

Patch updated.

Tue, Mar 19, 2:40 PM · Restricted Project
andreadb added inline comments to D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Tue, Mar 19, 2:28 PM · Restricted Project

Mar 19 2019

andreadb added inline comments to D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Mar 19 2019, 1:26 PM · Restricted Project
andreadb added inline comments to D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Mar 19 2019, 12:52 PM · Restricted Project
andreadb added inline comments to D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Mar 19 2019, 12:29 PM · Restricted Project
andreadb updated the diff for D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.

Addressed review comments.

Mar 19 2019, 12:13 PM · Restricted Project
andreadb added inline comments to D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Mar 19 2019, 11:05 AM · Restricted Project
andreadb added a comment to D59391: [X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD.

I've been toying with the idea of using a pseudo for all SHLD/SHRD cases so we can make it easier to select between that and the expanded shift pattern depending on scheduler-model/register-pressure etc. instead of trying to make the decision in DAG with the feature bits. I don't know if this could be a first step towards this? @andreadb Any thoughts?

Mar 19 2019, 10:41 AM · Restricted Project
andreadb created D59547: [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI.
Mar 19 2019, 8:30 AM · Restricted Project

Mar 15 2019

andreadb added a reviewer for D59412: [X86] X86ISelLowering::combineSextInRegCmov(): also handle i8 CMOV's: RKSimon.
Mar 15 2019, 7:29 AM · Restricted Project
andreadb added a comment to D59035: [X86] Promote i8 CMOV's (PR40965).

why can't we simply widen the hands of select, like

define i16 @new(i1 %c) {

%ret = select i1 %c, i16 117, i16 -19
ret i16 %ret

}

https://rise4fun.com/Alive/cs8
?

Mar 15 2019, 7:20 AM · Restricted Project, Restricted Project
andreadb accepted D59035: [X86] Promote i8 CMOV's (PR40965).

Looks good to me.

Mar 15 2019, 5:22 AM · Restricted Project, Restricted Project

Mar 7 2019

andreadb accepted D59098: [llvm-mca] Emit a message when no bottlenecks are identified..

LGTM if you add flags -all-views=false -summary-view to that new test, and then you regenerate it with the update_mca script.

Mar 7 2019, 11:01 AM · Restricted Project
andreadb accepted D59058: [X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model.

LGTM

Mar 7 2019, 3:12 AM · Restricted Project
andreadb accepted D59077: [X86] Correct scheduler information for rotate by constant for Haswell, Broadwell, and Skylake..

LGTM

Mar 7 2019, 3:09 AM · Restricted Project

Mar 5 2019

andreadb accepted D58939: [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array..

LGTM. Very nice refactoring.

Mar 5 2019, 4:34 AM · Restricted Project
andreadb accepted D58938: [Subtarget] Create a separate SubtargetSubtargetKV struct for ProcDesc to remove fields from the stack tables that aren't needed for CPUs.

Looks good to me.

Mar 5 2019, 4:10 AM · Restricted Project
andreadb accepted D58937: [Subtarget] Move SubtargetFeatureKV/SubtargetInfoKV from SubtargetFeature.h to MCSubtargetInfo.h. Move all code that operates on ProcFeatures and ProcDesc arrays to MCSubtargetInfo..
Mar 5 2019, 3:21 AM · Restricted Project
andreadb added a comment to D58937: [Subtarget] Move SubtargetFeatureKV/SubtargetInfoKV from SubtargetFeature.h to MCSubtargetInfo.h. Move all code that operates on ProcFeatures and ProcDesc arrays to MCSubtargetInfo..

LGTM.

Mar 5 2019, 3:21 AM · Restricted Project

Mar 4 2019

andreadb committed rG3437142aadc9: [MCA] Remove unused methods. NFC (authored by andreadb).
[MCA] Remove unused methods. NFC
Mar 4 2019, 5:34 AM
andreadb committed rG9735d9011a70: [MCA] Correctly initialize struct SummaryView::BackPressureInfo. (authored by andreadb).
[MCA] Correctly initialize struct SummaryView::BackPressureInfo.
Mar 4 2019, 4:23 AM
andreadb committed rGbe3281a281e3: [MCA] Highlight kernel bottlenecks in the summary view. (authored by andreadb).
[MCA] Highlight kernel bottlenecks in the summary view.
Mar 4 2019, 3:52 AM

Mar 1 2019

andreadb accepted D58672: [X86] Avoid codegen changes when DBG_VALUE appears between lowered selects.

LGTM

Mar 1 2019, 10:16 AM · Restricted Project
andreadb added inline comments to D58672: [X86] Avoid codegen changes when DBG_VALUE appears between lowered selects.
Mar 1 2019, 3:06 AM · Restricted Project

Feb 28 2019

andreadb added inline comments to D58672: [X86] Avoid codegen changes when DBG_VALUE appears between lowered selects.
Feb 28 2019, 11:05 AM · Restricted Project
andreadb updated the diff for D58728: [MCA] Highlight kernel bottlenecks in the summary view..

Patch updated.

Feb 28 2019, 4:30 AM · Restricted Project
andreadb updated the summary of D58728: [MCA] Highlight kernel bottlenecks in the summary view..
Feb 28 2019, 3:46 AM · Restricted Project

Feb 27 2019

andreadb added a reviewer for D58728: [MCA] Highlight kernel bottlenecks in the summary view.: lebedev.ri.
Feb 27 2019, 11:20 AM · Restricted Project
andreadb created D58728: [MCA] Highlight kernel bottlenecks in the summary view..
Feb 27 2019, 10:59 AM · Restricted Project

Feb 26 2019

andreadb accepted D58687: [TableGen] Make OpcodeMappings sort comparator deterministic NFCI.

LGTM. Thanks!

Feb 26 2019, 10:38 AM · Restricted Project
andreadb committed rGc032e2ab7cda: [MCA] Always check if scheduler resources are unavailable when reporting… (authored by andreadb).
[MCA] Always check if scheduler resources are unavailable when reporting…
Feb 26 2019, 6:23 AM

Feb 25 2019

andreadb committed rG4a1e59a6e083: Fix a sign compare warning breaking the -Werror build. (authored by andreadb).
Fix a sign compare warning breaking the -Werror build.
Feb 25 2019, 11:34 AM

Feb 20 2019

andreadb committed rG51c1cc0757ff: [MCA][Scheduler] Correctly initialize field NumDispatchedToThePendingSet. (authored by andreadb).
[MCA][Scheduler] Correctly initialize field NumDispatchedToThePendingSet.
Feb 20 2019, 10:23 AM
andreadb committed rG3316eb5bb802: [MCA][Scheduler] Collect resource pressure and memory dependency bottlenecks. (authored by andreadb).
[MCA][Scheduler] Collect resource pressure and memory dependency bottlenecks.
Feb 20 2019, 10:02 AM
andreadb committed rGd882ad5e6efb: [MCA][ResourceManager] Add a table that maps processor resource indices to… (authored by andreadb).
[MCA][ResourceManager] Add a table that maps processor resource indices to…
Feb 20 2019, 6:53 AM

Feb 18 2019

andreadb committed rGc102e2a2275b: [MCA] Correctly update register definitions in the PRF after move elimination. (authored by andreadb).
[MCA] Correctly update register definitions in the PRF after move elimination.
Feb 18 2019, 6:16 AM
andreadb committed rG7a950ed587ba: [MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI (authored by andreadb).
[MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI
Feb 18 2019, 3:27 AM

Feb 15 2019

andreadb committed rG2187a4fa6aaa: [MCA] Improved code comment. NFC (authored by andreadb).
[MCA] Improved code comment. NFC
Feb 15 2019, 10:28 AM
andreadb committed rG5ad52e35a8e4: [MCA][LSUnit] Return the ID of the dependent memory operation from method… (authored by andreadb).
[MCA][LSUnit] Return the ID of the dependent memory operation from method…
Feb 15 2019, 10:08 AM

Feb 13 2019

andreadb committed rG245163ffd0ef: [MCA] Store a bitmask of used groups in the instruction descriptor. (authored by andreadb).
[MCA] Store a bitmask of used groups in the instruction descriptor.
Feb 13 2019, 6:56 AM
andreadb committed rG318f990aee79: [MCA][Scheduler] Use latency information to further classify busy instructions. (authored by andreadb).
[MCA][Scheduler] Use latency information to further classify busy instructions.
Feb 13 2019, 3:03 AM

Feb 12 2019

andreadb committed rGd30fff9a9049: [MCA] Improved debug prints. NFC (authored by andreadb).
[MCA] Improved debug prints. NFC
Feb 12 2019, 8:19 AM
andreadb updated the diff for D58066: [MCA][Scheduler] Use latency information to further classify busy instructions..

Addressed review comments.

Feb 12 2019, 4:51 AM · Restricted Project
andreadb added inline comments to D58066: [MCA][Scheduler] Use latency information to further classify busy instructions..
Feb 12 2019, 3:03 AM · Restricted Project

Feb 11 2019

andreadb created D58066: [MCA][Scheduler] Use latency information to further classify busy instructions..
Feb 11 2019, 10:52 AM · Restricted Project
andreadb committed rG23ff2aa47cfe: [MCA][Scheduler] Track resources that were found busy when issuing an… (authored by andreadb).
[MCA][Scheduler] Track resources that were found busy when issuing an…
Feb 11 2019, 9:56 AM
andreadb committed rG83e68854d545: [MCA] Return a mask of busy resources from method ResourceManager… (authored by andreadb).
[MCA] Return a mask of busy resources from method ResourceManager…
Feb 11 2019, 6:53 AM

Feb 6 2019

andreadb committed rG02974728dc45: [MCA] Speedup ResourceManager queries. NFCI (authored by andreadb).
[MCA] Speedup ResourceManager queries. NFCI
Feb 6 2019, 6:58 AM

Feb 5 2019

andreadb committed rG4bce783ee332: [MCA] Moved the logic that updates register dependencies from DispatchStage to… (authored by andreadb).
[MCA] Moved the logic that updates register dependencies from DispatchStage to…
Feb 5 2019, 6:12 AM
andreadb committed rG998a925e0e47: [MCA] Simplify the logic in method WriteState::addUser. NFCI (authored by andreadb).
[MCA] Simplify the logic in method WriteState::addUser. NFCI
Feb 5 2019, 3:37 AM

Feb 4 2019

andreadb committed rGedbf06a76771: [AsmPrinter] Remove hidden flag -print-schedule. (authored by andreadb).
[AsmPrinter] Remove hidden flag -print-schedule.
Feb 4 2019, 4:53 AM

Feb 1 2019

andreadb accepted D57300: [X86][BdVer2] Transfer delays from the integer to the floating point unit..

Thanks for running that experiment. There is clearly an 8-10cy delay.

Feb 1 2019, 2:52 AM · Restricted Project

Jan 29 2019

andreadb added a comment to D57300: [X86][BdVer2] Transfer delays from the integer to the floating point unit..

(I edited my previous comment. However, the system didn't send another email.)

Jan 29 2019, 9:38 AM · Restricted Project
andreadb added a comment to D57300: [X86][BdVer2] Transfer delays from the integer to the floating point unit..
      2e:       41 bf 00 00 00 00       mov    $0x0,%r15d
      34:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
      3a:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
....
    ea88:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
Jan 29 2019, 9:28 AM · Restricted Project
andreadb updated the diff for D57148: [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions..

Patch updated.
Addressed review comment.

Jan 29 2019, 7:52 AM
andreadb updated the diff for D57148: [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions..

Patch updated.

Jan 29 2019, 5:30 AM
andreadb added reviewers for D57375: X86AsmParser AVX-512: Return error instead of hitting assert: craig.topper, RKSimon.
Jan 29 2019, 3:37 AM · Restricted Project
andreadb added a comment to D57300: [X86][BdVer2] Transfer delays from the integer to the floating point unit..

I'm unable to find this number in the "AMD SOG for family 15h".
llvm-exegesis measures the latencies of these instructions as 2,
which matches the latencies specified in "AMD SOG for family 15h".

Jan 29 2019, 2:39 AM · Restricted Project

Jan 28 2019

andreadb updated the diff for D57244: [AsmPrinter] Remove hidden flag -print-schedule..

Patch updated.

Jan 28 2019, 5:47 AM · Restricted Project

Jan 25 2019

andreadb created D57244: [AsmPrinter] Remove hidden flag -print-schedule..
Jan 25 2019, 9:02 AM · Restricted Project

Jan 24 2019

andreadb created D57148: [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions..
Jan 24 2019, 5:07 AM

Jan 23 2019

andreadb updated the diff for D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit..

Thanks for the feedback.

Jan 23 2019, 4:52 AM
andreadb accepted D57090: [IR] Match intrinsic paramater by scalar/vectorwidth.

The patch looks good to me. However, I don't claim to be an expert of this area. So getting another pair of eyes on this could be useful.

Jan 23 2019, 4:45 AM

Jan 22 2019

andreadb added inline comments to D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit..
Jan 22 2019, 10:54 AM
andreadb added a reviewer for D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit.: mattd.
Jan 22 2019, 9:51 AM
andreadb created D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit..
Jan 22 2019, 7:41 AM

Jan 18 2019

andreadb updated the diff for D56922: [X86][BtVer2] Update the WriteLoad latency..

Removed FIXME.

Jan 18 2019, 10:42 AM
andreadb created D56922: [X86][BtVer2] Update the WriteLoad latency..
Jan 18 2019, 10:08 AM