andreadb (Andrea Di Biagio)
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May 9 2013, 11:10 AM (275 w, 4 d)

Recent Activity

Today

andreadb updated subscribers of D50839: [llvm] Make YAML serialization up to 2.5 times faster.

Right.
I was mainly concerned about the assert. Thanks for fixing it! :-)

Tue, Aug 21, 2:50 AM

Yesterday

andreadb added a comment to D50929: [llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC..

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

Mon, Aug 20, 9:09 AM
andreadb added a comment to D50839: [llvm] Make YAML serialization up to 2.5 times faster.

Hi Kirill,

Mon, Aug 20, 2:58 AM

Thu, Aug 16

andreadb updated the diff for D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.

Addressed review comments.

Thu, Aug 16, 11:12 AM
andreadb added a comment to D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.

Hi Matt,

Thu, Aug 16, 10:57 AM
andreadb created D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.
Thu, Aug 16, 10:04 AM

Wed, Aug 15

andreadb added a comment to D50745: [llvm-mca] Update the comments for the mca:::Stage class. NFC..

Hi Matt,

Wed, Aug 15, 4:10 AM

Tue, Aug 14

andreadb updated the diff for D50708: [Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates in CodeGenSchedule.cpp..

Thanks for the review Matt.

Tue, Aug 14, 11:13 AM
andreadb created D50708: [Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates in CodeGenSchedule.cpp..
Tue, Aug 14, 8:06 AM

Mon, Aug 13

andreadb accepted D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..

LGTM. Thanks!

Mon, Aug 13, 10:51 AM
andreadb added inline comments to D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..
Mon, Aug 13, 10:19 AM
andreadb added inline comments to D50566: [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class..
Mon, Aug 13, 4:03 AM
andreadb added a comment to D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..

Added Stage::Status type alias to clean up the return value for Stage::execute. The previous iteration of this patch used an Expected<bool>, which I find confusing. This change makes the code more readable.

Mon, Aug 13, 3:42 AM

Fri, Aug 10

andreadb created D50566: [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class..
Fri, Aug 10, 9:55 AM

Thu, Aug 9

andreadb accepted D50328: [X86][SSE] Combine (some) target shuffles with multiple uses.

The change to combinePMULDQ() should be committed as a separate patch (as suggested by you and David).

Thu, Aug 9, 3:21 AM

Wed, Aug 8

andreadb added inline comments to D50457: [MC][PredicateExpander] Extend the grammar to support simple switch and return statements..
Wed, Aug 8, 10:12 AM
andreadb created D50457: [MC][PredicateExpander] Extend the grammar to support simple switch and return statements..
Wed, Aug 8, 9:40 AM

Mon, Aug 6

andreadb created D50333: [Tablegen] In TargetSchedule.td: Remove unused argument `pfmCounters` from ProcResourceUnits..
Mon, Aug 6, 6:48 AM

Tue, Jul 31

andreadb updated the diff for D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Patch updated.

Tue, Jul 31, 3:43 AM

Mon, Jul 30

andreadb updated the diff for D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Patch rebased and updated.

Mon, Jul 30, 7:26 AM
andreadb accepted D49692: [llvm-mca][docs] Add instruction flow documentation. NFC..

Hi Matt,

Mon, Jul 30, 3:49 AM

Jul 21 2018

andreadb accepted D49614: [llvm-mca][docs] Add documentation for the statistic outputs from mca. NFC.

LGTM. Thanks!

Jul 21 2018, 12:49 AM

Jul 20 2018

andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:54 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:40 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:23 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 7:43 AM

Jul 19 2018

andreadb accepted D49527: [llvm-mca][docs] Describe the Timeline View. NFC.

Overall, it looks good to me.

As you wrote, the "VIEW DESCRIPTIONS" section should be improved.
Also, it should probably have a more informative/different name (not sure which one though... I am not good with names).

Jul 19 2018, 7:52 AM
andreadb updated the diff for D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

Patch updated.

Jul 19 2018, 5:48 AM
andreadb added reviewers for D49527: [llvm-mca][docs] Describe the Timeline View. NFC: gbedwell, courbet, filcab.

Overall, it looks good to me.

Jul 19 2018, 4:04 AM

Jul 18 2018

andreadb updated the diff for D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

Patch updated.

Jul 18 2018, 5:33 AM
andreadb added a comment to D49393: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers..

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

That is because on x86-64, a write to EAX implicitly zeroes the upper half or RAX. So, there is no false dependency with previous values of RAX, and - for the purpose of mca - EAX renames as RAX. See also the definition of X86CInstrAnalysis::clearsSuperRegisters() in the X86 Backend (X86/MCTargetDesc/X86MCTargetDesc.cpp).

Right, thank you, so this already works as-is; Should i keep the test?

Jul 18 2018, 4:15 AM
andreadb added a comment to D49393: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers..

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

Jul 18 2018, 4:00 AM
andreadb added a comment to D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

I think it makes sense to have a separate patch for checkInvalidRegOperand. I do like that idea in particular, it simplifies reading the tablegen sources.

Jul 18 2018, 3:11 AM

Jul 17 2018

andreadb created D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..
Jul 17 2018, 10:37 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 17 2018, 4:05 AM

Jul 16 2018

andreadb added a comment to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

@craig.topper do you think this approach is acceptable?

Jul 16 2018, 9:03 AM
andreadb added inline comments to D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers..
Jul 16 2018, 8:10 AM
andreadb updated the diff for D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Patch updated.

Jul 16 2018, 5:05 AM

Jul 15 2018

andreadb added a comment to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Can you add a comment to the end of the btver sched profile, that X86MCInstrAnalysis::isDependencyBreaking()
is also responsible (as in, needs to be modified) in detection of dep-breaking patterns?

Jul 15 2018, 3:50 AM

Jul 14 2018

andreadb accepted D49329: [llvm-mca] Turn InstructionTables into a Stage..

Thanks for working on this!

Jul 14 2018, 3:17 PM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 14 2018, 5:42 AM
andreadb requested changes to D49329: [llvm-mca] Turn InstructionTables into a Stage..

Hi Matt,

Jul 14 2018, 5:23 AM

Jul 13 2018

andreadb created D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 13 2018, 11:20 AM

Jul 12 2018

andreadb accepted D49250: [llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage..

LGTM if you address the comments below.

Jul 12 2018, 2:58 PM
andreadb accepted D42044: X86: Utilize ZeroableElements for canWidenShuffleElements.
Jul 12 2018, 6:08 AM
andreadb added a comment to D42044: X86: Utilize ZeroableElements for canWidenShuffleElements.

Rebased and updated to fix potential issue if whole of V2 isn't zeros

Jul 12 2018, 6:08 AM
andreadb added inline comments to D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers..
Jul 12 2018, 3:49 AM
andreadb updated the diff for D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers..

Patch updated.

Jul 12 2018, 3:45 AM
andreadb accepted D49092: [X86][AVX] Use Zeroable mask to improve shuffle mask widening.

LGTM

Jul 12 2018, 3:24 AM
andreadb accepted D48672: [llvm-mca] Simplify eventing by adding an onEvent templated method..

Sorry. I completely forgot about this patch.

Jul 12 2018, 2:53 AM

Jul 11 2018

andreadb updated the summary of D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers..
Jul 11 2018, 9:27 AM
andreadb created D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers..
Jul 11 2018, 9:25 AM
andreadb created D49182: [X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions..
Jul 11 2018, 6:42 AM

Jul 4 2018

andreadb accepted D48876: [X86][BtVer2][MCA][NFC] Add CMPEQ one-idioms tests.

You can commit those tests to show that we don't correctly model dependency breaking packed compare instructions on BtVer2. However, I would remove the padd from the tests.

@andreadb do you feel like officially LGTM'ing this modulo the nit? :)

Jul 4 2018, 9:22 AM
andreadb added a comment to D48877: [X86][BtVer2][MCA] Recognize CMPEQ one-idioms.

Ok, well, i guess what i was trying to ask/understand is, is that already properly represented https://godbolt.org/g/9rYPYA, or not?

No, we don't properly model dependency breaking instructions yet - zero-idioms are making use of a special case of llvm-mca that assumes dependency breaking if no resources are used - IMO that's something that should be removed and we come up with a better way to model this.

Simon is right on this.
We still don't model dependency breaking instructions. There is already a plan to teach llvm-mca how to identify those instructions, and that is next on my TODO list. Once we have that system in place, we can remove the "zero-latency implies dependency-breaking" hack in llvm-mca.

This patch doesn't do the right thing. The timeline clearly shows how dependencies are not broken.

Ok, that is actually good, i was starting to question my [rudimentary] understanding of all this.

-Andrea

Then, back to square one, are D48876 tests of any use? :)

Jul 4 2018, 6:11 AM
andreadb added a comment to D48877: [X86][BtVer2][MCA] Recognize CMPEQ one-idioms.

Ok, well, i guess what i was trying to ask/understand is, is that already properly represented https://godbolt.org/g/9rYPYA, or not?

No, we don't properly model dependency breaking instructions yet - zero-idioms are making use of a special case of llvm-mca that assumes dependency breaking if no resources are used - IMO that's something that should be removed and we come up with a better way to model this.

Jul 4 2018, 5:25 AM
andreadb accepted D48691: [llvm-mca] Add a HardwareUnit and Context classes..

LGTM if you address the comments below.

Jul 4 2018, 2:46 AM

Jul 3 2018

andreadb added inline comments to D48691: [llvm-mca] Add a HardwareUnit and Context classes..
Jul 3 2018, 4:05 AM

Jul 2 2018

andreadb added a comment to D48691: [llvm-mca] Add a HardwareUnit and Context classes..

Hi Matt,

Jul 2 2018, 1:14 PM

Jun 27 2018

andreadb accepted D48576: [llvm-mca] Register listeners with stages; remove Pipeline dependency from Stage..

LGTM too.

Jun 27 2018, 2:55 AM

Jun 25 2018

andreadb added inline comments to D48496: [llvm-mca] Rename Backend to Pipeline. NFC..
Jun 25 2018, 4:21 AM
andreadb accepted D48496: [llvm-mca] Rename Backend to Pipeline. NFC..

Hi Matt,

Jun 25 2018, 3:20 AM

Jun 22 2018

andreadb accepted D46907: [llvm-mca] Introduce a sequential container of Stages.

Thanks for doing this!

Jun 22 2018, 2:56 AM

Jun 20 2018

andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

We have a quorum! LGTM

Jun 20 2018, 2:42 AM

Jun 19 2018

andreadb updated the diff for D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Patch updated.

Jun 19 2018, 11:32 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

So as it is now, writing a VR128X with XOP will zero [511:256] and [255:128], but writing VR256X with xop won't?

Jun 19 2018, 11:11 AM
andreadb added inline comments to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Jun 19 2018, 10:54 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Thanks Matt and Simon.

Jun 19 2018, 8:45 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Jun 19 2018, 4:32 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Jun 19 2018, 3:56 AM

Jun 18 2018

andreadb updated the diff for D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Patch updated.

Jun 18 2018, 7:34 AM
andreadb abandoned D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..

Abandoning this patch as there was no concrete plan to push this change Upstrea. It was mainly to help the review process for the RFC patches.

Jun 18 2018, 7:23 AM
andreadb accepted D48274: [X86][BtVer2] Flag AVX2+ scheduler classes as unsupported.

LGTM.

Jun 18 2018, 4:45 AM

Jun 15 2018

andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Does this cover writes to YMM clearing the upper half of ZMM registers?

Jun 15 2018, 10:51 AM
andreadb added inline comments to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Jun 15 2018, 10:44 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Should there be some AVX512VL tests? We don't have any scheduler that can test XOP instructions AFAICT (unless we want to cheat and use SandyBridge in its role as the generic model).

Jun 15 2018, 10:27 AM
andreadb created D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Jun 15 2018, 9:27 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Jun 15 2018, 7:53 AM
andreadb accepted D48209: [MCA] Add -summary-view option.

LGTM.

Jun 15 2018, 6:24 AM
andreadb accepted D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.

Well, I guess it doesn't hurt to have these new tests.
We already have tests for all the views and all the stats. But you are right, we don't have tests _only_ for those two flags.

Jun 15 2018, 6:05 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Given that Clement (and presumably Greg) are okay with this change, then I won't oppose it. Sorry for being pedantic.

Jun 15 2018, 5:51 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Jun 15 2018, 5:50 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Not sure what other reviewers think about this.
However, my opinion is that the summary view should never be optional in llvm-mca.
It is only a few lines, and it gives a nice overview of the run.

I mostly agree, but it does not hurt to have the option to disable it if you don;t want it to appear. Given that the patch is very small, I would be in favor of submitting.

Jun 15 2018, 4:30 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Jun 15 2018, 4:23 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Not sure what other reviewers think about this.
However, my opinion is that the summary view should never be optional in llvm-mca.
It is only a few lines, and it gives a nice overview of the run.

Jun 15 2018, 3:47 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Jun 15 2018, 3:44 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Jun 15 2018, 3:34 AM

Jun 13 2018

andreadb accepted D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

Thanks Matt!

Jun 13 2018, 4:10 PM
andreadb added a comment to D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

Hi Matt

Jun 13 2018, 8:27 AM

Jun 5 2018

andreadb accepted D47723: [CodeGen] print max throughput for 0-latency insts.

Thanks Sanjay.
It looks good to me.
I agree that this affects a lot of tests. However it looks like most of the diffs are for znver1, which apparently assigns an arbitrary 100cy latency , 1 uOp and no processor resource cycles to all microcoded instructions. So I am not particularly worried about it.
In the absence of extra/accurate schedule information, I think that computing an optimistic reciprocal throughput based on the number of opcodes and IssueWidth is the best that we can do.

Jun 5 2018, 2:22 PM
andreadb added a comment to D47723: [CodeGen] print max throughput for 0-latency insts.

Patch updated:
Please have a close look at the diffs because I'm not sure how to test all of these paths.

The cases that I see behaving as intended via tests are the recent variant scheduled "xorps %xmm0, %xmm0" and existing non-zero latency cases like:
; ZNVER1-SSE-NEXT: ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
(those cases are all unchanged, as I think is expected for this patch...but let me know if we want to treat that differently)

Jun 5 2018, 3:58 AM

Jun 4 2018

andreadb added a comment to D47723: [CodeGen] print max throughput for 0-latency insts.

Hey Sanjay,

Jun 4 2018, 9:24 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

Jun 4 2018, 7:49 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Address Simon's review comment.

Jun 4 2018, 7:22 AM
andreadb added inline comments to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
Jun 4 2018, 6:43 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated. This time with the correct diff...

Jun 4 2018, 4:01 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Address review comments.

Jun 4 2018, 3:51 AM

Jun 1 2018

andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated (sorry for the spam).

Jun 1 2018, 9:03 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

Jun 1 2018, 8:39 AM
andreadb accepted D47485: [X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003).

LGTM.
Thanks!

Jun 1 2018, 3:47 AM