andreadb (Andrea Di Biagio)
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May 9 2013, 11:10 AM (267 w, 3 d)

Recent Activity

Fri, Jun 22

andreadb accepted D46907: [llvm-mca] Introduce a sequential container of Stages.

Thanks for doing this!

Fri, Jun 22, 2:56 AM

Wed, Jun 20

andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

We have a quorum! LGTM

Wed, Jun 20, 2:42 AM

Tue, Jun 19

andreadb updated the diff for D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Patch updated.

Tue, Jun 19, 11:32 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

So as it is now, writing a VR128X with XOP will zero [511:256] and [255:128], but writing VR256X with xop won't?

Tue, Jun 19, 11:11 AM
andreadb added inline comments to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Tue, Jun 19, 10:54 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Thanks Matt and Simon.

Tue, Jun 19, 8:45 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Tue, Jun 19, 4:32 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Tue, Jun 19, 3:56 AM

Mon, Jun 18

andreadb updated the diff for D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Patch updated.

Mon, Jun 18, 7:34 AM
andreadb abandoned D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..

Abandoning this patch as there was no concrete plan to push this change Upstrea. It was mainly to help the review process for the RFC patches.

Mon, Jun 18, 7:23 AM
andreadb accepted D48274: [X86][BtVer2] Flag AVX2+ scheduler classes as unsupported.

LGTM.

Mon, Jun 18, 4:45 AM

Fri, Jun 15

andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Does this cover writes to YMM clearing the upper half of ZMM registers?

Fri, Jun 15, 10:51 AM
andreadb added inline comments to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Fri, Jun 15, 10:44 AM
andreadb added a comment to D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..

Should there be some AVX512VL tests? We don't have any scheduler that can test XOP instructions AFAICT (unless we want to cheat and use SandyBridge in its role as the generic model).

Fri, Jun 15, 10:27 AM
andreadb created D48225: [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register..
Fri, Jun 15, 9:27 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Fri, Jun 15, 7:53 AM
andreadb accepted D48209: [MCA] Add -summary-view option.

LGTM.

Fri, Jun 15, 6:24 AM
andreadb accepted D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.

Well, I guess it doesn't hurt to have these new tests.
We already have tests for all the views and all the stats. But you are right, we don't have tests _only_ for those two flags.

Fri, Jun 15, 6:05 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Given that Clement (and presumably Greg) are okay with this change, then I won't oppose it. Sorry for being pedantic.

Fri, Jun 15, 5:51 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Fri, Jun 15, 5:50 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Not sure what other reviewers think about this.
However, my opinion is that the summary view should never be optional in llvm-mca.
It is only a few lines, and it gives a nice overview of the run.

I mostly agree, but it does not hurt to have the option to disable it if you don;t want it to appear. Given that the patch is very small, I would be in favor of submitting.

Fri, Jun 15, 4:30 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Fri, Jun 15, 4:23 AM
andreadb added a comment to D48209: [MCA] Add -summary-view option.

Not sure what other reviewers think about this.
However, my opinion is that the summary view should never be optional in llvm-mca.
It is only a few lines, and it gives a nice overview of the run.

Fri, Jun 15, 3:47 AM
andreadb added inline comments to D48190: [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats.
Fri, Jun 15, 3:44 AM
andreadb added inline comments to D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity..
Fri, Jun 15, 3:34 AM

Wed, Jun 13

andreadb accepted D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

Thanks Matt!

Wed, Jun 13, 4:10 PM
andreadb added a comment to D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

Hi Matt

Wed, Jun 13, 8:27 AM

Tue, Jun 5

andreadb accepted D47723: [CodeGen] print max throughput for 0-latency insts.

Thanks Sanjay.
It looks good to me.
I agree that this affects a lot of tests. However it looks like most of the diffs are for znver1, which apparently assigns an arbitrary 100cy latency , 1 uOp and no processor resource cycles to all microcoded instructions. So I am not particularly worried about it.
In the absence of extra/accurate schedule information, I think that computing an optimistic reciprocal throughput based on the number of opcodes and IssueWidth is the best that we can do.

Tue, Jun 5, 2:22 PM
andreadb added a comment to D47723: [CodeGen] print max throughput for 0-latency insts.

Patch updated:
Please have a close look at the diffs because I'm not sure how to test all of these paths.

The cases that I see behaving as intended via tests are the recent variant scheduled "xorps %xmm0, %xmm0" and existing non-zero latency cases like:
; ZNVER1-SSE-NEXT: ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
(those cases are all unchanged, as I think is expected for this patch...but let me know if we want to treat that differently)

Tue, Jun 5, 3:58 AM

Mon, Jun 4

andreadb added a comment to D47723: [CodeGen] print max throughput for 0-latency insts.

Hey Sanjay,

Mon, Jun 4, 9:24 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

Mon, Jun 4, 7:49 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Address Simon's review comment.

Mon, Jun 4, 7:22 AM
andreadb added inline comments to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
Mon, Jun 4, 6:43 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated. This time with the correct diff...

Mon, Jun 4, 4:01 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Address review comments.

Mon, Jun 4, 3:51 AM

Fri, Jun 1

andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated (sorry for the spam).

Fri, Jun 1, 9:03 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

Fri, Jun 1, 8:39 AM
andreadb accepted D47485: [X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003).

LGTM.
Thanks!

Fri, Jun 1, 3:47 AM
andreadb added a comment to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Ping.

Fri, Jun 1, 3:02 AM

Wed, May 30

andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

Wed, May 30, 8:27 AM
andreadb created D47536: [MCSchedule] Add the ability to correctly compute the latency and throughput information for MCInst..
Wed, May 30, 8:08 AM

Sun, May 27

andreadb added inline comments to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
Sun, May 27, 12:41 PM

May 25 2018

andreadb updated the summary of D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
May 25 2018, 11:20 AM
andreadb added inline comments to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
May 25 2018, 11:14 AM
andreadb accepted D47244: [llvm-mca] Add the RetireStage. .

LGTM. Thanks!

May 25 2018, 10:35 AM
andreadb abandoned D46698: [RFC][llvm-mca][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Abandoning this patch in favor of D47374.

May 25 2018, 9:52 AM
andreadb updated the diff for D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated.

May 25 2018, 9:42 AM
andreadb added inline comments to D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
May 25 2018, 8:53 AM
andreadb created D47374: [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca..
May 25 2018, 8:14 AM
andreadb accepted D47244: [llvm-mca] Add the RetireStage. .
May 25 2018, 4:52 AM
andreadb added a comment to D47306: [llvm-mca] Register listeners with the Stage instances..

Hi Matt,

May 25 2018, 4:50 AM
andreadb added a comment to D47244: [llvm-mca] Add the RetireStage. .

I like Andrea's suggestion, and that we still maintain the RCU as a separate component.

This patch maintains that separation, but places ownership in the Backend. Additionally, the RegisterFile (renamed to RF instead of RAT) is also another simulated hardware component that is owned by the Backend. Any other MCA component that requires the use of such hardware abstraction will be passed pointers to those items during construction.

May 25 2018, 2:49 AM

May 24 2018

andreadb accepted D47321: [UpdateTestChecks] Improved update_mca_test_checks block analysis.

Nice! LGTM.

May 24 2018, 7:52 AM

May 23 2018

andreadb added a comment to D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

What I am trying to say is that the stage should only be responsible for the process (i.e. orchestrating the execution).
The logic that lives in Scheduler::cycleEvent() is essentially where the "process" logic is implemented. That logic (plus the event notification logic) should be moved to the stage class. The rest of the logic should still be part of the Scheduler class. Basically, the stage is only where we control the execution. It helps decoupling the actual feature from the process (i.e. how we use the feature/interact with the hardware components).

May 23 2018, 3:05 AM
andreadb added a comment to D47244: [llvm-mca] Add the RetireStage. .

On a second thought,
wouldn't it be better if we still keep the RetireControlUnit abstraction?
We can have that the RetireStage acts as a proxy for the RetireControlUnit.

May 23 2018, 2:51 AM
andreadb added a comment to D47246: [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class)..

Hi Matt,

May 23 2018, 2:43 AM
andreadb accepted D47244: [llvm-mca] Add the RetireStage. .

A couple of minor nits. Otherwise it LGTM too.

May 23 2018, 2:30 AM

May 22 2018

andreadb accepted D47213: [llvm-mca] Move DispatchStage::cycleEvent to preExecute. NFC..

LGTM.

May 22 2018, 12:37 PM

May 21 2018

andreadb updated the diff for D47077: [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling classes..

Address review comment.

May 21 2018, 5:46 AM
andreadb updated the diff for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..

Addressed review comments.

May 21 2018, 5:42 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 21 2018, 2:56 AM

May 18 2018

andreadb added inline comments to D47077: [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling classes..
May 18 2018, 10:03 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 9:32 AM
andreadb abandoned D46697: [RFC][Patch 1 and Patch 2 of 3] Teach how to resolve variant scheduling classes when using MCInst objects..

Abandoning in favor of D47077.

May 18 2018, 9:29 AM
andreadb created D47077: [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling classes..
May 18 2018, 9:28 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 7:10 AM
andreadb updated the diff for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..

Addressed review comment.

May 18 2018, 5:14 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 2:09 AM

May 17 2018

andreadb accepted D46983: [llvm-mca] Make Dispatch a subclass of Stage..
May 17 2018, 9:57 AM
andreadb added a comment to D46983: [llvm-mca] Make Dispatch a subclass of Stage..

LGTM too.

May 17 2018, 9:57 AM
andreadb added inline comments to D46907: [llvm-mca] Introduce a sequential container of Stages.
May 17 2018, 5:19 AM

May 16 2018

andreadb added inline comments to D46907: [llvm-mca] Introduce a sequential container of Stages.
May 16 2018, 1:56 AM
andreadb accepted D46916: [llvm-mca] Move the RegisterFile class into its own translation unit. NFC.

If the goal is to make the current DispatchUnit a DispatchStage, then this makes sense.

May 16 2018, 1:34 AM

May 15 2018

andreadb accepted D46741: [llvm-mca] Introduce a pipeline Stage class and FetchStage..

LGTM. Thanks!

May 15 2018, 10:59 AM
andreadb added a comment to D46741: [llvm-mca] Introduce a pipeline Stage class and FetchStage..

Thanks Matt,

May 15 2018, 3:26 AM

May 14 2018

andreadb updated the diff for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..

Addressed review comments.

May 14 2018, 8:56 AM
andreadb requested changes to D46741: [llvm-mca] Introduce a pipeline Stage class and FetchStage..

Hi Matt,

May 14 2018, 3:29 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 14 2018, 2:33 AM

May 11 2018

andreadb updated the diff for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..

Patch updated.

May 11 2018, 12:56 PM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 11 2018, 10:42 AM
andreadb updated the summary of D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 11 2018, 9:57 AM
andreadb updated the diff for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..

Patch updated.

May 11 2018, 9:57 AM
andreadb added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 11 2018, 6:12 AM
andreadb added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
May 11 2018, 6:09 AM
andreadb added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
May 11 2018, 3:21 AM

May 10 2018

andreadb updated the diff for D46698: [RFC][llvm-mca][patch 3/3] Add support for variant scheduling classes in llvm-mca..

Patch updated. Note that this patch still needs a test case.

May 10 2018, 10:31 AM
andreadb updated the summary of D46697: [RFC][Patch 1 and Patch 2 of 3] Teach how to resolve variant scheduling classes when using MCInst objects..
May 10 2018, 8:53 AM
andreadb updated the summary of D46697: [RFC][Patch 1 and Patch 2 of 3] Teach how to resolve variant scheduling classes when using MCInst objects..
May 10 2018, 8:53 AM
andreadb updated the summary of D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 10 2018, 8:49 AM
andreadb created D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
May 10 2018, 8:46 AM
andreadb created D46698: [RFC][llvm-mca][patch 3/3] Add support for variant scheduling classes in llvm-mca..
May 10 2018, 8:35 AM
andreadb created D46697: [RFC][Patch 1 and Patch 2 of 3] Teach how to resolve variant scheduling classes when using MCInst objects..
May 10 2018, 8:28 AM
andreadb created D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 10 2018, 8:23 AM

May 7 2018

andreadb added a comment to D46494: [DAGCombiner] Masked merge: enhance handling of 'andn' with immediates.

Fixed with the correct fold, updated mca diffs in the differential's description:

We need to be careful here (and maybe there's a way for mca to show/warn about this, cc @andreadb).

May 7 2018, 9:26 AM
andreadb accepted D46367: [llvm-mca] Avoid exposing index values in the MCA interfaces..

A few minor nits. Otherwise LGTM.

May 7 2018, 3:29 AM

May 6 2018

andreadb added a comment to D46367: [llvm-mca] Avoid exposing index values in the MCA interfaces..

Thanks Matt,

May 6 2018, 1:07 PM
andreadb added a comment to D46367: [llvm-mca] Avoid exposing index values in the MCA interfaces..

Hi Matt,

May 6 2018, 3:23 AM
andreadb requested changes to D46367: [llvm-mca] Avoid exposing index values in the MCA interfaces..
May 6 2018, 3:23 AM

May 5 2018

andreadb added a comment to D46493: [DagCombiner] Not all 'andn''s work with immediates..

I'd say this regression is an improvement, since IPC increased in that case?

As a rule of thumb when using llvm-mca, it's best to always remove return statements from the assembly code sequence.
llvm-mca should have warned you about the presence of a return statement in the input sequence:

warning: found a return instruction in the input assembly sequence.
note: program counter updates are ignored.

To get the correct resource pressure distribution in example icmp-opt.txt, you should remove the retq.

Thank you for your comments!
I will filter it out, so hopefully in future my mca expirience will be better :)

If you run multiple iterations and print the timeline view, you can see how the "average wait time" in the scheduler's queue is quite high for the shlq instruction.

Aha, so far i kinda ignored -timeline switch.
Those flags need work i think. I have just tried enabling them all, and it seems like they invert the current state?
I'd like to 1. have a switch to turn them all on, 2. maybe print which ones are currently enabled in -help

May 5 2018, 8:26 AM
andreadb added a comment to D46493: [DagCombiner] Not all 'andn''s work with immediates..

I'd say this regression is an improvement, since IPC increased in that case?

May 5 2018, 5:22 AM