andreadb (Andrea Di Biagio)
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May 9 2013, 11:10 AM (258 w, 4 d)

Recent Activity

Today

andreadb requested changes to D44782: Account for partial stack slot spills (PR30821).

Hi Jeremy.

Mon, Apr 23, 4:09 AM

Thu, Apr 19

andreadb updated subscribers of D45787: [llvm-exegesis] Fix PfmIssueCountersTable creation.

Hi Guillaume,

Thu, Apr 19, 2:04 AM

Wed, Apr 18

andreadb accepted D45666: [llvm-mca] Use WithColor for printing errors.

Really cool!

Wed, Apr 18, 7:57 AM

Wed, Apr 11

andreadb accepted D45404: [X86] Add variable shuffle schedule classes.

LGTM.

Wed, Apr 11, 3:07 AM

Mon, Apr 9

andreadb accepted D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

Thanks Andrea,

Nice patch.

Would it be difficult to have a single string table for all the PfmIssueCounters defined by the scheduling models?

The compressed table comes with the downside that it requires an extra mapping between processor resource IDs and indices to the string table. That mapping could be stored somewhere in the "ExtraInfo" table.

I hope this makes sense.

Makes sense, this is similar to how scheduling info is stored.
I guess that what we gain from doing this also depends on whether we really do split ExtraInfo to a separate target that only llvm-mca and llvm-exegesis link. If that's the case, then not compressing is not a big deal.

Overall, the patch looks good. I am also okay if you want to commit this patch first, and then improve the design in a follow-up patch.

I'd rather do it in a separate patch to keep matters separate if you don't mind.

Mon, Apr 9, 6:58 AM
andreadb added a comment to D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

Nice patch.

Mon, Apr 9, 6:17 AM
andreadb added inline comments to D45433: [llvm-mca] Add the ability to mark regions of code for analysis (PR36875).
Mon, Apr 9, 5:52 AM
andreadb updated the summary of D45433: [llvm-mca] Add the ability to mark regions of code for analysis (PR36875).
Mon, Apr 9, 4:01 AM
andreadb created D45433: [llvm-mca] Add the ability to mark regions of code for analysis (PR36875).
Mon, Apr 9, 3:58 AM

Fri, Apr 6

andreadb added a comment to D45369: [UpdateTestChecks] Add update_mca_test_checks.py script.

Thanks Greg.
I slightly changed some of the tests at r329403.
It should simplify the diff from your patch.

Fri, Apr 6, 8:56 AM
andreadb added a comment to D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

I think that (1) is as good as (2), because (2) will have to be something complex to handle all microarchitectures, so I'd rather leave this complexity to be dealt with by libpfm, which was designed for this very purpose.

I am a bit confused. Does it mean that exegesis will always have the dependency on libpfm (which means, it would only work on systems that provide it, for the cpus known by the installed lib version on the system)?

It does not *have to*, but until a better solution comes along, yes :) Just peeking at the tables in libpfm to abstract both OS and hardware really makes me want to not have to handle that !

Fri, Apr 6, 7:49 AM
andreadb added a comment to D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

Let's summarize what we need and how we can address those needs.

For each subtarget, we need to know:

  • How to count cycles.
  • How to count uops issued on each resource.

    There are two orthogonal technical aspects to decide on, which are how to name the counters, and where to store the mapping from subtarget/procres to abstract counter

    As for naming counters, the options that have been cited up to now are: 1 - (this design and Andrea's proposal) counters are identified by an abstract string (I happened to pick the libpfm convention, because that's the lib we've used). 2 - (raw counters) counters are identified by the architecture-specific id, which is an int on Intel but could be a something else on other architectures.

    I think that (1) is as good as (2), because (2) will have to be something complex to handle all microarchitectures, so I'd rather leave this complexity to be dealt with by libpfm, which was designed for this very purpose.
Fri, Apr 6, 7:23 AM
andreadb added a comment to D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

I'm a bit worried about creating a pfm dependency like this in the core - pfm doesn't come close to covering all targets that we'll want to check in the long term so it's likely that some targets will require a different library. (or raw msrs.....)

Is there anyway that we can keep more of this in llvm-exegesis project - config files or embedding in source?

Fri, Apr 6, 6:29 AM
andreadb added a comment to D45360: [MC][TableGen] Add optional libpfm counter names for ProcResUnits..

Hi Clement,

Fri, Apr 6, 4:50 AM
andreadb accepted D45272: [UpdateTestChecks] Add update_analyze_test_checks.py for cost model analysis generation.

I like this version of the script. The output is easier to read now that you removed all the needless tablegen variables with regexpr.
I don't have a strong opinion on which version to use for this script (whether python 2.7 or 3).
So, the script looks good to me.

Fri, Apr 6, 4:41 AM
andreadb accepted D45351: [X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs.

Nice cleanup!

Fri, Apr 6, 2:47 AM

Thu, Apr 5

andreadb updated subscribers of D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..

I am going to fix it now.
I guess I should have used int64_t ...

Thu, Apr 5, 8:54 AM
andreadb added a comment to D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..

Thanks Simon.

Thu, Apr 5, 8:02 AM
andreadb added inline comments to D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..
Thu, Apr 5, 6:32 AM
andreadb updated the diff for D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..

Patch updated.

Thu, Apr 5, 6:05 AM
andreadb accepted D43235: [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639) (WIP).

ping^2

Thu, Apr 5, 3:56 AM
andreadb added a comment to D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..

Why did the tests change ? I thought that this change would not impact tests.

Thu, Apr 5, 3:00 AM
andreadb added inline comments to D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..
Thu, Apr 5, 2:47 AM

Wed, Apr 4

andreadb created D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca..
Wed, Apr 4, 7:57 AM

Tue, Apr 3

andreadb updated the diff for D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca.

Patch updated.

Tue, Apr 3, 5:07 AM
andreadb added inline comments to D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca.
Tue, Apr 3, 4:55 AM
andreadb accepted D44519: Add llvm-exegesis tool..

The major problem I see is that the tool expects perf event "UNHALTED_CORE_CYCLES" to be always available. However, that event is Intel specific.
I tried to manually change it to something meaningful for my system. However, it would be really nice if we find a way to abstract "generic perf events".
For example, we could have the "generic cpu clock" event, which targets/subtargers can define as a alias for a specific hw event type. So, on Intel chips, that "generic cpu clock" event would be wired to UNHALTED_CORE_CYCLES. Is there a plan for doing it?

If you look at the code where the event is defined, there is a TODO to get the name of the event from the sched model (or resource Resource Unit for uops). Our plan is to add the name of the counters to use as an optional property of the SchedModel in TD files.

Tue, Apr 3, 3:59 AM
andreadb added inline comments to D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca.
Tue, Apr 3, 3:38 AM
andreadb added a comment to D44519: Add llvm-exegesis tool..

Hi Clement,

Tue, Apr 3, 3:09 AM

Thu, Mar 29

andreadb added a comment to D44726: [X86] Add ReadAfterLds to some 3 src instructions.

@andreadb does this one look ok? Ignoring that the InstRWs in the scheduler models drop the ReadAdvances anyway.

Thu, Mar 29, 2:21 PM
andreadb accepted D44726: [X86] Add ReadAfterLds to some 3 src instructions.

It looks good to me.

Thu, Mar 29, 2:20 PM
andreadb accepted D44836: [X86] Remove ReadAfterLd from BMI and TBM instructions that don't have a register operand in their memory form.
Thu, Mar 29, 2:00 PM
andreadb added a comment to D44836: [X86] Remove ReadAfterLd from BMI and TBM instructions that don't have a register operand in their memory form.

LGTM

Thu, Mar 29, 2:00 PM
andreadb accepted D44838: [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI.

About the bzhi/bextr change:
Your new patch looks good to me.

Thu, Mar 29, 1:27 PM
andreadb added a comment to D44838: [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI.

So basically the Intel per instruction overrides have broken every instruction with a folded load because we lost the ReadAfterLd on all of them?

For example
[0,0] DeER . . addl %edi, %esi
[0,1] D=eeeeeeER addl (%rdi), %esi

Thu, Mar 29, 1:20 PM
andreadb added inline comments to D44838: [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI.
Thu, Mar 29, 8:54 AM
andreadb added a comment to D44838: [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI.

Hi Craig.

Thu, Mar 29, 8:15 AM
andreadb added a comment to D44972: [X86] Add SchedRW for PMULLD.

The btver2 change looks good to me. Thanks!

Thu, Mar 29, 2:40 AM

Wed, Mar 28

andreadb created D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca.
Wed, Mar 28, 8:23 AM

Mon, Mar 26

andreadb added a comment to D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).

Thanks Clement,

Mon, Mar 26, 4:57 AM

Mar 24 2018

andreadb updated the diff for D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).

Patch updated.

Mar 24 2018, 9:16 AM
andreadb added a comment to D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).

Thanks Simon

Mar 24 2018, 8:24 AM

Mar 23 2018

andreadb updated the diff for D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).

Patch updated.

Mar 23 2018, 11:58 AM
andreadb updated subscribers of D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).
Mar 23 2018, 11:50 AM
andreadb created D44839: [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874).
Mar 23 2018, 11:43 AM

Mar 21 2018

andreadb closed D44741: [llvm-mca] Move the logic that computes the register file usage to the BackendStatistics view..

Thanks.
Committed revision 328129.

Mar 21 2018, 11:14 AM
andreadb updated the diff for D44741: [llvm-mca] Move the logic that computes the register file usage to the BackendStatistics view..

Patch updated.

Mar 21 2018, 10:53 AM
andreadb created D44741: [llvm-mca] Move the logic that computes the register file usage to the BackendStatistics view..
Mar 21 2018, 9:24 AM

Mar 20 2018

andreadb updated the diff for D44686: [llvm-mca] Move the logic that computes the scheduler's queue usage to the BackendStatistics view..

Patch updated.

Mar 20 2018, 11:09 AM
andreadb added a comment to D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP).

The changes to CodeGenSchedule.cpp looks good to me. I will let other people review the AArch64/ARM scheduling model changes.
P.s.: I also like the idea of having a warning (at least in debug mode) for when there is only one matching instruction.

Mar 20 2018, 10:05 AM
andreadb created D44686: [llvm-mca] Move the logic that computes the scheduler's queue usage to the BackendStatistics view..
Mar 20 2018, 9:15 AM
andreadb updated the diff for D44636: [Release Notes] Add release note for llvm-mca.

Hi Hans,

Mar 20 2018, 3:06 AM

Mar 19 2018

andreadb updated the diff for D44636: [Release Notes] Add release note for llvm-mca.

Addressed review comments.

Mar 19 2018, 1:47 PM
andreadb created D44636: [Release Notes] Add release note for llvm-mca.
Mar 19 2018, 10:28 AM
andreadb added inline comments to D44621: [llvm-mca] Add pipeline stall events..
Mar 19 2018, 5:38 AM
andreadb created D44621: [llvm-mca] Add pipeline stall events..
Mar 19 2018, 4:06 AM

Mar 16 2018

andreadb updated the diff for D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..

Patch updated.
Forgot to add a string message to the new asserts.

Mar 16 2018, 3:02 PM
andreadb updated the diff for D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..

Patch updated.
Address review comments.

Mar 16 2018, 11:24 AM

Mar 15 2018

andreadb updated the diff for D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..

Patch updated.
Please let me know what you think.

Mar 15 2018, 10:26 AM
andreadb added a comment to D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..

Jaguar treats 1 ymm logical as (upto) 2 x 128-bit physical entries - real world perf effect is minimal, but it does mean that it performs (upto) 2 read/writes into the PRF. 128-bit physicals that are known zero don't take up an PRF entry and the read/write should be quicker.

Mar 15 2018, 10:20 AM
andreadb added a comment to D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..

Thanks for the feedback.

Mar 15 2018, 10:17 AM

Mar 14 2018

andreadb created D44488: [llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files..
Mar 14 2018, 12:15 PM

Mar 13 2018

andreadb accepted D44309: [llvm-mca] Refactor event listeners to make the backend agnostic to event types..

Thanks Clement!

Mar 13 2018, 3:29 AM

Mar 12 2018

andreadb created D44392: [MC] Move the reciprocal throughput computation from TargetSchedModel to MCSchedModel..
Mar 12 2018, 9:24 AM
andreadb created D44383: [MC] Move the instruction latency computation from TargetSchedModel to MCSchedModel..
Mar 12 2018, 7:18 AM
andreadb added inline comments to D44309: [llvm-mca] Refactor event listeners to make the backend agnostic to event types..
Mar 12 2018, 5:19 AM

Mar 10 2018

andreadb added a comment to D44354: [lldb] Unbreak lldb builds due to r327219.

If this patch is to unbreak the buildbots, then I think you should just commit it.
We don't want to leave the buildbots in a failing state for too long.

Mar 10 2018, 1:12 PM · Restricted Project

Mar 9 2018

andreadb added a comment to D44309: [llvm-mca] Refactor event listeners to make the backend agnostic to event types..

Thanks Clement.

Mar 9 2018, 9:47 AM
andreadb added a reviewer for D44309: [llvm-mca] Refactor event listeners to make the backend agnostic to event types.: andreadb.
Mar 9 2018, 8:56 AM

Mar 7 2018

andreadb added a comment to D43951: [RFC] llvm-mca: a static performance analysis tool..

LGTM - as discussed in the summary, committing the llvm core changes separately prior to the llvm-mca addition. Then the further work discussed on the llvm-dev rfc can begin, and it should make it easier for others to investigate the tool themselves and propose patches (and find bugs....).

Mar 7 2018, 5:34 AM

Mar 6 2018

andreadb updated the diff for D43951: [RFC] llvm-mca: a static performance analysis tool..

Patch updated.

Mar 6 2018, 4:38 AM

Mar 5 2018

andreadb added inline comments to D43951: [RFC] llvm-mca: a static performance analysis tool..
Mar 5 2018, 8:50 AM
andreadb updated the diff for D43951: [RFC] llvm-mca: a static performance analysis tool..

Patch updated.

Mar 5 2018, 8:45 AM
andreadb updated the diff for D43951: [RFC] llvm-mca: a static performance analysis tool..

Patch updated.

Mar 5 2018, 8:17 AM
andreadb added inline comments to D43951: [RFC] llvm-mca: a static performance analysis tool..
Mar 5 2018, 2:19 AM
andreadb added a comment to D43951: [RFC] llvm-mca: a static performance analysis tool..

This is great! I always wanted to see a IACTA like tool for other architectures.

Mar 5 2018, 1:56 AM

Mar 2 2018

andreadb updated the diff for D43951: [RFC] llvm-mca: a static performance analysis tool..

Patch updated. Addressed review comments from Brian.

Mar 2 2018, 5:51 AM
andreadb added a comment to D43951: [RFC] llvm-mca: a static performance analysis tool..

Hi Clement,

Mar 2 2018, 5:46 AM
andreadb updated subscribers of D43951: [RFC] llvm-mca: a static performance analysis tool..
Mar 2 2018, 5:16 AM
andreadb added a comment to D43951: [RFC] llvm-mca: a static performance analysis tool..

Thanks Brian for the feedback!

Mar 2 2018, 3:30 AM

Mar 1 2018

andreadb added reviewers for D43951: [RFC] llvm-mca: a static performance analysis tool.: craig.topper, atrick, qcolombet.
Mar 1 2018, 9:30 AM
andreadb updated the summary of D43951: [RFC] llvm-mca: a static performance analysis tool..
Mar 1 2018, 9:27 AM
andreadb added a reviewer for D43951: [RFC] llvm-mca: a static performance analysis tool.: courbet.
Mar 1 2018, 9:26 AM
andreadb created D43951: [RFC] llvm-mca: a static performance analysis tool..
Mar 1 2018, 9:15 AM

Nov 9 2017

andreadb accepted D39726: [X86] Attempt to match multiple binary reduction ops at once. NFCI.

I made a couple of (minor) comments below.

Nov 9 2017, 5:28 AM
andreadb accepted D39728: Add -print-schedule scheduling comments to inline asm.

LGTM.

Nov 9 2017, 4:27 AM
andreadb accepted D39802: Sched model improving on btver2: JFPU01 resource, vtestp* for xmm..

I made updates required by andreadb except the question about JFPU01: if we need perf experiments please help me with perf test(s). If we agree to use the current implementation then I could commit the patch if you get me LGTM.

Nov 9 2017, 4:19 AM

Nov 8 2017

andreadb added inline comments to D39802: Sched model improving on btver2: JFPU01 resource, vtestp* for xmm..
Nov 8 2017, 10:24 AM
andreadb added a comment to D39728: Add -print-schedule scheduling comments to inline asm.

Overall, the patch looks good to me.
I made some minor comments below.

Nov 8 2017, 9:40 AM

Oct 23 2017

andreadb accepted D39169: [X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI..

Lgtm.

Oct 23 2017, 7:39 AM
andreadb accepted D38696: [DAGCombine] Permit combining of shuffle of equivalent splat BUILD_VECTORs.

LGTM.
Thanks Simon!

Oct 23 2017, 6:17 AM

Oct 12 2017

andreadb added inline comments to D38696: [DAGCombine] Permit combining of shuffle of equivalent splat BUILD_VECTORs.
Oct 12 2017, 11:44 AM

Aug 29 2017

andreadb updated subscribers of D36617: AMD Zen Scheduler Model Update.

I noticed that you forgot to include llvm-commits as a subscriber.

Aug 29 2017, 4:45 AM

May 12 2017

andreadb accepted D32563: Add LiveRangeShrink pass to shrink live range within BB..

Thanks for fixing the issue with debug values.

May 12 2017, 3:55 AM

May 11 2017

andreadb accepted D32563: Add LiveRangeShrink pass to shrink live range within BB..

Accepting this now as it looks reasonably safe and fast to me (nitpicks below).

It is a conservative/simple heuristic but given the fact that we lack other means of global code motion (in the sense of inter-basic block) in CodeGen today this is fine.

Please wait for some of the other reviewers which showed interest here to accept before committing.

May 11 2017, 11:09 AM
andreadb added a comment to D32563: Add LiveRangeShrink pass to shrink live range within BB..

Currently, we set 'SawStore' if there is at least one 'mayStore' instruction in the scheduling region.

May 11 2017, 6:26 AM

May 10 2017

andreadb added inline comments to D32563: Add LiveRangeShrink pass to shrink live range within BB..
May 10 2017, 12:22 PM

May 9 2017

andreadb added inline comments to D32563: Add LiveRangeShrink pass to shrink live range within BB..
May 9 2017, 5:55 AM

May 8 2017

andreadb accepted D32770: [X86][LWP] Add clang support for LWP instructions..

LGTM.

May 8 2017, 3:52 AM

May 5 2017

andreadb added a comment to D32563: Add LiveRangeShrink pass to shrink live range within BB..

Sorry, did not address this in the last patch. Done now. Note that I do not want to touch unnecessary files in this change. So I simply copied the code from MachineSink.cpp, and will refactor it to a utility function in MachineInstr.h/.cpp in a follow-up patch.

May 5 2017, 11:52 AM