andreadb (Andrea Di Biagio)
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May 9 2013, 11:10 AM (283 w, 5 d)

Recent Activity

Fri, Oct 12

andreadb added a comment to D53055: [MCA] Limit the number of bytes fetched per cycle..

Now that llvm-mca is a library, people can define their own custom pipeline without having to modify the "default pipeline stages".
In particular, I don't want to introduce any frontend concepts in the default pipeline of llvm-mca.
For now, any frontend simulation should be implemented by stages that are not part of the default pipeline.

I don't have a particular opinion about whether this should be part of the default pipeline or not, but I think modeling the frontend is very important.
This article from a couple years ago analyzes the typical workloads on a google datacenter. While most of the stalls are from the backend, the frontend has a significant contribution:

Fri, Oct 12, 3:36 AM

Thu, Oct 11

andreadb added inline comments to D53134: [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen..
Thu, Oct 11, 11:32 AM
andreadb added a comment to D53055: [MCA] Limit the number of bytes fetched per cycle..

Hi Andrea,

There is already bug https://bugs.llvm.org/show_bug.cgi?id=36665, which is about adding support for simulating the hardware frontend logic.
I know that @courbet and his team would like to work on it. So, you can probably try to work with them on this.
Unfortunately, that bugzilla must be updated. There is not enough information there (I suggested to send a detailed RFC upstream in case).

I strongly suggest you/your team/Clement's team to work together on that task. I am afraid that people may be working on the same tasks in parallel.. That has to be avoided.
You can use that bugzilla to coordinate your work upsteam on this.

Let me clarify this: Owen is working with us :) He has taken over the genetic scheduler work I presented at EuroLLVM. One of the bottlenecks we had was the frontend hence the change. I agree that this should have been made clearer (@owenrodley, can you create a bugzilla account and assign the bug to yourself ?)

Thu, Oct 11, 9:44 AM
andreadb accepted D53095: [x86] add and use fast horizontal vector math subtarget feature.

Thanks Sanjay!

Thu, Oct 11, 8:53 AM
andreadb updated the diff for D53134: [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen..

Patch updated:

Thu, Oct 11, 8:09 AM
andreadb created D53134: [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen..
Thu, Oct 11, 5:26 AM

Wed, Oct 10

andreadb added reviewers for D53055: [MCA] Limit the number of bytes fetched per cycle.: courbet, gchatelet, RKSimon, atrick.

Hi Owen,

Wed, Oct 10, 3:23 AM

Tue, Oct 9

andreadb added a comment to D52932: [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel..

Thanks for the description Clement,

Tue, Oct 9, 7:56 AM
andreadb added a comment to D52997: [x86] allow single source horizontal op matching (PR39195).

So 2 options for moving forward:

  1. Allow this transform as shown here because it is mostly just restoring the behavior of last week. Follow that up with a subtarget feature to prevent the transform (not ideal, but the alternative 'undo' is much harder).
  2. Limit this transform to 'optsize' right now because it's a size win in all cases.

I'd vote for (1) for this patch - optsize + HasFastHorinzontalOp might be necessary depending on how soon we can agree on a scheduler model driven mechanism that re-expands HADD later on (per Andrea's suggestion - but hopefully we can discuss that at the devmtg)

Tue, Oct 9, 5:35 AM
andreadb added a comment to D52932: [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel..

Thanks for waiting Clement.

Tue, Oct 9, 4:27 AM
andreadb added a comment to D52997: [x86] allow single source horizontal op matching (PR39195).

Hi Sanjay,

Tue, Oct 9, 3:23 AM

Fri, Oct 5

andreadb added a comment to D52932: [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel..

I’m not at work today, but I’d like a bit of time to review this patch.

Fri, Oct 5, 8:03 AM
andreadb added inline comments to D52779: AMD BdVer2 (Piledriver) Initial Scheduler model.
Fri, Oct 5, 4:07 AM

Thu, Oct 4

andreadb added a comment to D52886: [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957).

Thanks Simon!

Thu, Oct 4, 8:06 AM
andreadb added a comment to D52779: AMD BdVer2 (Piledriver) Initial Scheduler model.

Hi Roman,

Thu, Oct 4, 5:59 AM

Mon, Oct 1

andreadb accepted D46662: [X86] condition branches folding for three-way conditional codes.

Thanks.
I don’t have other comments.

Mon, Oct 1, 12:24 PM

Sat, Sep 29

andreadb updated the diff for D52663: [X86][BtVer2] Teach how to identify zero-idio VPERM2F128rr instructions..

Addressed review comments.

Sat, Sep 29, 6:48 AM
andreadb added a comment to D46662: [X86] condition branches folding for three-way conditional codes.
In D46662#1248780, @xur wrote:

Using new SubtargetFeature method (suggested by Andrea) to make this pass opt-in for subtargets.
Changed the tests accordingly.

Sat, Sep 29, 6:45 AM

Fri, Sep 28

andreadb retitled D52663: [X86][BtVer2] Teach how to identify zero-idio VPERM2F128rr instructions. from [X86][BtVer2] VPERM2F128rr instructions with Mask bits 3 and 7 are also zero-idioms. to [X86][BtVer2] Teach how to identify zero-idio VPERM2F128rr instructions..
Fri, Sep 28, 11:00 AM
andreadb created D52663: [X86][BtVer2] Teach how to identify zero-idio VPERM2F128rr instructions..
Fri, Sep 28, 10:58 AM
andreadb accepted D52642: [MCA] Remove SM.hasNext() call in FetchStage::execute..

LGTM.

Fri, Sep 28, 1:18 AM

Thu, Sep 27

andreadb accepted D52603: Split invocations in CodeGen/X86/cpus.ll among multiple tests. (NFC).

LGTM. Thanks!

Thu, Sep 27, 9:50 AM
andreadb added a comment to D52570: [X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR.

Forgot to mention that BEXTR breaks the two addressness of the shift+and pattern to avoid a copy which can also be beneficial. Unfortunately isel can't generally determine that a copy will be needed.

I agree, I don't really want to add a new fast/slow flag either.

Thu, Sep 27, 6:18 AM

Wed, Sep 26

andreadb updated subscribers of D46662: [X86] condition branches folding for three-way conditional codes.
In D46662#1246781, @xur wrote:

Hi Andrea,

Thanks for running this test, and the explanation. Can you run the tests
on Bulldozer/Ryzen? I don't have access to these platforms. If I need to do
this in subtarget way, it would be good to know the performance there.

Wed, Sep 26, 10:13 AM
andreadb accepted D52560: [utils] Allow better identification of matching blocks in update_mca_test_checks.py.

LGTM.

Wed, Sep 26, 9:57 AM
andreadb accepted D48276: [llvm-mca] Stricter checking from update_mca_test_checks.py.

Thanks Greg.

Wed, Sep 26, 9:57 AM
andreadb added a comment to D46662: [X86] condition branches folding for three-way conditional codes.

What is the definition of branch density?

Wed, Sep 26, 9:44 AM
andreadb added a comment to D46662: [X86] condition branches folding for three-way conditional codes.

Hi Rong,

Wed, Sep 26, 6:54 AM

Tue, Sep 25

andreadb added a comment to D46662: [X86] condition branches folding for three-way conditional codes.

Nice! This looks good, ping @RKSimon for more suggestions, if any :)

Tue, Sep 25, 12:27 PM
andreadb accepted D52318: [x86] avoid 256-bit andnp that requires insert/extract with AVX1 (PR37449).

Thanks Sanjay.

Tue, Sep 25, 10:24 AM

Fri, Sep 21

andreadb added inline comments to D51553: [DAGCombiner][x86] add transform/hook to load a scalar directly for use in a vector binop.
Fri, Sep 21, 10:20 AM
andreadb added a comment to D52318: [x86] avoid 256-bit andnp that requires insert/extract with AVX1 (PR37449).

Hi Sanjay,

Fri, Sep 21, 7:37 AM
andreadb accepted D52358: [X86][Sched] Add zero idiom sched data to the SNB model..
On SNB, renamer-based zeroing does not work for:
Fri, Sep 21, 7:02 AM
andreadb added inline comments to D52347: [X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms..
Fri, Sep 21, 4:34 AM
andreadb created D52347: [X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms..
Fri, Sep 21, 2:56 AM

Thu, Sep 20

andreadb accepted D52288: [MCA] Remove dependency on CodeGen..

LGTM. Thanks!

Thu, Sep 20, 12:48 AM

Wed, Sep 19

andreadb updated the diff for D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..

Address review comments.

Wed, Sep 19, 5:22 AM
andreadb added inline comments to D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..
Wed, Sep 19, 5:02 AM

Tue, Sep 18

andreadb updated the diff for D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..

Patch rebased.

Tue, Sep 18, 8:32 AM
andreadb updated the diff for D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..

Patch updated.

Tue, Sep 18, 5:32 AM
andreadb accepted D51839: [TableGen] CodeGenDAGPatterns::GenerateVariants - full caching of matching predicates.

LGTM.

Tue, Sep 18, 3:13 AM

Mon, Sep 17

andreadb updated the diff for D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..

Patch updated.

Mon, Sep 17, 9:56 AM
andreadb added inline comments to D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..
Mon, Sep 17, 9:33 AM
andreadb created D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions..
Mon, Sep 17, 7:39 AM

Sep 11 2018

andreadb accepted D51903: [llvm-mca] Delay calculation of Cycles per Resources, separate the cycles and resource quantities..

LGTM.

Sep 11 2018, 9:59 AM
andreadb updated subscribers of D51903: [llvm-mca] Delay calculation of Cycles per Resources, separate the cycles and resource quantities..

I noticed that you forgot to add llvm-commits to the subscribers list.
Adding it now.

Sep 11 2018, 4:15 AM
andreadb added a comment to D51903: [llvm-mca] Delay calculation of Cycles per Resources, separate the cycles and resource quantities..

Hi Matt,

Sep 11 2018, 3:43 AM

Sep 3 2018

andreadb added a comment to D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.

There seems to be 2 things here - (1) ReadAfterLd is being used incorrectly to try to make a dependency on the dst reg and (2) we have no mechanism to handle partial dependencies like for the scalar sse instructions.

AFAICT this patch fixes the (1) issue but (2) isn't handled at all by the scheduler models yet.

Yep.

I will raise a bug for 2. This patch only addresses the issue with ReadAfterLd being incorrectly applied to a register used as the base address of the folded load.

Raised bug https://bugs.llvm.org/show_bug.cgi?id=38813.

Thanks! I think everyone agrees that the ReadAfterLd is not behaving as intended on the SSE instructions. I am still wondering about the AVX case (and the SSE intrinsic is the same?):
As noted, this is testing with llvm-mca with skylake CPU:

With ReadAfterLd:

[0,0]     DeeeeeeeeeER   .   vdppd	$1, %xmm0, %xmm1, %xmm2
[0,1]     D=eE-------R   .   leaq	8(%rsp,%rdi,2), %rax
[0,2]     D====eeeeeeeeeER   vrsqrtss	(%rax), %xmm2, %xmm3  <--- execution delayed by vdppd?

No ReadAfterLd:

[0,0]     DeeeeeeeeeER   .    .   vdppd	$1, %xmm0, %xmm1, %xmm2
[0,1]     D=eE-------R   .    .   leaq	8(%rsp,%rdi,2), %rax
[0,2]     D=========eeeeeeeeeER   vrsqrtss	(%rax), %xmm2, %xmm3   <--- execution delayed until xmm2 is known

Do we have confirmation from hardware testing or Intel docs that the 1st timeline is correct? We can punt this question to another patch to not delay this one if needed, but I'd like to understand what the hardware does in this case.

Sep 3 2018, 7:29 AM
andreadb added a comment to D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.

There seems to be 2 things here - (1) ReadAfterLd is being used incorrectly to try to make a dependency on the dst reg and (2) we have no mechanism to handle partial dependencies like for the scalar sse instructions.

AFAICT this patch fixes the (1) issue but (2) isn't handled at all by the scheduler models yet.

Yep.

I will raise a bug for 2. This patch only addresses the issue with ReadAfterLd being incorrectly applied to a register used as the base address of the folded load.

Sep 3 2018, 6:34 AM
andreadb added a comment to D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.

There seems to be 2 things here - (1) ReadAfterLd is being used incorrectly to try to make a dependency on the dst reg and (2) we have no mechanism to handle partial dependencies like for the scalar sse instructions.

AFAICT this patch fixes the (1) issue but (2) isn't handled at all by the scheduler models yet.

Sep 3 2018, 4:06 AM

Aug 31 2018

andreadb added a comment to D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.

Hi Sanjay,

Thanks for the feedback.

I think this requires an understanding of the intent of ReadAfterLd:

// Instructions with folded loads need to read the memory operand immediately,
// but other register operands don't have to be read until the load is ready.
// These operands are marked with ReadAfterLd.

...that D51534 did not. That's because a broadcast only has one source operand, so ReadAfterLd doesn't even make sense on that instruction?

Not only it didn't make any sense. It was even harmful because it was decreasing the use latency of the register used as the base address for the folded load by 'ReadAfterLd' cycles..

In this case, we have 2 source operands:

  1. The loaded value that we're doing the math on.
  2. The unchanging vector lanes of the second source (destination) register.

I think you are getting confused. These are not instructions with 2 input operands.
These are just SSE1/SSE2 unary operations (one def, and one use; see below the tablegen definition).

Aug 31 2018, 4:13 PM
andreadb added a comment to D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.

Hi Sanjay,

Aug 31 2018, 3:45 PM
andreadb added a reviewer for D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s: spatel.
Aug 31 2018, 8:46 AM
andreadb created D51542: [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.
Aug 31 2018, 7:56 AM
andreadb created D51534: [X86][BtVer2] Remove wrong ReadAdvance from AVX vbroadcast(ss|sd|F128) instructions..
Aug 31 2018, 4:23 AM

Aug 30 2018

andreadb updated the diff for D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info..

Patch updated with a fix for the throughput information for VBROADCASTF128.

Aug 30 2018, 11:10 AM
andreadb added a comment to D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info..

I don't see any changes for VEXTRACTF128 in tests. Do you really need this JWriteVecExtractF128? If YES you should add the corresponding test.

Aug 30 2018, 10:07 AM
andreadb created D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info..
Aug 30 2018, 9:01 AM

Aug 29 2018

andreadb created D51430: [llvm-mca] Report the number of dispatched micro opcodes in the DispatchStatistics view..
Aug 29 2018, 8:33 AM

Aug 27 2018

andreadb accepted D50929: [llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC..

Hi Matt.

Aug 27 2018, 3:56 AM

Aug 23 2018

andreadb added a comment to rL340536: [llvm-mca] Allow the definition of custom strategies for selecting processor….

It should be fixed now at revision 340545.

I am going to run some tests to see if there are other issues with the implementation (hopefully not..).

Thanks @waltl for reporting it!

Aug 23 2018, 12:07 PM
andreadb added a comment to rL340536: [llvm-mca] Allow the definition of custom strategies for selecting processor….

It should be fixed now at revision 340545.

Aug 23 2018, 10:11 AM
andreadb added inline comments to rL340536: [llvm-mca] Allow the definition of custom strategies for selecting processor….
Aug 23 2018, 9:47 AM
andreadb added inline comments to D46276: [CostModel][X86] Derive TTI costs from complete scheduling models (PR36550) (RFC).
Aug 23 2018, 7:34 AM
andreadb added a comment to D46276: [CostModel][X86] Derive TTI costs from complete scheduling models (PR36550) (RFC).

Hi Simon,

Aug 23 2018, 6:32 AM

Aug 21 2018

andreadb created D51051: [llvm-mca] Add the ability to customize the instruction selection strategy in the Scheduler..
Aug 21 2018, 10:45 AM
andreadb updated subscribers of D50839: [llvm] Make YAML serialization up to 2.5 times faster.

Right.
I was mainly concerned about the assert. Thanks for fixing it! :-)

Aug 21 2018, 2:50 AM

Aug 20 2018

andreadb added a comment to D50929: [llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC..

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

Aug 20 2018, 9:09 AM
andreadb added a comment to D50839: [llvm] Make YAML serialization up to 2.5 times faster.

Hi Kirill,

Aug 20 2018, 2:58 AM

Aug 16 2018

andreadb updated the diff for D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.

Addressed review comments.

Aug 16 2018, 11:12 AM
andreadb added a comment to D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.

Hi Matt,

Aug 16 2018, 10:57 AM
andreadb created D50849: [llvm-mca] Refactor how execution is orchestrated by the Pipeline. NFCI.
Aug 16 2018, 10:04 AM

Aug 15 2018

andreadb added a comment to D50745: [llvm-mca] Update the comments for the mca:::Stage class. NFC..

Hi Matt,

Aug 15 2018, 4:10 AM

Aug 14 2018

andreadb updated the diff for D50708: [Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates in CodeGenSchedule.cpp..

Thanks for the review Matt.

Aug 14 2018, 11:13 AM
andreadb created D50708: [Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates in CodeGenSchedule.cpp..
Aug 14 2018, 8:06 AM

Aug 13 2018

andreadb accepted D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..

LGTM. Thanks!

Aug 13 2018, 10:51 AM
andreadb added inline comments to D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..
Aug 13 2018, 10:19 AM
andreadb added inline comments to D50566: [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class..
Aug 13 2018, 4:03 AM
andreadb added a comment to D50561: [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver..

Added Stage::Status type alias to clean up the return value for Stage::execute. The previous iteration of this patch used an Expected<bool>, which I find confusing. This change makes the code more readable.

Aug 13 2018, 3:42 AM

Aug 10 2018

andreadb created D50566: [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class..
Aug 10 2018, 9:55 AM

Aug 9 2018

andreadb accepted D50328: [X86][SSE] Combine (some) target shuffles with multiple uses.

The change to combinePMULDQ() should be committed as a separate patch (as suggested by you and David).

Aug 9 2018, 3:21 AM

Aug 8 2018

andreadb added inline comments to D50457: [MC][PredicateExpander] Extend the grammar to support simple switch and return statements..
Aug 8 2018, 10:12 AM
andreadb created D50457: [MC][PredicateExpander] Extend the grammar to support simple switch and return statements..
Aug 8 2018, 9:40 AM

Aug 6 2018

andreadb created D50333: [Tablegen] In TargetSchedule.td: Remove unused argument `pfmCounters` from ProcResourceUnits..
Aug 6 2018, 6:48 AM

Jul 31 2018

andreadb updated the diff for D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Patch updated.

Jul 31 2018, 3:43 AM

Jul 30 2018

andreadb updated the diff for D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..

Patch rebased and updated.

Jul 30 2018, 7:26 AM
andreadb accepted D49692: [llvm-mca][docs] Add instruction flow documentation. NFC..

Hi Matt,

Jul 30 2018, 3:49 AM

Jul 21 2018

andreadb accepted D49614: [llvm-mca][docs] Add documentation for the statistic outputs from mca. NFC.

LGTM. Thanks!

Jul 21 2018, 12:49 AM

Jul 20 2018

andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:54 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:40 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 8:23 AM
andreadb added inline comments to D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms..
Jul 20 2018, 7:43 AM

Jul 19 2018

andreadb accepted D49527: [llvm-mca][docs] Describe the Timeline View. NFC.

Overall, it looks good to me.

As you wrote, the "VIEW DESCRIPTIONS" section should be improved.
Also, it should probably have a more informative/different name (not sure which one though... I am not good with names).

Jul 19 2018, 7:52 AM
andreadb updated the diff for D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

Patch updated.

Jul 19 2018, 5:48 AM
andreadb added reviewers for D49527: [llvm-mca][docs] Describe the Timeline View. NFC: gbedwell, courbet, filcab.

Overall, it looks good to me.

Jul 19 2018, 4:04 AM

Jul 18 2018

andreadb updated the diff for D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

Patch updated.

Jul 18 2018, 5:33 AM
andreadb added a comment to D49393: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers..

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

That is because on x86-64, a write to EAX implicitly zeroes the upper half or RAX. So, there is no false dependency with previous values of RAX, and - for the purpose of mca - EAX renames as RAX. See also the definition of X86CInstrAnalysis::clearsSuperRegisters() in the X86 Backend (X86/MCTargetDesc/X86MCTargetDesc.cpp).

Right, thank you, so this already works as-is; Should i keep the test?

Jul 18 2018, 4:15 AM
andreadb added a comment to D49393: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers..

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

Jul 18 2018, 4:00 AM
andreadb added a comment to D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..

I think it makes sense to have a separate patch for checkInvalidRegOperand. I do like that idea in particular, it simplifies reading the tablegen sources.

Jul 18 2018, 3:11 AM

Jul 17 2018

andreadb created D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions..
Jul 17 2018, 10:37 AM